First Int. Workshop on Power Supply On Chip (PowerSoC08), Sept. 22-24, 2008, Cork, Ireland
Ultrahigh-density (> 0.4 µF/mm2)
trench capacitors in silicon
F. Roozeboom1,2, W. Dekkers1, K. Jinesh1, W. Besling1,
Y. Lamy1, J. Klootwijk3, M. Verheijen3, H.-D. Kim4 and D. Blin4
1 NXP-TSMC
Research Center, 2 TU Eindhoven,3 Philips Research, Eindhoven, The Netherlands
4 Jusung Engineering, Korea and France
Outline
• Introduction
• ‘Moore than Moore’ vs. ‘More Moore / Beyond’
• Conventional MOS trench capacitors for decoupling
– ONO / (poly)-Si stacks
• NXP Roadmap for 3D System-in-Package (SiP)
– From MOS to MIM capacitors from ~25 to 400 nF/mm2
• ALD of multiple high-k MIM (TiN / Al2O3 / TiN)
• Growth and processing
• Structural and electrical characterization
• Concluding remarks
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
2
Outline
• Introduction
• ‘Moore than Moore’ vs. ‘More Moore / Beyond’
• Conventional MOS trench capacitors for decoupling
– ONO / (poly)-Si stacks
• NXP Roadmap for 3D System-in-Package (SiP)
– From MOS to MIM capacitors from ~25 to 400 nF/mm2
• ALD of multiple high-k MIM (TiN / Al2O3 / TiN)
• Growth and processing
• Structural and electrical characterization
• Concluding remarks
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
3
Miniaturization by Moore…. over 40 years ago (1965)
Number of components per chip
10
10
10
10
10
10
5
4
3
2
1
0
1960
1965
1970
1975
4
http://www.intel.com/technology/mooreslaw/index.htm
PowerSoC08,
Sept. 22-24, 2008, Cork, Ireland
Miniaturization and diversification….
Two ways to build device-based systems …
baseline
CMOS
memory
MPU
RF
HV
sensors
bio,
Power passives actuators fluidics
2000
‘More Moore’
Planar
bulk CMOS
‘More than Moore’
2005
System in Package
Moore’s
Law
Interaction
2010
2015
‘feel, smell, touch, hear, see’
System on Chip
Data processing:
‘compute and store’
FinFET
2020
‘Senses’
‘Brains’
0 1
Beyond Moore: nanowires,
spintronics, molec. electr.
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
5
Miniaturization plus
diversification
Miniaturization
and
diversification….
baseline
CMOS memory
RF
HV
sensors
bio,
Power passives actuators fluidics
2000
100 mm
1000
2005
500
250
2010
300 mm
2015
130
150-200 mm
65
32
size
[nm]
2020
Non-CMOS devices, multi-chip (MEMS, Lab-on-Chip, ..) in SiP solutions
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
6
Miniaturization by Moore…... foreseen or not ?
Passive integration
Smart system integration: BAW,
car radar, MEMs oscillators, tuners, ..
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
7
RF passive devices for mobile communications
Switchable MEMS
capacitors and
tunable dielectrics
BAW-filters
Passive integration in SiP
front-end power amplifier
esp. integrated
capacitors
MEMS
oscillators
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
8
NXP: Vias and Integrated Passives (VIP) for SIP
Passive and heterogeneous integration charter :
F. Roozeboom et al., Sol. State Technology 51, (May 8, 2008) 38
Digital
Digital CMOS
CMOS
Memory
Memory
PICS3
SiSi/SiGe
/SiGe
MEMS
• System in Package
• High-density capacitors
– MOS and MIM trench cap arrays for
RF-decoupling & filtering
– Ultralow ESR and ESL
– Low temperature drift
– Reduced size
• Trench Li-ion batteries
– JDA with Philips for autonomous
networks
– Materials for active and barrier layers
• High-value inductors
– Fine (and tapered) vias for heat
spreading, DC grounding, RF signal and
interposing / re-routing
– Laminate and Si-based
– Double-sided wafer processing and diestacking
– Wafer Level Package
– Chip-scale
P. Notten, F. Roozeboom, R. Niessen, L. Baggetto,
Adv. Mater. 19, 4564–4567 (2007) ;
More in: Adv. Funct. Mat. 18, 1057–1066 (2008)
– for DC-DC conversion in SIP
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
9
Capacitance increasing from ~1 (planar) to 400 nF/mm2 (trench)
C = ε0 εr A / d
C = ε0 εr A / d
C = ε0 εr A / d
~ 3.5 µ
m
~ 1 µm
d - thinner dielectrics
(breakdown limited)
A - Porous Si ~ 25-30 x
- HSG: Hemispherical Si Grain ~ 2 x
- MIMIM.... ~ 2 - 3
~ 30 µm
εr - medium-k dielectrics : ~ 1.5 - 15 x
Al2O3 , HfO2, Ta2O5, La
(Ba-)Sr-Ti-O
2O3- ZrO
2, nanolaminates,
PowerSoC08,
Sept. 22-24,
2008, Cork, Ireland
10
Outline
• Introduction
• ‘Moore than Moore’ vs. ‘More Moore / Beyond’
• Conventional MOS trench capacitors for decoupling
– ONO / (poly)-Si stacks
• NXP Roadmap for 3D System-in-Package (SiP)
– From MOS to MIM capacitors from ~25 to 400 nF/mm2
• ALD of multiple high-k MIM (TiN / Al2O3 / TiN)
• Growth and processing
• Structural and electrical characterization
• Concluding remarks
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
11
Trench capacitors: use of 3rd dimension
C = ε0 εr A / d
~ 25-30x surface with trenches in Si
~ 3.5 µ
m
~ 1 µm
20 - 30 µm
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
12
Capacitor manufacturing
RIE Etching of trenches in Si substrate:
Plasma etching with SF6 /O2 and C4F8 (‘Bosch’ process)
up to ~ 30 µm depth
Etching of trenches in Si substrate
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
13
RIE etching (‘Bosch process’)
~ 30 µm deep
~ 1.5 µm dia.
~ 3.5 µm pitch
~ 1 µm /min
~ 1 µm /min
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
14
Capacitor manufacturing
Local P-doping of high-ohmic substrate
remaining substrate high-ohmic for further PASSITM integration
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
15
Capacitor manufacturing
5 nm
20 nm
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
5 nm
16
Capacitor manufacturing
~0.7 µm
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
17
Capacitor manufacturing
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
18
Capacitor manufacturing
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
19
Capacitor manufacturing
~1 to 2 µm
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
20
Capacitor manufacturing
capacitance tuned
by area
flip-chip
mountable
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
21
Al 0.7 µm poly Si
30 nm Si
ONO
Uniform step coverage
over entire pore depth
Sept.
22-24,
Ireland
ALDPowerSoC08,
2008, June 29
– July
2, 2008,
2008,Cork,
Bruges,
Belgium
22
Capacitor performance (wafer level) MOS
Capacitance (nF)
103
102
~35 µm dry-etched pores
30 nF/mm2
and Ebd=10 MV/cm
10
1
planar
1 nF/mm2
10-1
10-2
10-2
10
10-1
1
Top electrode surface (mm2)
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
102
23
Capacitor performance (wafer level) MOS
density:
breakdown:
leakage:
tan δ (1kHz)
≥ 30 nF/mm2
30 V/30 nm ►10 MV/cm
< 1 nA/mm2 @ 22 V
< 5·10-3
and for 15 nm nitride @ 8 V 90 nF/mm2
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
24
Dielectric breakdown and accelerated lifetime
testing at 100 oC (wafer level)
8 mm² die size
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
25
Intrinsic operating voltage of 10 V (wafer level)
10 years
0.1 % cumulative failure, intrinsic
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
26
RF decoupling (die level) MOS
0
C
L
R
Transmission S21 (dB)
-5
-10
2.2 nF
MOS
Discrete 2.2 nF
-15
-20
-25
-30
-35
-40
-45
-50
1.0E+06
1.0E+07
1.0E+08
1.0E+09
1.0E+10
f (Hz)
50 Ω transmission line
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
27
RF decoupling (die level) MOS
0
-5
Transmission S21 (dB)
C
L
R
-10
2.2 nF
MOS
Discrete 2.2 nF
-15
-20
-25
-30
-35
-40
-45
LCR modeling:
MOS
Discrete
L(nH)
0.038
0.5
R(Ω)
0.145
0.4
-50
1.0E+06
1.0E+07
1.0E+08
1.0E+09
1.0E+10
f (Hz)
Superior, low-loss RF decoupling !!
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
28
Devices in RF Modules and System-in-Package
3 µm Al
1 µm Al
Resistor
50 Ω/sq
Planar capacitor
1.5 nF / mm²
Multi-turn
Inductor
Bumping
Pad
Oxide
Metal 2
Oxide
High-ohmic substrate
1 kΩ.cm
Metal 1
CO
Poly
PICS capacitor
ONO
~25 nF / mm²
1
HL
High/Low
Ohmic
8 masks ►
2
PI
PICS
4
3
CO
PS
Poly Contact
Silicon Opening
Doping
5
M1
Metal 1
6
CO2
Contact
Opening
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
7
8
M2
UB
Metal 2 Under
Bump
29
Si-based SiP assembly technology
Flip-Chip in plastic package
Good RF interconnect to lead frame
Active die attached to die pad : low thermal resistance
Small height package : 0.8 mm
Nearly chip-size package : substrate size + 0.5 mm
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
30
RF System-in-Package Modules commercialized by NXP
1G SiP Bluetooth ‘plug and play’ radio module:
active RF chip integrated on passive die
flip
flip
Passive ‘PICS’ die
transceiver
RF active die
150 µm thick
Decoupling
capacitors
die
passive die
300 µm thick
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
lead frame
31
PICS: Passive Integration Connective Substrate
PICS1: sold in > 300 M SiP devices with
high-density capacitors (25 nF/mm²)
PICS
PA
TRX
power
amplifier
transceiver
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
32
NXP’s Roadmap and PICS Process Capabilities
• PICS1: mass volume manufacturing
– High value decoupling capacitors:
•
•
•
•
25 nF/mm²
Vbd = 32 V
Low ESR = 40 mΩ
Ultra low ESL < 40 pH
• PICS2: qualified in 2007
– High value capacitors:
• 80 nF/mm²
• Vbd = 15.5 V
• ESL=50 pH typical
– ►Thinner ON (16 nm)
– Accurate fine value capacitors for
RF filtering and decoupling
• 80 pF/mm², 100 V max
• ESR = 10 mΩ
– Inductors
• Up to 50 nH with Q=30
– Resistors
• Up to 100 kΩ
• Matching accuracy < 2%
– Interconnect
32 µm high pillars
• 2 metal layers with fine pitch
routing (5 µm)
See also NXP’s paper 6.3 (H.J Bergveld• PICS3: 250 nF/mm² demonstrated
– ►More layers, deeper pores
et al.), on Sept. 25 on inductive downconversion using « PICS2C » technology• PICS4: 400 nF/mm² demonstrated
(with 8 um Cu
– ►ALD layer stacks
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
33
Outline
• Introduction
• ‘Moore than Moore’ vs. ‘More Moore / Beyond’
• Conventional MOS trench capacitors for decoupling
– ONO / (poly)-Si stacks
• NXP Roadmap for 3D System-in-Package (SiP)
– From MOS to MIM capacitors from ~25 to 400 nF/mm2
• ALD of multiple high-k MIM (TiN / Al2O3 / TiN)
• Growth and processing
• Structural and electrical characterization
• Concluding remarks
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
34
Stepping up from 25 to 400 nF/mm2
C = ε0 εr A / d
C = ε0 εr A / d
C = ε0 εr A / d
~ 3.5 µ
m
~ 1 µm
d - thinner dielectrics
(breakdown limited)
A - Porous Si ~ 25 - 30 x
- HSG: Hemispherical Si Grain ~ 2 x
- MIMIM.... ~ 2 - 3
~ 30 µm
εr - medium-k dielectrics : ~ 1.5 - 4 x
Al2O3 , HfO2, Ta2O5, La
(Ba-)Sr-Ti-O.....
2O3- ZrO
2, nanolaminates,
PowerSoC08,
Sept. 22-24,
2008, Cork, Ireland
35
HSG: Hemispherical Silicon Grain
• increased surface area 1.5-2.4 x
• grain size 20 - 100 nm
• used in DRAM technology
(STM, Infineon, …)
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
36
Thermal ALD of multiple MIM in high aspect ratio pores
• Al2O3 at 380 °C using TMA and O3
- cycle time: 3.5 s
• TiN at 400 °C using TiCl4 and NH3
- cycle
time: 1.8 s
• Part of wafers post-dep annealed after each Al2O3 layer:
5 mins at 400 °C in O3 to reduce defects (O-vacancies, etc.)
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
37
(Thermal) ALD of Al2O3 from Al(CH3)3 and H2O
animation on:
http://www.cambridgenanotech.com/animation/
- sequential pulsing of precursors
- self-limiting (ligand exchange)
PowerSoC08,
Sept. 22-24, 2008,
Cork, Ireland
- purge/ vacuum between
all pulses
- step
conformal
38
Stepping up from 25 to > 400 nF/mm2 (world record):
Excellent step coverage in
High Angle Annular Dark Field ►
(30 µm)
IEEE EDL 29, 740-742, July
2008 Sept.
and22-24,
Solid
State
Technology 37 May 2008
PowerSoC08,
2008,
Cork, Ireland
39
High resolution TEM
TiN-3
Al2O3
• sharp interfaces after O3 annealing
• reproducible layer thicknesses
TiN #2
Al2O3
TiN #1
SiO2
5 nm
SiPowerSoC08, Sept. 22-24, 2008, Cork, Ireland
40
Electrical connection on capacitor
Pore Ø: 1.5 um
Pore depth: 30
um
Substrate: n++
TiN etch (dry):
Cl-ChemistryTiN #3
(STS Cluster tool)
TiN #2 Al2O3 etch (wet):
H3PO4 + CrO3+ H2O,
T=95oC
TiN #1
100u
m
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
TiN electrode #3
Al2O3 dielectric #3
TiN electrode #2
Al2O3 dielectric #2
TiN electrode #1
SiO2 dielectric #1
Subst. electrode
41
Bond pads on triple MIM capacitor
Pore Ø: 1.5 um
Pore depth: 30
um
Substrate: n++
TiN #3
SiO2 etch (wet):
BOE (7:1)
Al etch (wet):
TiN #2
PES -etch,
T=30oC
Subst.
TiN #1
100u
m
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
Metal bond
pads(Al)
Oxide
TiN electrode #3
Oxide
Al2O3 dielectric #3
TiN electrode #2
Al2O3 dielectric #2
TiN electrode #1
SiO2 dielectric #1
Subst. electrode
42
Improved leakage for 400 nF/mm2 capacitors after O3 anneal
0.1
Planar: annealed
Trench: annealed
Planar: as deposited
Trench: as deposited
1E-3
Current (A)
1E-5
1E-7
1E-9
1E-11
1 nA/mm2
1E-13
1E-15
-8
-6
-4
-2
0
2
4
6
8
Voltage (V)
2008, Cork,July
Ireland2008
IEEEPowerSoC08,
EDL 29,Sept.
pp.22-24,
740-742,
43
Improved leakage and breakdown for capacitors after O3 anneal
Weibull plots indicating reproducible leakage current and breakdown
(35 samples averaged) :
2
2
Trench: annealed
1
Planar: annealed
0
Planar: annealed
0
ln(-ln(1-F))
ln(-ln(1-F))
Trench: annealed
1
-1
-2
-3
-1
-2
-3
-4
-4
-5
0.01
-5
0.1
1
10
100
0
5
ILeak [nA]
2008, Cork,July
Ireland2008
IEEEPowerSoC08,
EDL 29,Sept.
pp.22-24,
740-742,
10
15
VBD [V]
44
What to expect with future ‘high-k’ ?
E
bd
≅
20
k
k
PowerSoC08,
Sept.
22-24, 2008, Packaging
Cork, Ireland 25 (3) 454 (2002)
P. Jain et al, IEEE
Trans.
Advanced
45
ALD of La2O3-ZrO2: potential for 1-2 µF/mm2 !
La:Zr
1:0
12:1
4:1
1:1
1:4
E
bd
≅
20
k
1:9
Tetragonal ZrO
0:12
nanocrystals: k~32
10 nm
k
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
46
Integrated 3D capacitors in Si
● NXP/Philips
□ Others
World record
8 IEEE*
5x PICS2
density
PICS2 :
Transferred to production
PICS1: In production at NXP
Overview of published capacitance densities
22-24,
2008, Cork, July
Ireland 2008
* IEEEPowerSoC08,
EDL 29,Sept.
pp.
740-742,
47
Outline
• Introduction
• ‘Moore than Moore’ vs. ‘More Moore / Beyond’
• Conventional MOS trench capacitors for decoupling
– ONO / (poly)-Si stacks
• NXP Roadmap for 3D System-in-Package (SiP)
– From MOS to MIM capacitors from ~25 to 400 nF/mm2
• ALD of multiple high-k MIM (TiN / Al2O3 / TiN)
• Growth and processing
• Structural and electrical characterization
• Concluding remarks
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
48
Concluding remarks
• Passive integration (3D caps and other passives):
- Ongoing, for new and future functionalities:
decoupling, filtering, DC-DC conversion in System-in-Package
- Back-end temperature processing, compatible with CMOS, MEMS, etc.
• Capacitance density > 400 nF/mm2 demonstrated with ALD
for TiN / Al2O3 multiple MIM stack
• Outlook: > 1-4 µF/mm2 foreseen
- La-Zr-oxide: k~32
- BaSrTiOx:
k~80
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
49
Recommended literature
F.Roozeboom, R.Elfrink, J.Verhoeven, J. van den Meerakker and F.Holthuysen, Microelectr. Eng. 53 (2000) 581
F. Roozeboom, R. Elfrink, T.G.S.M. Rijks, J. Verhoeven, A. Kemmeren and J. van den Meerakker,
nt. J. Microcircuits and Electronic Packaging, 24 (3) (2001) pp. 182-196
F.Roozeboom, A.Kemmeren, J.Verhoeven, F.van den Heuvel, H.Kretschman and T.Frič, ‘High-Density, Low-loss MOS
Decoupling Capacitors integrated in a GSM Power Amplifier’, Mat. Res. Soc. Symp. Proc. 783, 157-162 (2003)
F. Roozeboom, A.L.A.M. Kemmeren, J.F.C. Verhoeven, F.C. van den Heuvel, J. Klootwijk, H. Kretschman, T. Frič,
E.C.E. van Grunsven, S. Bardy, C. Bunel, D. Chevrie, F. LeCornec, S. Ledain, F. Murray and P. Philippe, ‘Passive and
heterogeneous integration towards a silicon-based System-in-Package concept’, Thin Solid Films 504 (2006) 391-396
F. Roozeboom, A.L.A.M. Kemmeren, J.F.C. Verhoeven, F.C. van den Heuvel, J. Klootwijk, H. Kretschman, T. Frič,
E.C.E. van Grunsven, S. Bardy, C. Bunel, D. Chevrie, F. LeCornec, S. Ledain, F. Murray and P. Philippe, ‘More than
'Moore': towards Passive and System-in-Package integration’, in C. Claeys, J. W. Swart, N. I. Morimoto and P. Verdonck,
eds., ‘Microelectronics Technology and Devices- SBMicro 2005’, The Electrochemical Society, Pennington (NJ), USA ;
Electrochem. Soc. Symp. Proc. 2005-8 (2005) 16-31
J. Klootwijk, A. Kemmeren, R. Wolters, F. Roozeboom, J. Verhoeven and E. van den Heuvel, ‘Extremely High-Density
Capacitors with ALD High-k Dielectric Layers ; ALD Dielectric layers in High Aspect Ratio Macropore Arrays’ in
‘Defects in Advanced High-κ Dielectric Nano-Electronic Semiconductor Devices’, (E. Gusev, ed.), Springer, Dordrecht,
2006, pp. 17-28
F. Roozeboom, J.H. Klootwijk, J.F.C. Verhoeven, F.C. van den Heuvel, W. Dekkers, S.B.S. Heil, J.L. van Hemmen,
M.C.M. van de Sanden, W.M.M. Kessels, F. Le Cornec, L. Guiraud, D. Chevrie, C. Bunel, F. Murray, H.-D. Kim and D.
Blin, ‘ALD options for Si-integrated ultrahigh-density decoupling capacitors in pore and trench designs ', 210th
Electrochemical Society Meeting, Cancun, Oct. 29-Nov. 3, 2006 ; abstract PR-MS 26.699, 16 May 2006, manuscript PRMS 27.595, Jan. 3, 2007; Electrochem. Soc. Trans. 3 (15), 173-181 (2007)
J.H. Klootwijk, K.B. Jinesh, W. Dekkers, J.F. Verhoeven, F.C. van den Heuvel, H.-D. Kim, D. Blin, M.A. Verheijen, R.
Weemaes, M. Kaiser, J.J.M. Ruigrok and F. Roozeboom, ‘Ultra-high capacitance density for multiple ALD-grown MIM
capacitor stacks in 3D silicon’, IEEE Electron Device Letters 29 (7) 740-742, (2008)
F. Roozeboom, J.H. Klootwijk, W. Dekkers, Y. Lamy, E. van Grunsven and H.-D. Kim, ‘3D Passive and Heterogeneous
Integration Technology Options for System-in-Package’, Solid State Technol., 51 (5), 38-47 May 8, 2008
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
50
Acknowledgments
• Senter-Novem Project ‘INNOVia’, (2005-2008)
INNOVia
• European FP6-programs ‘REALISE’ and ‘e-CUBES’ (2006-09)
• MEDEA+ ‘MAXCAPS’ (2008-11)
MaxCaps
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
51
Thank you:
Tyndall and you
PowerSoC08, Sept. 22-24, 2008, Cork, Ireland
52