Characterization of Graphene Field-Effect Transistors for
High Performance Electronics
Inanc Meric
Submitted in partial fulfillment of the
requirements for the degree
of Doctor of Philosophy
in the Graduate School of Arts and Sciences
COLUMBIA UNIVERSITY
2011
c
2011
Inanc Meric
All Rights Reserved
Abstract
Characterization of Graphene Field-Effect Transistors for
High Performance Electronics
Inanc Meric
It is an ongoing effort to improve field-effect transistor (FET) performance. With silicon
transistors approaching their physical limitations, alternative materials that can outperform
silicon are required. Graphene, has been suggested as such an alternative mainly due to
its two-dimensional (2D) structure and high carrier velocities. The band structure limits
achievable bandgaps, preventing digital electronic applications. This, however, does not rule
out analog electronic applications at high frequencies, where the full potential of improved
carrier speeds in graphene can be exploited.
In this thesis, the high-bias characteristics of graphene FETs are investigated. Current saturation as well as the effect of ambipolar conduction on the current-voltage characteristics are studied. A field-effect model is developed that can capture the effects of
the unique band structure, such as a density-dependent saturation velocity. The effect of
channel length scaling in these devices is studied down to 100-nm channel length with the
aid of pulsed-measurement techniques. Transistors RF performance and bias dependence
of high frequency behavior is explored.
Novel fabrications methods are developed to improve FET performance. A technique
is developed to grow metal-oxides on graphene surface for efficient gate coupling. An alternative approach to making high quality devices is realized by incorporating hexagonal-boron
nitride as a gate dielectric. These transistors exhibit the potential of graphene electronics
for high-performance analog electronic applications.
Contents
List of Figures
iv
Acknowledgments
vi
Chapter 1 Introduction
1
1.1
An overview of graphene research . . . . . . . . . . . . . . . . . . . . . . . .
2
1.2
Graphene properties significant for FET applications . . . . . . . . . . . . .
4
1.2.1
Crystal structure
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
1.2.2
Band structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
1.2.3
Zero-bandgap in graphene . . . . . . . . . . . . . . . . . . . . . . . .
9
1.2.4
Electrical transport
. . . . . . . . . . . . . . . . . . . . . . . . . . .
10
1.2.5
Other properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
Thesis outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
1.3
Chapter 2 Current saturation in zero-bandgap, top-gated graphene fieldeffect transistors
13
2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
2.2
Device fabrication and experimental methods . . . . . . . . . . . . . . . . .
14
2.2.1
Transistor fabrication . . . . . . . . . . . . . . . . . . . . . . . . . .
14
2.2.2
Device measurement . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
2.3
Small-signal characterization . . . . . . . . . . . . . . . . . . . . . . . . . .
17
2.4
High-bias characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
i
2.5
Field-effect modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
2.6
Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
Chapter 3 Channel length scaling in GFETs studied with pulsed currentvoltage measurements
29
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
3.2
Device structure and fabrication . . . . . . . . . . . . . . . . . . . . . . . .
30
3.3
Measurement and results . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
3.4
Modeling and discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
3.5
Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
Chapter 4 Graphene field-effect transistors based on boron nitride gate
dielectrics
39
4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
4.2
Basic device structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
4.3
Low-field transport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
4.4
I-V characteristics on h-BN supported devices . . . . . . . . . . . . . . . . .
45
4.5
Device modeling and saturation velocity . . . . . . . . . . . . . . . . . . . .
46
4.6
Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
Chapter 5 High-frequency characterization of GFETs
48
5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
5.2
RF performance of top-gated GFETs . . . . . . . . . . . . . . . . . . . . . .
49
5.2.1
Device structure and fabrication . . . . . . . . . . . . . . . . . . . .
49
5.2.2
DC characterization . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
5.2.3
Device frequency response . . . . . . . . . . . . . . . . . . . . . . . .
51
RF performance h-BN supported GFETs . . . . . . . . . . . . . . . . . . .
52
5.3.1
Device structure and fabrication . . . . . . . . . . . . . . . . . . . .
53
5.3.2
DC characterization . . . . . . . . . . . . . . . . . . . . . . . . . . .
54
5.3.3
Device frequency response . . . . . . . . . . . . . . . . . . . . . . . .
56
5.3
ii
5.4
Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 6 Conclusion
57
59
6.1
Summary of contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59
6.2
Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
iii
List of Figures
1.1
The atomic structure of graphene. . . . . . . . . . . . . . . . . . . . . . . .
3
1.2
Band structure of graphene. . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
1.3
Density-of-states in 2D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
1.4
Conceptual current-voltage characteristics of a FET. . . . . . . . . . . . . .
10
2.1
Characterization of mechanically exfoliated graphene sheets. . . . . . . . . .
15
2.2
Atomic-force microscopy (AFM) image of graphene covered with HfO2 . . .
16
2.3
Basic top-gated graphene FET design. . . . . . . . . . . . . . . . . . . . . .
17
2.4
The effect of HfO2 on conductance. . . . . . . . . . . . . . . . . . . . . . . .
18
2.5
Room temperature low-field transport in top-gated GFET. . . . . . . . . .
19
2.6
Low-field transport in top-gated GFET at 1.7K. . . . . . . . . . . . . . . .
20
2.7
Current-voltage characteristics of GFET device. . . . . . . . . . . . . . . . .
21
2.8
Current-voltage characteristics in contour plot. . . . . . . . . . . . . . . . .
22
2.9
Kink effect in GFET devices. . . . . . . . . . . . . . . . . . . . . . . . . . .
23
2.10 I-V characteristics of back gated GFETs. . . . . . . . . . . . . . . . . . . .
24
2.11 Field-effect modeling of GFET device. . . . . . . . . . . . . . . . . . . . . .
26
2.12 Density dependence of vsat . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
3.1
Top-gated GFET device structure with PVA. . . . . . . . . . . . . . . . . .
31
3.2
Effect of PVA growth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
3.3
DC current-voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . .
33
3.4
Pulsed measurement technique. . . . . . . . . . . . . . . . . . . . . . . . . .
34
iv
3.5
Pulsed I-V measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
3.6
Small-signal parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
3.7
Channel-length scaling.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
4.1
h-BN structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
4.2
Mechanical transfer process. . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
4.3
Back-gated GFET with h-BN gate dielectric. . . . . . . . . . . . . . . . . .
42
4.4
Low-field transport characteristics of GFET device with h-BN. . . . . . . .
43
4.5
Current-voltage characteristics of GFET devices with h-BN. . . . . . . . . .
44
4.6
Intrinsic device IV characteristics. . . . . . . . . . . . . . . . . . . . . . . .
44
4.7
Intrinsic small-signal transconductance. . . . . . . . . . . . . . . . . . . . .
45
4.8
Saturation velocity in GFETs with h-BN dielectric. . . . . . . . . . . . . . .
46
5.1
Graphene FET structure for RF measurements. . . . . . . . . . . . . . . . .
50
5.2
Current-voltage characteristics of top-gated GFET device for RF. . . . . . .
51
5.3
Frequency response of top-gated GFET. . . . . . . . . . . . . . . . . . . . .
52
5.4
GFET device with h-BN for RF. . . . . . . . . . . . . . . . . . . . . . . . .
53
5.5
High-frequency device characteristics. . . . . . . . . . . . . . . . . . . . . .
54
5.6
Bias-dependence of small-signal parameters. . . . . . . . . . . . . . . . . . .
55
5.7
Bias dependence of high-frequency figures-of-merit. . . . . . . . . . . . . . .
55
5.8
Small-signal and RF modeling. . . . . . . . . . . . . . . . . . . . . . . . . .
56
5.9
Improvements possible with device optimization. . . . . . . . . . . . . . . .
57
v
Acknowledgments
First and foremost, I would like to thank my advisor, Kenneth L. Shepard, for all the
extraordinary support over the course of my doctoral studies at Columbia. I’m grateful
to him for the encouragement to join his research group, all the helpful advice, and the
endless work he put into this project together with me. Ken is one of the brightest people
I have ever met, with a vast knowledge in a wide range of topics. It’s truly been a joy and
a privilege to work with him. His teachings were limitless, and I am particularly grateful
to have learned from him an enthusiasm for doing research.
I also would like to thank all my coworkers and group members, past and present,
as without them this work wouldn’t have been possible. To mention a few Simeon Realov,
Matt Johnston, Peter Levine, Omar Ahmad, Mike Lekas, Ryan Field, Jared Roseman, and
Vincent Caruso; these guys helped, cheered, and distracted (when needed) me over the
years.
Special recognition goes of course to Sebastian Sorgenfrei, whose company (of course
in German), both at and outside of work, I very much appreciated. I admire his detailoriented approach, and I’ve learned a lot (etiquette and good manners) from him. I owe a
special thanks to Cory Dean, who has been a close co-worker, an excellent mentor, and a
good friend (eh?!); and Andrea Young, whose passion for physics taught me more than I
ever could have wanted to know about physics.
I would like to extend particular gratitude to my dissertation defense committee
members, Professors Tony Heinz, John Kymissis, James Hone, and Philip Kim. I also
would like to thank them and many of their group members for all the help I got from
vi
throughout the years.
During the course of my studies, I had the pleasure to work with some great people.
I want to thank Sami Rosenblatt, Barbaros Ozyilmaz, Kirill Bolotin, Pablo Jarillo-Herrero,
Kin Fai Mak, and Nick Petrone. I also want to thank all my co-authors, Melinda Han, Lei
Wang, Noah Tremblay, Robert Caldwell, Shu-Jen Han, Keith Jenkins, and Zhang Jia for
all the hard work they put in. In addition, Natalia Baklitskaya deserves a special thanks
for her help with meticulous device fabrication.
Luckily, I had the pleasure of having some great friends outside of work as well. I
deeply appreciate their enthusiasm for keeping me away from work at times. Out of all of
my friends in New York, Tufan has always been a true friend; his humor helped through
every possible situation. And thanks to him, Deniz, and Sebastian; we’ve shared many
memories over endless dinner parties.
And last, but certainly not least, I’d like to thank my family, without whom this all
wouldn’t have been possible. I’m deeply grateful to them for their love and encouragement
throughout my life, and for their support in every possible way. I’m thankful to my mom,
my brother Can, and Cemre for their daily phone calls; they kept me close to home when I
couldn’t be.
vii
To my grandfather.
viii
1
Chapter 1
Introduction
Since the early days of the semiconductor technology, there has been an ongoing quest for
faster, more energy efficient, and cheaper electronics. This enabled a multitude of novel
applications, and possibly, the information era. Driven mainly by the growing electronics
markets and backed by predictions such as the Moore’s Law, silicon semiconductor industry
kept constant performance gains through shrinking the of field-effect transistors (FETs) size
since the early 60s. The inherent physical limitations to smaller silicon transistors however
are rapidly approaching, motivating the need for alternative semiconductor materials.
While silicon technology is focusing on improved three-dimensional devices, high-κ
gate dielectrics, and uniaxial strained silicon channels, alternative semiconducting materials
that could outperform silicon, without the requirement of aggressive size shrinkage have been
suggested. Focus has been on improving transistor speeds by engineering materials with
higher carrier mobilities, increased saturation velocities, and lower effective carrier mass
such as SiGe, and III-Vs such as InP, GaAs, InGaAs. After over 30 years of active research,
these technologies remain complex and therefore costly, preventing a mainstream debut.
Recently, there has been growing interest in carbon electronics. For example the
outstanding properties of carbon nanotubes (CNTs), exhibiting mobility values close to
1, 000 times higher than bulk silicon, suggested the possibility of realizing ballistic FETs
with extremely high unity-current-gain frequencies (fT ), up to the THz range [1]. Yet serious
2
challenges remain unsolved due to the inherent 1D structure of CNTs such as limited control
over chirality and lack of large area samples with dense enough nanotubes.
Graphene has emerged as another promising carbon-based electronic material showing ultrahigh mobility and, therefore, significant promise for high-frequency electronics. The
two-dimensional nature of graphene makes it attractive over nanotubes from an architectural standpoint because it readily admits large area samples that can be patterned using
standard lithography techniques. The ultrathin nature, high mechanical strength, flexibility, high thermal conductivity, optical transparency, and potential low cost, in conjunction
with its high carrier velocities, make graphene a promising semiconductor.
In pursuit of keeping the electronic age booming, the challenge remains to find a
replacement to silicon. Graphene, a novel addition to the semiconductor world, remains
a strong contender in theory. This work aims to investigate the potential of graphene for
electronic applications with an experimental approach.
1.1
An overview of graphene research
The first experimental realization of graphene in 2004 [2] sparked a whole new epoch in the
research community world wide. This was the first experimental demonstration of a freestanding, strictly 2D crystal. Since then, numerous other 2D crystals have ben realized [3],
but none have had the same impact. Neither was this the first example of a two-dimensional
electron gas (2DEG), since this has been widely explored in many semiconducting materials
since the early days of condensed matter research [4]. It was due to the combination of many
unique physical and electrical properties, with the added benefit of a rather straightforward
method for realizing graphene samples.
Graphene, a single layer of carbon atoms arranged in a honeycomb lattice (Figure 1.1), can be viewed as the building block of all other sp2 bonded carbon. Stacked
layers that are weakly bound together form the most common 3D form, graphite; whereas
nanotubes can be envisioned as graphene layers rolled up into a tube with a diameter of
typically less than few nanometers [1] or fullerene when formed into a ball-shape [5].
3
Figure 1.1 The atomic structure of graphene. Carbon atoms are arranged in a 2D
Figure 1.1:lattice
The atomic structure of graphene. Carbon atoms are arranged in a 2D honeyhoneycomb
comb lattice.
The exceptionality of graphene can be attributed to numerous features. In conventional 2DEGs carrier confinement is due to electrostatics. In graphene, the confinement
of electrons (holes) is ensured by the physical 2D structure, enabling an exposed 2DEG
on both sides. Furthermore, graphene is a zero-bandgap semiconductor with linear energy
dispersion around a neutrality point (Dirac point) and symmetric valence and conductance
bands. Undoubtedly, these characteristics backed by the experimental observation of massless Dirac fermions [6, 7] had a major impact on the prospects of graphene research.
The discovery of graphene lead to breakthrough research across several different
disciplines both in sciences and engineering. Condensed matter physics, leading the field
with probably the most significant results such as the observation of room-temperature
quantum Hall effect [8], the first observation of Klein tunneling [9, 10] and, with improved
sample quality over time, the fractional quantum Hall effect [11–13].
While electrical transport led the way at the beginning, other spectroscopy methods
soon caught up. Scanning-tunneling microscope images of graphene made the honeycomb
lattice visible [14–16], and optical spectroscopy studies [17–19] revealed important characteristics such as optical absorption, transparency, and the number of layers and stacking
4
configuration in multi-layer samples. Probably the most common optical tool remains Raman spectroscopy [20, 21], which is used to identify the number of layers and doping in
samples.
Although graphene refers to a single atomic layer thick sheet, it is widely used to
refer to multi-layer stacks (anywhere from 2-5 layers) as these cannot be considered as fully
graphitic carbon. Among them, bilayer graphene [22] has been the most intensely studied,
owing mostly to the unique property that a tunable bandgap that can be induced through
the application of an electric field [23–26].
Some novel applications that benefit from the novel physical structure of graphene
have been impermeable membranes [27, 28] and the oscillating component of electromechanical resonators [29, 30]. The chemical stability and exposed nature of the 2DEG make
excellent gas sensors [31, 32] and liquid pH sensor [33].
Among all the possible graphene applications, field-effect transistors for analog/RF
retain the highest profile area. The first demonstration of a saturating graphene FET
(GFET) was in 2008 [34], quickly followed by high-frequency measurements [35, 36] and
numerous theoretical studies [37–39]. GFET performance continues to improve. Recent
results have demonstrated cut-off frequencies of 100 GHz [40], and even more recently of
300 GHz [41].
Countless other research directions, both exploring the intrinsic properties of graphene
and the application of graphene to novel technologies, can be found in the literature, and
are too numerous and varied to be included here. A broad overview of the current status of
graphene research can be obtained through several comprehensive review articles [42–45].
1.2
1.2.1
Graphene properties significant for FET applications
Crystal structure
The most notable feature of graphene is probably its 2D structure. Compared to its 1D
counterpart, carbon nanotubes, this enables some key advantages for device application.
5
While field-effect transistors based on carbon nanotubes have been the subject of intensive
research for the last decade [46–48], a major limitation remains to be the requirement for
tightly packed arrays of nanotubes to achieve device performance comparable to silicon
FETs [49]. Graphene does not require such an assembly of large parallel arrays and it can
readily be realized on a full wafer scale.
The 2D shape also improves the electrostatics for FET applications. The basic structure of most FETs mimics the standard metal-oxide-semiconductor (MOS) structure, where
an electrostatic field applied through a metal gate is used to modulate the carrier density,
and hence the current in the semiconductor [50]. As this standard principal operation relies on electrostatics between two parallel plates, it is straightforward to conceptualize the
advantage of graphene over nanotubes in terms of electrostatics. Though there have been
carbon nanotube FETs made with all-around gates [51], they remain extremely challenging
to fabricate. The limited control over the chirality and diameter of nanotubes (and the
associated electronic bandgap) remains a major problem as well.
The advantage of 2D over 3D is that there is no body or bulk charge in a purely
2D system. This is mainly advantageous compared to silicon-on-insulator (SOI) or deeply
scaled transistors, where bulk charge can degrade device performance [50]. In silicon-MOS
technology, these adverse effects are addressed by complicated device structures such as
Tri-Gate FETs [52], while graphene inherently circumvents these.
A significant advantage of graphene is the possibility for large area fabrication. For
device research, the most widely used method for realizing graphene in the laboratory setting
remains the exfoliation technique, where single layers of graphene are peeled off of naturally
occurring bulk graphite [2]. However, synthetic growth of large area graphene films has
been first rendered possible through conversion of SiC [53, 54] and more recently through
direct CVD growth on metal films like nickel [55] and copper [56]. The uniformity and
size of the CVD films have improved very quickly [57, 58], a crucial step in commercializing
graphene applications.
6
1.2.2
Band structure
The electrical band structure of graphene is most certainly another very unique characteristic that was discovered long before the first experimental realization [59]. The lattice
structure of graphene is made up of carbon atoms in a hexagonal structure that repeat to
form the honeycomb-patterned sheet. In sp2 carbon the 2pz orbital forms π bonds in plane
within the structure. The basic structure of the unit cell contains two atoms bond together
with a carbon bond with a separation of a ' 1.42Å. The lattice vectors are:
!
!
√
√
3 a
3 a
a1 =
, a2 =
a,
a,
2
2
2
2
(1.1)
and the unit vectors for the reciprocal-lattice are given by:
b1 =
2π 2π
√ ,
3a a
, b2 =
2π 2π
√ ,
3a a
(1.2)
The band structure can be calculated with the above vectors using the tight binding model
considering only the nearest-neighbor interactions [60]. Figure 1.2 depicts the energy dispersion that can be calculated from
E(k) = ±tw(k),
(1.3)
where both the atomic energy of the 2pz orbital and the overlap integral between nearest
two atoms is set to zero, t is the tight binding parameter equal to 3.0 eV, and w(k) is given
by:
√
ky a
ky a
3kx a
1 + 4cos
cos
+ 4cos2
2
2
2
s
w(k) =
(1.4)
At the corners of the Brillouin zone, called the K points (or Dirac points), the valence
and conductions bands touch each other, making graphene a zero-bandgap semiconductor.
At low energies, limited to approximately 0.35 eV mainly due to the lack of dielectrics
with breakdown fields to exceed this, the energy dispersion around the K points can be
approximated by
E ≈ ~vF |k0 |,
(1.5)
giving a linear relation between energy and wavevector (Figure 1.2). Here, vf = 1 × 108
7
!"
#"
%#
!$#
!"#
Figure 1.2 Band structure of graphene. (a) Dispersion relation of graphene
Figure 1.2:
Band structure
of graphene
schematically
schematically
depictedofingraphene.
the k-space.(a)
(b)Dispersion
The linear relation
energy dispersion
around
the
depictedK-point.
in the k-space. (b) The linear energy dispersion around the K-point.
cm/sec is the Fermi velocity at which electrons (holes) move. The linear dispersion, in
contrast to the conventional parabolic dispersion characteristic with effective mass, means
that the carriers move with a velocity that is independent of the energy. Hence, carriers
behave like massless Dirac fermions, making graphene an unparalleled system with carriers
acting like relativistic particles moving at the Fermi velocity.
√
The electronic density n can be related to the momentum k by k = πn, from which
√
we can rewrite the energy relation from Eqn. 1.5 as E = ~vf πn. As a consequence, the
Fermi energy in a graphene FETs can be modulated by applying an external electric field
(usually done with the FET gate) that can continuously change the carrier density from
holes to electrons passing through a minimum, known as the neutrality or Dirac point [6].
Another outcome of the linear dispersion is the unique density-of-states (DOS). One can
easily calculate the DOS in graphene from the dispersion Eqn. 1.5 including the four-fold
degeneracy as
DOS =
2E
~2 vf2 π
(1.6)
whereas the DOS in parabolic systems can be calculated as:
DOS =
m∗
~2 π
(1.7)
8
!"
#$%&'()"*+"&(,($&"
#"
#$%&'()"*+"&(,($&"
!"
!"
Figure 1.3 Density-of-states in 2D. (a) A cartoon of the DOS in graphene with
Figure 1.3:
Density-of-states
in 2D.
A the
cartoon
DOS in graphene
energy
linear
energy dependence
and(a)(b)
DOSof
inthe
a conventional
2DEGwith
withlinear
parabolic
dependence
and
(b)
the
DOS
in
a
conventional
2DEG
with
parabolic
bands.
bands.
Figure 1.3 shows the DOS for the two cases given above. The striking difference is that the
DOS in conventional 2DEGs is constant over energy, whereas in graphene, there is a linear
dependence that goes all the way to zero. This fact has two major implications on FET
operation. First, a small DOS means that changing the electronic density requires a larger
change of the Fermi energy. This is usually modeled by a quantum capacitance in series
with the electrostatic one [61]. The quantum capacitance in graphene can be calculated
as [62]:
Cq = e2 DOS =
e2 2E
~2 vf2 π
(1.8)
In the density range of 1012 to 1013 cm−2 , where most graphene FETs operate, the quantum
capacitance can be calculated to average 2 µF/cm2 . As a comparison, the electrostatic
capacitance in state-of-the-art MOS transistors with an effective oxide thickness (EOT) of
2 nm can be as high as 1.6 µF/cm2 . This poses a significant limitation to the achievable
gate efficiency in graphene; a major drawback for deeply scaled transistor applications.
Second, the linear DOS means that the carrier velocity at high lateral electric fields becomes
carrier density dependent [34, 38], as described in Chapter 2. This density dependence
makes biasing of the FETs to attain maximum possible performance more complicated and
together with the quantum capacitance, adds additional nonlinearity to these devices.
9
1.2.3
Zero-bandgap in graphene
A major implication of the band structure for FET applications is the zero-bandgap.
Broadly speaking, transistors are used in two separate circuit applications; digital and
analog. In digital electronics, transistor are used as switches to create the 0 and 1 states
required for Boolean logic. Ideally, the transistor should turned fully off, meaning no current should flow through the device in the 0 state. Typically in a semiconducting device
this off current (Iof f ) is limited by thermionic emission over the source−drain barrier modulated by the gate bias as determined by a subthreshold slope of 60 mV/decade at room
temperature. For a narrow bandgap (< 200 meV), direct source-drain tunneling currents
can become significant at short channel lengths limiting Iof f . Although, it is possible to
open a bandgap in graphene electrostatically in bilayers as described before, these methods
are limited in the achievable gap sizes.
An alternative approach to open up a bandgap in graphene involves patterning single
layer graphene into nano-ribbons [63–66]. This physical constriction in the range of tens
of nanometers, however, severely limits carrier mobility due to disorder introduced at the
edges. Recent reports achieved higher mobility numbers close to 20, 000 cm2 /V sec [67]
and room temp ION /IOF F ratio as high as 106 for 10-nm wide ribbons [68, 69]. Nevertheless, inducing sufficiently large bandgaps reliably for electronic applications remains a
daunting task even with state-of-the-art fabrications techniques and, thus, prevents digital
applications in near future.
Analog circuits on the other hand are typically biased “ON” and the ION /IOF F ratio
is a less important metric. As shown in Figure 1.4, the device transconductance (∂Id /∂Vgs ),
which ultimately determines the intrinsic device gain, at a given drain-to-source voltage
(Vds ) is more important. Here, Vgs is the gate-to-source voltage and Id is the drain current.
10
!"
#"
%&$$
%&$$
!"#$$
!"#$$
Figure 1.4 Conceptual current-voltage characteristics of a FET. (a) A small-signal
Figuregate
1.4:voltage
Conceptual
current-voltage
of a FET.
(a) A small-signal
gate
is applied
to a transistor characteristics
with a bandgap causing
a modulation
in the
current.to(b)
The same conditions
are applied
to aazero-gap
transistor
showing
voltagedrain
is applied
a transistor
with a bandgap
causing
modulation
in the
drain current.
that
a higher
current are
gainapplied
is possible.
(b) The
same
conditions
to a zero-gap transistor showing that a higher current
gain is possible.
1.2.4
Electrical transport
Certainly, the one feature that has created the highest excitement in graphene electronics
is the high carrier velocity. Low-field carrier mobilities in graphene are limited to 20, 000
cm2 /V sec in silicon−dioxide−supported devices [70,71]. Sample mobility, doping, and minimum conductivity have been studied thoroughly [72–75]. Charged impurities surrounding
the 2DEG are seen as the main source of mobility degradation. In an attempt to reduce
such external dopants, suspended graphene samples have been measured [76–78] that successfully improve sample characteristics with carrier mobility in excess of 200, 000 cm2 / V
sec at cryogenic temperatures.
At room temperature, suspended samples have mobility values that can exceed
100, 000 cm2 /V sec [76], making graphene the fastest semiconductor at room temperature.
Although high mobility is a desirable feature, in short channel FETs the carrier speeds are
mainly dictated by the saturation velocity or source injection velocity [79, 80]. Here, the
advantage of graphene over traditional semiconductors is less obvious and requires further
investigation [34].
Another advantage of graphene is the Ohmic contact resistance with metals [81].
11
In carbon nanotubes, contact resistance is quantized and limited by the number of modes
available within the Fermi energy and generally limited to ∼ 6 kΩ. The continuous band
structure in graphene does not pose such restrictions and contact resistance can be as small
as 50 Ωµm [81]. Maximum attainable current densities are also remarkable, higher than 1
mA/µm, almost six orders of magnitude higher than copper [43].
1.2.5
Other properties
Several additional properties such as large mechanical strength, flexibility, optical transparency, and thermal conductivity can make graphene ideal for novel FET applications.
Graphene is shown to be the strongest material ever measured [82]. Graphene’s pliability
can be used in flexible electronic applications, whereas the 98% transparency is ideal for
transparent electronics. The thermal conductivity is even higher than graphite [83] and can
be in the range of 3, 000 to 5, 000 W/mK, making graphene FETs promising for high-power
circuit applications.
Graphene is chemically stable even in oxygen environment up to few hundred degrees
Celsius [84]. This is mainly due to the strong sp2 carbon lattice that lacks dangling bonds
on the surface of the crystal. While this is an advantage in terms of chemical stability, it can
turn into a disadvantage in situations that require joining graphene with other materials.
For example, combining graphene with oxides in MOS structures is an inherent challenge.
In conclusion, there are many properties of graphene that could make it an ideal
FET channel material. Conversely, there are still many unique qualities of graphene that
have an undetermined effect on its potential for use, and require further study.
1.3
Thesis outline
This dissertation investigates the application of graphene field-effect transistors for analog
electronics with an experimental approach involving different fabrication and measurement
techniques.
Chapter 2 describes the fabrication of top-gated GFETs and characterizes the low-
12
and high-bias transport characteristics. High-bias measurements show current saturation
in these devices that is influenced both by the ambipolar nature of the material and the
density−dependent saturation velocity. The results are modeled with a standard FET
model modified to take into account the unique properties of graphene.
Chapter 3 investigates channel length scaling in GFETs. Devices are fabricated with
a more reliable gate oxide but the trapped charge effects remain, limiting short channel
performance. A pulsed measurement technique is employed to probe the intrinsic graphene
FET properties at high-bias.
Chapter 4 examines an improved GFET structure where hexagonal-boron nitride is
used as the dielectric material. Devices fabricated in this manner have improved transport
characteristics and do not suffer from the trapped-charge-related performance degradation
apparent in SiO2 -supported devices.
Chapter 5 investigates the high-frequency characteristics of GFETs. Both types
of device structures, from Chapter 2 and 4 are analyzed at RF frequencies. The bias
dependence of high frequency performance as well as a simple high-frequency model is
presented.
Chapter 6 summarizes the work and comments on future graphene research and the
prospects for graphene FETs.
13
Chapter 2
Current saturation in
zero-bandgap, top-gated graphene
field-effect transistors
In this Chapter, we report the observation of saturating transistor characteristics in a
graphene field-effect transistor first published in Ref. [34]. Unusual features in the currentvoltage characteristic are explained by a field-effect model with diffusive carrier transport
in the presence of a singular point in the density-of-states. These results demonstrate
the feasibility of two-dimensional graphene devices for analog and radio-frequency circuit
applications without the need for bandgap engineering.
2.1
Introduction
In graphene, the charge carriers in the two-dimensional channel can change from electrons
to holes with the application of an electrostatic gate, with a minimum density (or Dirac)
point characterizing the transition. The zero-bandgap of graphene limits achievable on-off
current ratios (Ion /Iof f ). Bandgaps can be achieved through various methods in single- and
bilayer-graphene, but these either result in significant mobility degradation and fabrication
14
challenges or are far less than 200 meV and would lead to significant band-to-band tunneling.
Here, we describe the design of a top-gated GFET based on a high-κ gate dielectric without
bandgap engineering. Despite Ion /Iof f ∼ 7, high transconductances and current saturation
are achieved, making this device well-suited for analog applications.
2.2
2.2.1
Device fabrication and experimental methods
Transistor fabrication
The fabrication of the GFETs starts with mechanically-exfoliated graphene from Kish
graphite (as in Ref. [2]) on a degenerately-doped Si substrate (ρ = 0.01Ω-cm) with a
285-nm thermally grown SiO2 layer (SiTech). The Si wafer is diced into 1 cm × 1 cm
pieces and treated with standard piranha cleaning prior to the mechanical exfoliation step.
Single-layer graphene pieces are then identified optically. The optical visibility of graphene
samples are higher in reflection compared to transmission if the substrate is tuned to the
optimum resonance condition [85]. The choice of the SiO2 layer thickness is therefore to
ease visual identification. Fig. 2.1(a) shows the optical image of single-layer graphene with
100× magnification. Raman spectroscopy can be used to verify that these are single-layer
graphene sheets. Fig. 2.1(b) shows the Raman spectroscopy results, where a weak D band
peak at 1340 cm−1 , a G band peak at 1583 cm−1 , and a sharp 2D band peak at 2682 cm−1
with a FWHM of 26 cm−1 indicates that the sample is single layer with few defects.
Strips of graphene with widths between 1-5 µm are selected for the device fabrication. Cr/Au (5nm/90nm) electrodes are patterned 3 µm apart by standard electron beam
lithography with a single layer of PMMA 950K A6 e-beam resist (MicroChem), followed by
metal deposition and lift-off processes in acetone to define the source and drain contacts.
A low-temperature atomic-layer-deposition(ALD) process is used the directly grow 15-nm
HfO2 onto the graphene sheet as a high-κ gate dielectric for the local top gate and the
fabrication is finished with top gate electrodes using the same process above.
The HfO2 gate dielectrics are deposited with (ALD) in a Cambridge Nanotech ALD
15
!"
#"
Figure
Characterizationofofmechanically
mechanicallyexfoliated
exfoliatedgraphene
graphene sheets.
sheets. (a)
Figure
2.1:2.1Characterization
(a) Graphene
Graphene
sheets
can
be
optically
discriminated
on
300
nm
SiO
oxides
on Si
sheets can be optically discriminated on 300 nm SiO2 oxides on2Si wafers.
(b)wafers.
Raman spec(b) Raman
spectroscopy
is single-layer
used to verifycharacteristics
the single-layerofcharacteristics
the graphene
troscopy
is used
to verify the
the graphene of
sheets
after device
-1 shows clearly the single
−1
sheets
after
device
fabrication.
The
sharp
2D
peak
at
2682
cm
fabrication. The sharp 2D peak at 2682 cm shows clearly the single layer characteristics
-1 indicates that
layer
characteristics
theweak
graphene
piece.
weak
D band
at 1340
cmthe
of the
graphene
piece. of
The
D band
atThe
1340
cm−1
indicates
that
sample has few
the
sample
has
view
defects.
defects.
system with a tetrakis(dimethylamido)hafnium(IV) (Sigma Aldrich) precursor. The growth
was carried out at 90 ◦ C with a 0.3 sec pulse time for the hafnium precursor, followed by a
50 sec purge time, 0.03 sec H2 O pulse, and 150 sec purge time. The resulting growth rate is
approximately 1 Å/cycle. The film thickness varies less than 2% across a 4” wafer and the
dielectric constant is approximately 13 as determined by capacitance versus voltage (CV)
measurements. The leakage current through the oxide is recorded throughout all device
measurements and is below the detection limit of our measurement setup (< 1pA).
Figure 2.2 shows an atomic-force microscope (AFM) image of single layer graphene
on SiO2 with 5 nm of HfO2 grown directly after mechanical exfoliation. We can still measure
the height of the graphene sheet (∼ 9 Å) and find it to be consistent with the previous
measurements [2, 7], suggesting that the growth is taking place at the same rate both on
the SiO2 surface and on the graphene. As the graphene lattice does not have any dangling
bonds on the surface, the growth is most likely due to physiosorption, which is enhanced
by the low-temperature growth procedure. Alternatively, growth may also nucleate from
ambient residues (e.g. water molecules or contaminants) adhering to the graphene surface.
The roughness of the oxide on top of the graphene is observed to be ∼ 30% higher than on
16
Figure
Atomic-force microscopy
(AFM)
image
of of
graphene
covered
withwith
HfOHfO
2 . 2.
Figure2.2:
2.2. Atomic-force
microscopy
(AFM)
image
graphene
covered
Graphene
sheet
covered
with
5
nm
HfO
prior
to
fabrication
of
any
contacts.
The
thickness
2
Graphene sheet covered with 5 nm HfO
2 prior to fabrication of any contacts. The thickness of
ofthe
thepiece
pieceisis99A°
Å suggesting
that
the
growth
suggesting that the growthtakes
takesplace
placeatatthe
thesame
samerate
rateon
onboth
bothSiO
SiO2 2 and
and graphene.
graphene.
the SiO2 , supporting the postulated growth mechanisms.
The final GFETs (Figure 2.3(a)) have source and drain regions that are electrostatically doped by the back gate, which enables control over the contact resistance and
threshold voltage of the top-gated channel. Figure 2.3(b) shows a GFET structure with
3-µm source-drain separation, a 1-µm top gate length, and a device width of 5 µm. In the
following section, we present representative measurement results for a similar device with a
width of 2.1 µm.
2.2.2
Device measurement
The low-temperature measurements are carried out at 1.7K (in a pumped helium cryostat)
with standard lock-in techniques. All room-temperature measurements are measured with
an Agilent 4155C Semiconductor Parameter Analyzer in a two-probe configuration at room
temperature using Cascade DCP-150 probes in a Cascade Summit 9000 probe station.
The degenerately doped Si substrate is used as the back gate. Throughout the entire
17
6RXUFH'UDLQHOHFWURGHV
a !"
*UDSKHQH
#"
b
7RS*DWH
6L2Հ
2 +m
6LVXEVWUDWH
+I2Հ
c
ï
[
d
VJVïEDFN = 40V
g ds (mS)
VJVïEDFN (V)
60
9
0.4
Figure 2.3:Figure
Basic
graphene
FET
design.
Schematic
depiction
2.3top-gated
Basic top-gated
graphene
FET
design. (a)
(a) Schematic
depiction
of an of an graphene
40
FET on a graphene
Si/SiO
substrate
with
a
heavily
doped
Si
wafer
acting
as
a
back-gate
2FET on a Si/SiO2 substrate with a heavily doped Si wafer acting as a back-gate and a gold
7
and
a
gold
top-gate.
(b) SEM showing
micrographashowing
a representative
graphenetop-gated
top-gated FET. The
top-gate. (b) SEM
micrograph
representative
graphene
FET.
The
Cr/Au
top-gate
of
this
device
is
1
um
long,
with
3
um
spacing
between
the source-drain
Cr/Au top-gate of this device is 1 µm long, with 3 µm spacing between the
0
source-drain
contacts. All electrodes are Cr/Au.
contacts. All electrodes are Cr/Au.
ï
ï
measurements leakage currents from the back and top gates are recorded. Leakage currents
ï
2 over the full bias range.
through the HfO2 top gate are always less than 0.5 pA/µm
ï
ï
ï
0
ï
f
2.3
ï
ï
0
VJVïWRS (V)
VJVïWRS (V)
e
0.8
VJVïWRS 9
Small-signal characterization 0.8
VJVïEDFN = ï9
0.6
g ds (mS)
g ds (mS)
In order to determine the effect of the HfO2 growth
on the electronic properties of the
0.6
0.4
graphene sheet,
we measure drain current (Id ) at source-drain voltage Vsd = 10mV as a
0.4
function ofback-gate voltage (Vgs−back ) before and after the HfO2 growth. Representative
curves for one sample with width of 1.5 µm and length
of 3 µm are shown in Figure 2.4.
0
ï
ï
ï
0
ï ï
0
40
60
While there is aïsmall
shift
in
the
Dirac
point, the mobility
of the
graphene
sheet
is largely
VJVïEDFN = 40V
VJVïWRS(V)
the same before and after HfO2 growth. Figure 2.5 shows source-drain small-signal conductance gds = (∂Id /∂Vsd )|Vgs−back ,Vgs−top , where Id is the current into the drain near Vsd ≈ 0V
for varying top-gate (Vgs−top ) and constant back-gate (Vgs−back = 0V ) bias. The hysteresis
hinders the extraction of the location of the Dirac point. We attribute the hysteresis to
trapped charges between graphene and the HfO2 and inside the dielectric. We perform
the room-temperature I-V measurements of Figure 2.7 with consistent Vgs−top sweep directions, allowing reproducibility of these measurements despite the effects of trapped charge.
18
of Vgs-back. TheThe
mobility
before and
after HfO
is
d as a2function
Figure 2.4: The Figure
effect2.4
of IHfO
on conductance.
mobility
before
and2 growth
after HfO
2 growth
largely unchanged measured at Vsd = 10 mV for a GFET device with width of 1.5 um
is largely unchanged
measured
and length
of 3 um. at Vsd = 10 mV for a GFET device with width of 1.5 µm
and length of 3 µm.
Figure 2.6 shows similar low-field transport characterization to Figure 2.5 at low temperature. These data are taken at 1.7K in order to suppress gate hysteresis by freezing out
trapped charge, allowing a more accurate estimate of the Dirac point and therefore top-gate
capacitance. The back-gate capacitance (Cback ) is approximately 12 nF/cm2 (thickness of
285 nm, κ ∼ 3.9). Sheet carrier concentrations (electrons or holes) in the source and drain
regions can be approximated by
n∼
=
q
0
)/e)2
n20 + (Cback (Vgs−back − Vgs−back
(2.1)
0
is the back-gate-to-source voltage at the Dirac point in these regions and
where Vgs−back
n0 is the minimum sheet carrier concentration as determined by disorders and thermal
excitation [72, 73]. The addition of the two quantities in the square root ensures a smooth
transition from minimum concentration limited regime to capacitively dominated one. From
0
the constant top-gate voltage slice of Figure 2.6(c), Vgs−back
= 2.7V , indicating slight p-type
doping, most likely due to impurities adsorbed to the graphene. Under the top gate, carrier
concentrations are determined by both the front and back gates,
n∼
=
q
0
0
n20 + [(Cback (Vgs−back − Vgs−back
) + (Ctop (Vgs−top − Vgs−top
)]/e)2
(2.2)
19
Figure 2.5 Room temperature low-field transport in top-gated GFET. g as
Figure 2.5: Room temperature low-field transport in top-gated GFET. gds asds a function of
a function of Vgs-top at Vgs-back = -40 V for both sweep directions. A hysteresis of
Vgs−top at Vgs−back
Vbe
forobserved
both sweep
directions.
1.26=V 0can
due to trapped
charges.A hysteresis of 1.26 V can be observed
due to trapped charges.
0
= 1.45V , where Ctop is the effective top-gate capacitance per unit area. The
with Vgs−top
slope of the dashed line shown in Fig. 2.6(a), which tracks the location of the Dirac point, has
the slope Ctop /Cback = 46, giving Ctop = 552 nF/cm2 , more than twice that of previously
demonstrated devices [86–89]. If one takes the top-gate capacitance as being the series
combination of the electrostatic capacitance (Ce ) of the gate dielectric and the quantum
capacitance (Cq ) [Eqn. 1.8], then
Ctop =
Cq Ce
Cq + Ce
(2.3)
We can approximate Cq = 2 µ F/cm2 for the relevant range of n (0.5 − 10 × 1012 cm−2 ),
then Ce = 762 nF/cm2 , which is in perfect agreement with the 760 nF/cm2 predicted
for the HfO2 gate insulator (thickness of 15 nm, κ ∼ 13). Even at this relatively large
insulator thickness compared to state-of-the-art silicon technology, quantum capacitance has
a significant effect on the total capacitance. Two representative constant back-gate voltage
slices at Vgs−back = 40 V and −40 V are shown in Fig. 2.6b and Fig. 2.6d, respectively. The
low-field field-effect mobility,
µF E =
1 L ∂gds
Ctop W ∂Vgs−top
(2.4)
7RS*DWH
6L2Հ
c !"
20
2 +m
6LVXEVWUDWH
ï
[
d#"
9
0.4
+I2Հ
60
VJVïEDFN = 40V
40
7
0
g ds (mS)
VJVïEDFN (V)
ï
ï
ï
ï
ï
ï
f $"0.8
0
VJVïWRS (V)
ï
ï
ï
0
VJVïWRS (V)
e%"
VJVïEDFN = ï9
VJVïWRS 9
0.8
g ds (mS)
g ds (mS)
0.6
0.4
0.6
0.4
0
ï
ï
ï
0
VJVïEDFN = 40V
40
60
ï
ï
ï
0
VJVïWRS(V)
Figure 2.6 Low-field transport in top-gated GFET at 1.7K. (a) Small-signal
source-drain
conductance
= 0 V asat
a function
Vgs-top
and Vgs-back at source-drain
Figure 2.6: Low-field
transport
in(gtop-gated
1.7 K.of(a)
Small-signal
ds) around VsdGFET
1.7K.
The
dashed
line
tracks
the
location
of
the
Dirac
point
for
the
top-gate
with aat 1.7 K. The
conductance (gds ) around Vsd = 0 V as a function of Vgs−top and Vgs−back
slope Ctop/Cback = 46. (b) gds as a function of Vgs-to pat Vgs-back = 40 V. (c) gds as a
dashed line tracks the location of the Dirac point for the top-gate with a slope Ctop /Cback =
function of Vgs-top at Vgs-back = -40 V. (d) gds as a function of Vgs-back at Vgs-top = -3 V.
46. (b) gds as a function of Vgs−top at Vgs−back = 40 V. (c) gds as a function of Vgs−back at
Vgs−top = 1.45 V. (d) gds as a function of Vgs−top at Vgs−back = −40 V.
of the device is approximately 1, 200 cm2 /V-sec; the conductance minimum is approximately
78.3µS = 2e2 /h. The conductance shown in Figs. 2.6b and 2.6d saturates for large top-gate
voltages due to the series resistance of the source-drain regions. For Vgs−back = 40 V, the
source and drain regions are n-type with a series resistances of approximately ∼ 1.2 kΩ
each; for Vgs−back = −40 V, the source and drain regions are p-type with series resistances
of approximately ∼ 700 Ω each.
21
a
b
1
1.2
VJVïEDFN = 40V
VJVïEDFN ï9
1
0.8
Id (mA)
Id (mA)
0.8
0.6
0.6
0.4
0.4
0.2
0
0.2
0
0.5
1
1.5
Vsd (V)
2
2.5
0
3
0
0.5
1
1.5
2
2.5
3
Vsd (V)
2.4
All
0.5
.LQN
High-bias characterization
3
0
ï
2
ï
measurements
1
in this section areVsdshown
for
(V)
ï
V JVïWRS (V)
0 0
Id (mA)
Id (mA)
Figure 2.7 Current-voltage characteristics of GFET device. (a) Drain current (Id) as a
Figurefunction
2.7: Current-voltage
characteristics
of GFET
(a) V,Drain
as a V,funcof source-to-drain
voltage (Vsd) for
Vgs-top =device.
-0.3 V, -0.8
-1.3 V,current
-1.8 V, -2.3
c ofand
d
V
= 40V
tion
source-to-drain
voltage
=
−0.3V,
−0.8V,
−1.3V,
−1.8V,
−2.3
V,
and
−2.8
-2.8 V(from bottom
to for
top)Vfor
V
=
40
V.
(b)
I
as
a
function
of
V
for
V
==
ï
40V
gs−top
VJVïEDFN
gs-back
d
sdJVïEDFN
gs-top
= 40V
V
JVïEDFN
V(from-0.3
bottom
top)V,for
V.V(b)
Id bottom
as a function
ofVVgs-back
Vgs−top
V, -0.8 to
V, -1.3
-1.8VV,
-2.3 V,=
and40-2.8
(from
to top) for
= -40
V. =
s d for
gs−back
1
−0.3V,1−0.8V, −1.3V, −1.8V, −2.3 V, and −2.8 V (from
bottom to top) for Vgs−back = −40
V.
0.5
.LQN
3
0
ï
ï
ambient conditions.
ï
V JVïWRS (V)
2
1
Figure 2.7(a)
and
Vsd (V)
0
0
(b)
show the measured Id as a function of Vsd (for different Vgs−top voltages) at Vgs−back of 40 V
and −40 V. Measurements are reproducible although we attribute the slightly negative gds
observed in saturation in, for example, Fig. 2.7b to residual trapped charge in the ALD oxide.
Figure 2.8(a) and (b) show the complete Id characteristics as a contour plot in the Vgs−top Vsd plane. To understand these curves, we focus first on the Id curve from Fig. 2.7(a) for
Vgs−top = −0.3 V, which shows a pronounced kink in the characteristic, shown in more detail
in Figure 2.9(a). Similar to the features observed in ambipolar semiconducting nanotube
FETs [90], these kinks in the Id characteristics signify the presence of an ambipolar channel.
The carrier concentration in the channel, shown schematically in Figure 2.9(b) for different
points in the I-V trace, is calculated using a field-effect model:
q
n(x) = n20 + (Ctop (Vgs−top − V (x) − V0 )/e)2
(2.5)
0.2
0
0.2
0
0.5
1
1.5
Vsd (V)
2
2.5
0
3
0
0.5
1
d #"
2.5
3
22
V
= 40V
VJVïEDFN = ï40V
JVïEDFN
VJVïEDFN = 40V
1
0.5
.LQN
3
2
1
ï
ï
V JVïWRS (V)
0 0
Vsd (V)
Id (mA)
1
Id (mA)
2
Vsd (V)
c !"
0
ï
1.5
0.5
.LQN
3
0
ï
2
ï
V JVïWRS (V)
1
ï
0 0
Vsd (V)
Figure2.8:
2.8 Current-voltage
Full
contour
plotplot
of Id of Id as
Figure
Current-voltage characteristics
characteristics in
in contour
contourplot.
plot.(a)(a)
Full
contour
as
a
function
of
V
and
V
at
V
=
40
V.
The
“kink”
produced
by
the
entry
of the
gs-topand Vsd
sd at V
gs-back
a function of Vgs−top
gs−back = 40 V. The kink produced by the entry of the
minimal
density
point
into
the
channel
is
noted
by
a
red
arrow.
(b)
Full
contour
plot
Id of I
minimal density point into the channel is noted by a red arrow. (b) Full contourofplot
d
function of
of VVgs-top and
V at Vgs-back
= -40=
V.−40 V.
asasa afunction
Vgs−back
gs−top andsdVsd at
0
0
− Vgs−back ) functions as a device threshold
+ (Cback /Ctop )(Vgs−back
where V0 ∼
= Vgs−top
voltage, controlled by the back-gate; x is the distance along the graphene channel; and
V (x) is the potential in the channel. For the device in Figure 2.9, with channel length L,
V (L) = Vsd , so that for Vsd ≤ Vsd−kink = Vgs−top − V0 current is carried by holes throughout
the length of the channel (Figure 2.9(b-I)). The linear relationship between Vgs−top and
Vsd−kink is also evident in the contour plots of Figure 2.8. For Vsd = Vsd−kink , the vanishing
carrier density produces a pinch-off region at the drain (Figure 2.9b-II) that renders the
current in the channel relatively insensitive to Vsd and results in the pronounced kink seen in
the I-V characteristic. For Vsd > Vsd−kink , the minimal density point resides in the channel,
producing a pinch-off region that moves from source to drain with increasing drain bias
magnitude (Figure 2.9b-III). In this bias range the carriers in the channel on the source
side of the minimal density point are holes, while those on the drain side are electrons.
The voltage drop across the hole portion of the channel remains fixed at Vsd−kink while
the voltage drop across the electron portion increases as Vsd − Vsd−kink . In this ambipolar
regime, the pinch-off point becomes a place of recombination for holes flowing from the
source and electrons flowing from the drain. Because there is no bandgap, no energy is
released in this recombination.
23
!"
#"
Figure Figure
2.9: Kink
effecteffect
in GFET
devices.
(a)(a)
Measured
Vgs−back
2.9 Kink
in GFET
devices.
MeasuredI-V
I-Vcharacteristic
characteristic atatVgs-back
= 40= 40
V and VVgs−top
==
−0.3
points(I,(I,
are identified
in the
I-V(b)curve.
(b) A
and Vgs-top
-0.3 V.
V. Three
Three points
II, II,
III) III)
are identified
in the I-V
curve.
A
schematic
demonstration
of the
carrier
concentration underneath
underneath the
region.
At At
schematic
demonstration
of the
carrier
concentration
thetop-gated
top-gated
region.
(VsdV<V
charge
at theatdrain
begins
decrease
the minimal
point Ipoint
(VsdI <
), the
thechannel
channel
charge
the end
drain
endtobegins
toasdecrease
as the
sd-kink),
sd−kink
density
point
enters
the channel.
At point
(Vsd =IIV(V
),
the
minimal
density
point
minimal
density
point
enters
the channel.
AtIIpoint
=
V
),
the
minimal
density
sd-kink
sd
sd−kink
forms at
at the
VsdV
>sdVsd-kink
(point III),
an electron
channel
forms
at the drain.
point forms
thedrain.
drain.ForFor
> Vsd−kink
(point
III), an
electron
channel
forms at the
drain.
We note that front-gated device structures are essential to provide the electrostatics
required for exploring high-bias operation of graphene field-effect transistors. The geometry
of back-gated GFET structures is constrained by the requirement that graphene be visible;
as a result, most GFET devices are built with a thick (∼ 300 nm) silicon dioxide dielectric
layer. Figure 2.10(a-b) show the I-V characteristics of two back-gated GFET structures of
widths 5.5 µm and 300 nm and lengths 3 µm and 150 nm, respectively. The long channel
device in Figure 2.10(a) shows a weak kink effect for Vds values around 1.5−2.0 V. The
effect is much less pronounced than for the top-gated device structures (Figure 2.7) because
of the inferior electrostatics coupling to the gate electrodes in the back-gated device; we
believe that out-of-plane fringing fields from the drain have a significant gating influence on
the graphene channel as electric field lines from the drain contact terminate in the graphene
24
!"
#"
Figure 2.10 I-V characteristics of back gated GFETs. I-V characteristics of back-
Figure 2.10: I-V characteristics of back gated GFETs. I-V characteristics of back-gated
gated GFET with a 300 nm-thick oxide. (a) Device width is 5.5 mm and length is 3
GFET with
nm-thick
oxide.= 9(a)
width
is 5.5 µm and
length
is 3 µm for
mm a
for300
Vgs-back
= 1 V to V
V inDevice
2 V steps.
(b) Short-channel
device
with width
gs-back
Vgs−back =
1V
Vgs−back
= 9nm
V showing
in 2 V steps.
(b) Short-channel
device
300
nmtoand
length 150
“punch-through”
behavior for
Vgs-backwith
= 14 width
V to 300 nm
and length
150=nm
punch-through behavior for Vgs−back = 14 V to Vgs−back = 17
Vgs-back
17 Vshowing
in 1 V steps.
V in 1 V steps.
channel. This reaches an extreme for short-channel-length devices at high values of Vds . As
shown in Figure 2.10(b), the drain current shows a sharp increase, very similar to punchthrough characteristics seen in short-channel-affected Si MOSFETs [91] as the gate loses all
control of conduction in the channel. At sufficiently high Vds , this runaway drain current
leads to irreversible thermal damage to graphene channels.
For the I-V curves at Vgs−back = −40 V and Vgs−top < −0.8 V (Fig. 2.7b), the
device shows flat saturating I-V characteristics (high-field regime for a unipolar channel).
To accurately model these characteristics, the drift velocity must be assumed to saturate
at some value vsat for electric fields beyond a critical electric field (Ecrit ). This is consistent
with the carrier drift velocity eventually saturating due to optical-phonon scattering, as
in the case of metallic nanotubes [92, 93]. For values of Vgs−top sufficiently negative, such
that Vsd−kink > Ecrit L, the I-V characteristics show a strongly saturating behavior in the
unipolar region with the kink indicating a transition to an ambipolar channel. Large enough
electric fields are reached in the channel at the drain end for the holes to reach saturation
velocity, resulting in an Id that becomes independent of Vsd .
25
2.5
Field-effect modeling
With this consideration, the current in the channel is expressed by [94]:
W
Id =
L
Z
L
en(x)vdrif t (x)dx
(2.6)
0
Where L is the channel length and W is the channel width. Current continuity forces a selfconsistent solution for the potential V (x) along the channel. We approximate the carrier
drift velocity (vdrif t ) by a velocity saturation model [95]:
vdrif t =
µE
1+
µE
vsat
(2.7)
where vsat is the saturation velocity of the carriers. For simplicity, we assume that both
electrons and holes are characterized by the same µ and vsat values in our model. A closedform analytical expression for Id can be derived using the expressions for n(x) [Eqn. 2.5]
and vdrif t [Eqn. 2.7] given above, we find:
Id =
R Vsd −Rs Id
W
L eµ Rs Id
p
n20 + (Ctop (Vgs−top − V − V0 )/e)2 dV
1+
µ(Vsd −2Rs Id )
Lvsat
(2.8)
where Rs is the source-drain series resistance. This can be integrated and the resulting
transcendental equation solved numerically. Figure 2.11(a) shows a comparison of this
model with the measured data at Vgs−back = −40 V. As input parameters, the fit uses a
low-field mobility of 550 cm2 /V-sec, a minimum sheet carrier density of 0.5 × 1012 cm−2 ,
and source-drain series resistances of 700 Ω, comparable to those found from the analysis
of Section 2.3. vsat for holes is found to vary between 6.3 × 106 cm/sec at high densities
(at n = 10 × 1012 cm−2 ) and 5.5 × 107 cm/sec at low densities (near n = n0 ). This
apparent dependence of vsat is clearly demonstrated in Figure 2.12, where we display the
vsat obtained from the model fit as a function of EF modulated by Vgs−top . Remarkably,
the observed vsat shows a linearly increasing trend with EF−1 . Within the relaxation time
approximation to the Boltzmann transport equation, we explain that such a relation is
indeed expected for hot carriers in graphene scattered by optical phonons. We assume a
model in which the coupling to the phonon is strong enough that once the electron reaches
I d (mA)
g m (mS)
0.8
0.6
26
0
a!"0.4
d#"
c 0.4
0.4 Vgs-top = ïV
1.2
0.2
1
g m (mS)
g m (mS)
+ data
ïPRGHO
Vgs-top = ï2.9
0.2
0
0
0.5
1
1.5
Vsd (V)
0.8
2
2.5
3
0.2
0.5
I d (mA)
v sat / vf
e 0.4 0
d 0.4 V
0.4
0.3
gs-top =
OV
Vgs-top = ïV
0.2
0.2
0.1 0
b
0
$"
0.6
0.4
00.5
2
g m (mS)
g m (mS)
b
0.2
0.2
0
0.5
4
1
1.5
Vsd (V)
2
2.5
6
8
1/EfH9 ï )
10
3
0
12
0.4
0.2
e
0
0
0.5
1
1.5
Vsd (V)
2
2.5
3
0.4
g m (mS)
v sat / vf
Field-effect
modeling
GFET device.
device. (a)
Model
(solid)
and measured
FigureFigure
2.11:2.11
Field-effect
modeling
ofofGFET
(a)
Model
(solid)
and measured
V
gs-top = OV
0.3
(dashed)
I
-V
curves
are
compared
for
V
=
40
V
at
V
=
0
V,
-1.5V,
(dashed) Id − V
Vgs−back = −40Vgs-top
at Vgs−top = 0-1.9V
V, -1.5V, d sdsdcurves are compared for gs-back
and
-3
V.
(from
the
bottom
to
the
top)
(b-c),
Small-signal
transconductance
(gm) as a(gm ) as
1.9V and -3 V. (from the bottom to the top) (b-c), Small-signal transconductance
0.2
function
of drain-to-source
voltagefor
(VV
) for V== -V1.5
V and
0.2
a function
of drain-to-source
voltage
1.5
and
0 V.0 V.
sdgs−top
gs-top
0.1
the energy threshold for phonon emission, it is immediately scattered. This means that the
0
0
2
0 current
0.5
1
1.5carried
2 by 2.5
6
8
10
12
Fermi sea
will 4be shifted
byïthe
phonon
energy
~Ω. The
density
such a3
1/EfH9 )
Vsd (V)
shifted sea in the direction of the applied electric field is given by:
Z
dk
vF cos2 θ~Ω
π2
j=e
∂f −
∂E E=~vF k
(2.9)
where θ is the angle between dk and the electric field and f is the Fermi-Dirac distribution
function. Writing the integral in polar coordinates,
Z
j=e
0
∞
dk
k
π2
Z
2π
dθvF cos2 θ~Ωδ(~vF k − EF ) =
0
e EF
Ω
π ~vF
(2.10)
√
Taking the current density to be j = nevsat , with EF = ~vF πn yields:
vsat = vF
~Ω
EF
(2.11)
This result implies that vsat is concentration-dependent for graphene; the higher the concentration, the lower the saturation velocity. While semiconductors have vsat values limited by
0
0
b
0.5
1
1.5
Vsd (V)
2
2.5
3
g m (mS)
0.2
0.2
27
0.5
0
e
0.4
Vgs-top = OV
0.3
g m (mS)
v sat / vf
0.4
0.2
0.1
0
2
4
6
8
1/EfH9 ï )
10
12
0.2
0
0
0.5
Figure
2.12 Density dependence of vsat. Measured
density dependence of vsat (red
Figure 2.12: Density dependence of vsat . Measured
density dependence of vsat (red crosses
crosses
as extracted
fromA the
fit). A least-squares
fitline)
(solid
blackEline)
between E of
as extracted
from the fit).
least-squares
fit (solid black
between
F of 0.1 eV and F
0.1
0.37 eV
determines
a slope which
phonon
energy
of 54
0.37 eV
eV and
determines
a slope
which corresponds
to a corresponds
phonon energytoofa 54
meV. A
fit that
passes
through
v
=
0
and
1/E
=
0
predicts
a
slightly
lower
phonon
energy.
F vsat = 0 and 1/EF = 0 predicts a slightly lower
meV. A fit thatsatpasses through
phonon energy.
the thermal velocity [96], vsat values for graphene are instead limited by vF . It is important
to note that this derivation assumes that this expression is not valid in the vicinity of the
Dirac point.
The solid line in Figure 2.12 represents the linear fit to this model from which we
obtained an optical phonon energy of 54 meV. Note that this value is close to the 59 meV
surface phonon energy of SiO2 [70, 97] and consistent with the observation of the effect of
this phonon energy on temperature-dependent low-field mobility [71]. We also remark that
this phonon energy is significantly below the 200 meV longitudinal zone boundary phonon
of intrinsic graphene [20], suggesting that the saturation velocity in future generations of
graphene transistors may be augmented by choosing different substrates with higher phonon
energies.
Figure 2.11(b-c) show the small-signal device transconductance (gm ) as a function
of Vsd for two different values of Vgs−top . Model and measurement show good agreement.
gm values exceed 320 µS/µm (∼ 150 µS/µm) for these 2.1-µm-channel-length devices
1
28
at Vgs−top = 0 V, Vgs−back = −40 V, Vsd = 1.6 V. Removing the effect of series resistance, the devices intrinsic transconductance is approximately 833 µS/µm at a vsat value
of 5.5 × 107 cm/sec. In comparison, velocity-saturated n-channel 65-nm Si MOSFETs
deliver transconductances of approximately 1.5 mS/µm with gate capacitances of approximately 1.77 µF/cm2 . At this gate capacitance, which is close to graphenes quantum capacitance, the graphene transistor would have a transconductance of more than 2.9 mS/µm.
As expected, and as is evident in Figure 2.11(c), the transconductance goes to zero at
Vsd = Vsd−kink . The highest transconductances are observed in the unipolar regime away
from Vsd−kink , which can be achieved by proper choice of V0 . Therefore the device is most
likely to be operated in the high-transconductance, velocity-saturated region with Vsd below
Vsd−kink .
2.6
Chapter Summary
In this Chapter, the fabrication of top-gated GFETs and both low- and high-bias measurements along with a FET model are presented. The current saturation observed at high bias
is the first experimental observation in graphene and supports the idea of using GFETs for
analog electronics. The importance of high gate efficiency in device structures is experimentally observed as back-gated devices suffer from short-channel like effects at high bias. The
observed current-voltage characteristics can be related to the zero-bandgap and ambipolar
nature of graphene and is modeled with a FET model. The saturation velocity is found to
be density dependent, a unique feature of the linear energy dispersion.
29
Chapter 3
Channel length scaling in GFETs
studied with pulsed
current-voltage measurements
In this Chapter, we investigate current saturation at short channel lengths in graphene
field-effect transistors as adopted from Ref. [98]. Dual-channel pulsed current-voltage measurements are performed to eliminate the significant effects of trapped charge in the gate
dielectric, a problem common to all oxide-based dielectric films on graphene. The transconductance of the devices is independent of channel length, consistent with a velocity saturation model of high-field transport. Saturation velocities have a density dependence
consistent with diffusive transport limited by optical phonon emission.
3.1
Introduction
Long-channel GFET operation has been thoroughly investigated in Chapter 2 and in other
experimental [99–104], as well as theoretical work [37–39, 105]. Saturating current-voltage
(I-V) characteristics have been observed down to channel lengths of 1 µm determined by the
interplay of velocity saturation and density-of-states modulation in the channel. However,
30
it is uncertain whether saturating characteristics will continue to be observed with scaling
channel length, given the absence of a band-gap and the dependence of this saturating
characteristic on inelastic scattering in the channel. This uncertainty has been augmented
by RF measurements of GFETs with channel lengths as short as 140 nm, which despite
demonstrating impressive unity-current-gain cutoff frequencies (fT ) of more than 300 GHz,
show non-saturating device characteristics [41]. Current saturation is necessary for both
voltage and power gain in these devices [106].
Here, we explore GFET devices using pulsed current-voltage (I-V) measurements,
which mitigate the effects of trapped charge in the gate oxide. When measured in this
manner, we show strong saturating I-V characteristics in even the shortest channel lengths
measured (130 nm), with output conductance in saturation of less than 0.3 mS/µm. The
resulting I-V characteristics are well modeled by a density-dependent saturation velocity.
Standard DC measurements of these same devices yield non-saturating characteristics and
systematically degrading device characteristics with decreasing channel length, demonstrating the importance of trapped charges in these measurements.
3.2
Device structure and fabrication
The GFET devices studied here consist of dual-gated structures (see Figure 3.1(a)), in
which the top gate extends to the contacts, minimizing access resistance to the channel.
The highly doped silicon substrate acts as a back gate. An important challenge to GFET
device fabrication remains establishing a reliable gate dielectric for the top gate. Atomiclayer deposition (ALD) of high−κ dielectric gate oxides has been demonstrated, utilizing a
seed layer [88,89,107,108] to facilitate ALD growth on the chemically inert graphene surface.
Typically, however, these seed layers either have to be thick for a reliable gate dielectric
or result in significant degradation of the mobility and substantial doping of the graphene
channel. Our approach employs polyvinyl alcohol (PVA), which relies on adsorption of the
PVA-carbon-chain to the graphene surface with the hydroxyl groups providing a surface
to seed ALD growth (see Figure 3.1(b)). In addition, PVA has a relatively high dielectric
31
6)
7)
?56==+@)A+=945)
<)
*)
'#)=>)
+)
(%&
)
)*+,-.+)/01
)2345)/01
)*+,(
)*+GFET
,(
Figure 3.1: Top-gated
device structure
with PVA. (%#
(a) Schematic of the devices with
U:8:
$%& functionalization layer used to
the top gate spanning the entire channel length. (b) PVA
!"#$%&'()*+,-!*)(./0(*1'230'32(*4/'5*6789!:&;!"#$%&'(#!)*!
$%#
nucleate the ALD growth of HfO2 films.
'%&
+$%!,%-.#%/!0.+$!+$%!+)1!2'+%!/1'33.32!+$%!%3(4%!#$'33%5!
'%#
5%32+$6!:<;!789!*:3#()3'5.;'()3!5'<%4!:/%,!+)!3:#5%'+%!+$%!9=>!
!"#$%&'&(
constant
(κ ∼ 6) [109], leading
to minimal gate capacitance
!"#$%&'&(
#%& reduction when it is present as
#)=>)
24)0+$!)*!?*@A!B5&/6!!
!"# !$# #
$# "#
a component of the gate stack. In this work, single-layer graphene
samples
are prepared
0
):0;
*678!964+
by mechanical exfoliation on silicon wafers (ρ ∼ 0.002 Ω−cm) with a ∼300 nm SiO2
layer. 1 nm Cr/ 80 nm Au source and drain contacts are deposited using standard e-beam
lithography techniques. After contact deposition, devices are annealed at 330 ◦ C for 3
hours in forming gas and subsequently dipped into a 1% aqueous solution of 85,000-125,000
molecular weight PVA (Sigma-Aldrich) for 12 hours. The samples are then rinsed with a
second dip into deionized water and blown dry with nitrogen resulting in an approximately
2.5-nm thick layer of PVA on the graphene surface.
Figure 3.2(c) shows resistivity measurements of a representative sample fabricated in
this manner after the annealing step and then after the PVA coating. Samples after forming
gas annealing are usually heavily p-doped in ambient, which remains unchanged with the
addition of the PVA layer. A brief UV/Ozone treatment is employed to activate the OH
groups before the ALD growth of hafnium oxide at 150 ◦ C with [(CH3 )2N]4Hf and H2 O for
50 cycles, yielding a 5-nm-thick film. Figure 3.2(a,b) shows atomic-force-microscopy (AFM)
images of two samples so prepared, one with a PVA layer and one without. Without PVA,
ALD growth proceeds only on the SiO2 area, leaving only patches of oxide at nucleation
sites formed most likely by surface contamination. With PVA, films grow uniformly on both
the SiO2 and graphene surfaces with a surface roughness of ±2.5 Å, compared to the film
roughness of ±2.0 Å on SiO2 . The breakdown electric field for the PVA/HfO2 dielectric
7)7)
<)
#"<)
<)
(%&
)*+,( )*+
)*+
,(,(
U:8:
)*+,( )*+
)*+,(,(
+)
'#)=>) '#)=>)
'#)=>)
!"#$%&'&(
!"#$%&'&(
!"#$%&'&(
!"#$%&'&(
!"#$%&'&(
!"#$%&'&(
#)=>)
+)+)
$"
))
(%&
(%&
)*+,-.+)/01
)*+,-.+)/01
)*+,-.+)/01
)2345)/01
(%#
)2345)/01 )2345)/01
(%#
(%#
$%&
$%&
$%&
$%#
'%&
$%#
$%#
'%&
'%&
'%#
'%#
'%#
#%&
#%&
#%&
#)=>)
#)=>)
32
U:8:
U:8:
!"7)
)
!"#
!"# !$#
!"##!$#
!$#$## # "#$#$# "#"#
):0;
0*678!964+0
):0;
0*678!964+
):0;
*678!964+
Figure 3.2: Effect of PVA growth. (a) AFM image of graphene on a SiO2 substrate after
the deposition of 5 nm of HfO2 without PVA, showing only patchy growth. (b) AFM
image of graphene on an SiO2 substrate after the deposition of 5 nm of HfO2 with a PVA
%&'$(")*"+,-"./)0(12"3!4!"#$!%&'()!*+!(,'-.)/)!*/!'!0%12!
functionalization layer, showing improved area coverage with a roughness of only
2.5Å. (c)
34536,'6)!'7),!6.)!8)-*3%9*/!*+!:!/&!*+!;+1
!<%6.*46!=>"?!
2
Resistivity of a device after annealing and then after the PVA deposition as a function of
3.*<%/(!*/@A!-'6B.A!(,*<6.C!3#4!"#$!%&'()!*+!(,'-.)/)!*/!
back-gate
bias. The doping and the mobility of the device stay relatively unchanged.
'/!0%12!34536,'6)!'7),!6.)!8)-*3%9*/!*+!:!/&!*+!;+12!<%6.!'!
stack is =>"!+4/B9*/'@%D'9*/!@'A),?!3.*<%/(!%&-,*E)8!',)'!
approximately 0.7 V/nm. We employ a 12-nm-thick oxide in the GFETs measured
B*E),'()!<%6.!'!,*4(./)33!*+!*/@A!2C:FC!3$4!G)3%39E%6A!*+!'!
subsequently to achieve a breakdown voltage of approximately 10 V. This oxide thickness
8)E%B)!'7),!'//)'@%/(!'/8!6.)/!'7),!6.)!=>"!8)-*3%9*/!'3!
yields a top-gate capacitance of Ctop−gate ≈ 600 nF/cm2 , as determined by the relative
'!+4/B9*/!*+!5'BHI('6)!5%'3C!J.)!8*-%/(!'/8!6.)!&*5%@%6A!*+!
coupling6.)!8)E%B)!36'A!,)@'9E)@A!4/B.'/()8C!
of the top and back gates [87].
!
3.3
Measurement and results
Devices were fabricated on multiple graphene samples with channel lengths, L, varying from
2.5 µm down to 130 nm. Due to the work-function mismatch between the graphene and the
metal contacts [110], the contacts are p-type. To avoid any additional resistance due to p-n
junctions at the source/drain contacts, subsequent large-signal characterization uses these
devices in the p-doped regime. Figure 3.3(a) shows high-bias measurements of a 2.5-µmchannel-length device, showing output characteristics similar to previous demonstrations at
these channel lengths. However, for a device of 350-nm channel length (see Figure 3.3b),
made from the same graphene sample, both the transconductance (gm = ∂Id /∂Vsg |Vsd )
and output conductance (g0 = ∂Id /∂Vsd |Vsg ), the product of which determines the intrinsic
voltage gain of the device, are heavily degraded. This degradation is systematically observed
with decreasing channel length. Here, Id is the drain current of the device, Vsg is the source-
!%!
'
()*'+,-.P,/
#%!
''
#%!#%!
!%6
!"#(&)#*'#
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0)*'+0/
7189,:,';
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P
,/ P,/
,
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1'
!
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!%"
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#
0)*'+0/
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$
7189,:,';,
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! ! $!! ""4!! #
5!!# $
=>1??@A'B@?;C>'+?,/
'+0/
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)*
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! $!! 4!! 5!!
=>1??@A'B@?;C>'+?,/
33
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#%!!%$
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! ! $!!" 4!! 5!!
#
=>1??@A'B@?;C>'+?,/
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7189,:,';,'+,<.P,/
()*'+,-.
"%!
*'
$%!
'
$%!
()*'+,-.P,/
()*'+,-.P,/
()*'+,-.P,/
()*'+,-.P,/
#%! DC current-voltage characteristics.
#%!
Figure 3.3:
(a) DC I-V measurements
of a 2.5-µm!"#(&)#*'#
!"#(&)#*'#
!"#(&)#*'#
!"#(&)#*'#
#%&
#%&
!"#$%&&'()*+,-)./'#$0.&.$)'&123$24!5.6!"#!$%&!'()*+,('(-.*!
channel-length
device.
Gate
voltage
varies
from
1.5
V
to
−1.5
V
on
−0.5−V
steps.
(b) DC
"%&
#%!"%&
#%!
/0!)!123%4'%56)--(7%7(-8.6!9(:;5(2!<).(!:/7.)8(!:),;(*!0,/'!
I-V measurements
of a 350-nm-channel-length
device fabricated"%&
from the same graphene
"%&"%!
"%!
sample.
The
strong
degradation
in
device
characteristics
is
clearly
"%!
"%! visible. (c) Maximum
=23!&!./!%=23!&!/-!%>23%&!*.(?*2!!576#"#!$%&!'()*+,('(-.*!/0!)!
!%&
!%&
transconductance as a function of channel
length. Transconductance
!%&
!%& (black squares), after
@3>%-'%56)--(7%7(-8.6!9(:;5(!0)A,;5).(9!0,/'!.6(!*)'(!
removing!%!
the effect of the contact resistance,
is also shown.
!%!!%!
!%!
8,)?6(-(!*)'?7(2!B6(!*.,/-8!9(8,)9)C/-!;-!9(:;5(!
!
"
#
! !
" "
# #
!
"
#
0
'+0/
0
'+0/
0
'+0/
0
'+0/
)*
)* )*
)*
56),)5.(,;*C5*!;*!57(),7D!:;*;A7(2!5$6!E)F;'+'!
gate voltage, and Vsd the source-drain voltage. The maximum transconductance drops by
.,)-*5/-9+5.)-5(!)*!)!0+-5C/-!/0!56)--(7!7(-8.62!!
more than a factor-of-two as the channel length is decreased from 900 nm to 150 nm as
B,)-*5/-9+5.)-5(!GA7)5H!*I+),(*JK!)L(,!,('/:;-8!.6(!(M(5.!/0!
.6(!5/-.)5.!,(*;*.)-5(K!;*!)7*/!*6/N-2!
shown
in Figure 3.3(c). Contact resistance, Rcontact , as extracted by fitting the channel
resistance Rds at Vds = 10 mV to
Rds = 2Rcontact +
L
p
W µe n20 + n2
(3.1)
where W is the width of the top-gated device, n is the carrier density modulated by the top
gate, µ is the low-field field-effect mobility, and n0 is the carrier density at the neutrality
point [108], varies between 190 Ωµm and 224 Ωµm for the devices studied here, scaling with
width rather than contact area [111]. Rcontact is expected to be more important at short
channel lengths as the relative contribution to the total device resistance becomes larger.
To account for the adverse effect of contact resistance, we rescale the source-to-drain and
0 = V − 2I R
0
source-to-gate bias according to Vsd
sd
d contact and Vsg = Vsg − Id Rcontact . In Fig-
ure 3.3(c), we plot the intrinsic transconductance after this contact resistance subtraction
along with the measured one. Despite the increase in the gm values, the decreasing trend
with channel length remains unchanged. It is well known that transport in graphene devices is heavily degraded by charge-traps in the oxide or graphene-oxide interface [112]. This
charge trapping is made worse by high drain-to-source biasing which strongly affect transis-
!
2'
Vg , Vd
%
'
$
"%&
"%!
!%&
!%!
!
!"#$
"
0)*'+0/
!%"
!%!
*' #"
current
#%! measurement
!"#(&)#*'#
()*'+,-.P,/
!"
"
#
0)*'+0/
7189,
!%!
%
#
time
()*'+,-.P,/
()
!%&
$%!
#%&
#%!
"%&
"%!
!%&
!%!
! $!! 4!! 5!!
34
=>1??@A'B@?;C>'+?,/
'
!"#(&)#*'#
!
"
0)*'+0/
#
Figure 3.4: Pulsed measurement technique. (a) Cartoon of how the pulsed measurement
technique works in the time domain. The current is measured only in the orange-marked
regions. (b) Pulsed I-V measurements of the same 350-nm device shown in Figure 3.3(b).
$%&'()"*(!'%+(*(,-"-(./,01%(2"3!4"&'(!""#$")$*"+$!*,$
-./0,1$2,'0.(,2,#!$!,3*#45.,$+"(60$4#$!*,$72,$1"2'4#8$
tor characteristics and can be expected to have a stronger impact in short-channel devices
9*,$3.((,#!$40$2,'0.(,1$"#/:$4#$!*,$"('#;,<2'(6,1$(,;4"#08$$
because of hot carrier injection [113]. Pulsed I-V measurements are a standard technique to
3#4$$=./0,1$><?$2,'0.(,2,#!0$")$!*,$0'2,$@AB<#2$1,C43,$
avoid these adverse effects [114, 115]. Figure 3.4(b) shows pulsed I-V characteristics of the
0*"+#$4#$D4;.(,EEE8$$
same 350 nm-channel-length device as in Figure 3.3(b), showing significant improvement
$
in both device transconductance and output conductance in saturation when employing
the pulsed measurement method. In these measurements, performed with a Keithley 4200
parametric analyzer, both gate and drain biases are pulsed with a pulse width of 500 ns
and period of 100 µsec. The back-gate is kept grounded throughout these measurements.
Pulsed measurements have little effect on device characteristics for channel lengths longer
than approximately 1 µm.
Figures 3.5(a,c) show detailed pulsed I-V measurements at L of 500 nm and 130
nm. Strong saturating characteristics are consistently observed in the I-V characteristics.
Figures 3.5(b,d) show the measured intrinsic device transconductance and the output con0 . The intrinsic transconductance (after contact resistance extraction) as function of Vsd
ductance of the 130-nm device exceeds 0.45 mS/µm and the minimum output conductance
is 0.3 mS/µm. Figure 3.6(a) shows the maximum transconductance and minimum output
conductance as a function of channel length. Both values are relatively independent of chan-
35
&
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9%!
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!"#$%&'()*'+%,$"-%+%./$0!1,2!"#$%&#'&(!")*!(+,%,($-%&'.('!
Figure
3.5: Pulsed I-V measurements. (a) Intrinsic I-V characteristics after the extraction
of
the
contact
resistance for a 500-nm device. Model fits are shown as solid lines. The
,/-%!$+-!-0$%,(.1#!12!$+-!(1#$,($!%-'&'$,#(-!21%!,!344)#5!
0 from 1.5 V to −0.5 V in 0.5 V steps. The neutrality point (V ) for
family of curves vary Vsg
0
6-7&(-8!!916-:!;$'!,%-!'+1<#!,'!'1:&6!:&#-'8!=+-!2,5&:>!12!
this device is 1.67 V. (b) Intrinsic transconductance and output conductance for the same
0 . Model fits are shown as solid lines. (c) Intrinsic I-V
500-nm
device as a function
of Vsd
(?%7-'!7,%>!!"
#$!2%15!@83!*!$1!)483!*!&#!483!*!'$-A'8!=+-!
characteristics for a 130-nm device for the same gate voltage values as in (a). V0 = 2.2 V.
#-?$%,:&$>!A1&#$!B!
%C!21%!$+&'!6-7&(-!&'!@8DE!*8!132!"#$%&#'&(!
(d)
Intrinsic transconductance
and output conductance for the same 130-nm device.
$%,#'(1#6?($,#(-!,#6!1?$A?$!(1#6?($,#(-!21%!$+-!',5-!344)
nel
length, indicating that velocity saturation
is the dominant cause of current saturation.
#5!6-7&(-!,'!,!2?#(.1#!12!!
#&8!!916-:!;$'!,%-!'+1<#!,'!'1:&6!
:&#-'8!142!"#$%&#'&(!")*!(+,%,($-%&'.('!21%!,!@F4)#5!6-7&(-!21%!
$+-!',5-!G,$-!71:$,G-!7,:?-'!,'!&#!B,C8!!%HI8I!*8!!1&2!"#$%&#'&(!
$%,#'(1#6?($,#(-!,#6!1?$A?$!(1#6?($,#(-!21%!$+-!',5-!@F4)
3.4
Modeling and discussion
#5!6-7&(-8!!
For sufficiently high vertical electric fields in the channel such that, Vsg + V0 Vsd , where
V0 is Vgs (= −Vsg ) at the Dirac point, the density variation in the channel can be ignored.
In this case, the drain current is given by Id = nevdrif t and the drift velocity (vdrif t ) can
"!
:!
#!
JK&0L>8E12
=!
& !" +&
!%"
&
A&
!%#
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!
!%# !%# !%$ !%<
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! #$&0>2
&
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! #$&0>2
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36
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<
$
&!"#&G&9%=>
#
&!"#&G&9%!>
"
!
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!
9!
"!
:!
#!
=!
JK&0L>8E12
&
$
&09! &E18@+E2
&
Figure 3.6: Small-signal
parameters. (a) Maximum intrinsic transconductance and mini9"
$%!&&'()*+!&",!-!%./.-(0"1!2!"#$%&'&!%()*%(+%,!
mum output conductance as a function of channel length. (b) Drift velocity as a function
9!
of transverse electric field in the channel for the 130-nm-channel-length device for three
)*#(+,-(.',)#(,/!#(.!&%(%&'&!-')0')!,-(.',)#(,/!#+!#!
different gate <
voltages. The solid curves show fits calculated from the Thornbers equation
1'(,2-(!-1!,3#((/4!4/(5)36!!1#2!7*%8!9/4-,%):!#+!#!1'(,2-(!-1!
for β = 2. β =$1 is shown in dashed for comparison.
)*#(+9/*+/!/4/,)*%,!;/4.!%(!)3/!,3#((/4!1-*!)3/!<=>?(&?
&!" G&9%=>
#
then be directly determined from
drain current. As shown in Figure 3.6(b), we find
&!" the
G&9%!>
"
,3#((/4?4/(5)3!./9%,/!1-*!)3*//!.%@/*/()!5#)/!9-4)#5/+6!A3/!
&!" G&!%=>
0 /L, is accurately modeled by
that vdrif t as a function of transverse electric field, Ey = Vsd
!
+-4%.!,'*9/+!+3-B!;)+!,#4,'4#)/.!1*-&!)3/!A3-*(C/*D+!
!%#
!%$
!%<
! 9! "! :! #! =!
Thornbers equation [116]
/E'#2-(!1-*!FGH6!FG<!%+!+3-B(!%(!.#+3/.!1-*!,-&0#*%+-(6!!
J &0L>8E12
! &0>2
AI5D/
#&
&H
.;&0178P12 .1&0178P12
%!
!%=
#&
#&
!%"
"
K
#$
vdrif t =
1
µEy
β
+
1
vsat
β !−1/β
(3.2)
with β ≈ 2, vsat is the saturation velocity, and µ the zero-field mobility, consistent with
other studies for oxide dielectric interfaces [104]. Such phenomenological modeling is commonplace in semiconductor device compact modeling and complements microscopic calculations [103].
Figure 3.7(a) shows the field-effect mobility (µ) and minimum charge-density (n0 )
as a function of L, extracted from the low-field channel conductance of the pulsed measurements. The coefficient of variation of the root-mean-square error of these fits is better than
3.5% over the full gate bias range. The same results are achieved from dc measurements, indicating that the pulsed measurements have no effect on low-field transport. The field-effect
mobility increases from 640 cm2 /V-sec at 130-nm channel length to ∼1500 cm2 /V-sec once
a channel length of 500 nm is reached. n0 follows a similar trend, decreasing from 3.4 × 1012
-$
P"
($$
$
"
!"
#"
#"
($$
)
%$$
&$$
'$$
+,!--./"0.-12,"3-45
"
37
")%$"-4
"%=$"-4
"=$$"-4
"&$$"-4
)<=
?
*
>9!2"3)$ "6479.65
)*
)*$$
;*
%
*
P"364 78"9.65
*<$
:
)&$$
-$"3)$ "64 5
!"
)
)<$
$
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%$$
&$$
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+,!--./"0.-12,"3-45
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*<:
%<*
)7*
:<$
:<(
;?
)7- "3)$ "645
")%$"-4
>9!2"3)$ "6479.65
*<$ Channel-length scaling. (a) Field-effect mobility and impurity density versus
Figure
3.7:
$%!&&'()('&*+%",-!(.&*/!0!1!"#$%&'$($)*!+,-#%#*.!/0&!
"%=$"-4
"=$$"-4
channel length. The
dashed lines are guides to the eye. (b) Saturation velocity as a func√
#+123#*.!&$04#*.!5$3424!)6/00$%!%$07*68!96$!&/46$&!%#0$4!
"&$$"-4
tion of 1/ n calculated
at the source end for different channel lengths. The dashed line
/3$!72#&$4!*,!*6$!$.$8!0#1!:/*23/;,0!5$%,)#*.!/4!/!<20);,0!
corresponds
to an optical phonon energy of 54 meV.
)<=
?
,<!!=>?@4A3*B0C=!)/%)2%/*$&!/*!*6$!4,23)$!$0&!<,3!&#($3$0*!
−2 at L = 130 nm to 0.92 × 1012 cm−2 once L = 500 nm is reached. We believe that this
cm)6/00$%!%$07*648!!96$!&/46$&!%#0$!),33$41,0&4!*,!/0!,1;)/%!
µ 16,0,0!$0$37.!,<!!"#$%&'!!
degradation at short channel lengths is due to e-beam damage from the metal-contact
)<$
fabrication in
of the
[117]. This degradation at short channel lengths
*<: the vicinity
%<*
:<$ contact:<(
)7*
;?
)7- to
"3)$
"645
has also been attributed
a cross-over
from diffusive to quasi-ballistic transport [118]. For
the relatively short low-field mean free paths (28 nm at the highest carrier densities) in these
devices, this mechanism is unlikely. We note that despite the degradation in low-field transport with decreasing channel length, high-field transport is unaffected, supporting a model
for high-field diffusive transport that is independent of impurity scattering and determined
by phonon emission.
Further support for the phonon emission model comes from the density-dependence
of the saturated velocity, vsat . Figure 3.5(a-d) shows a simple model fit (solid curves) along
with the measured data for the I-V characteristics. In this case, vsat is treated as a fitting
parameter and the extracted vsat values are shown in Figure 3.7(b) as a function of sheet
density. The density dependence is consistent with a simple phonon emission model given in
Chapter 2, Eqn. 2.11. The extracted phonon energy in this model (~Ω) is approximately 54
meV, close to the phonon energies previously reported for similar device sturucters [104,119].
38
vsat is independent of channel length down to the shortest gate lengths measured, indicating
that transport is diffusive in the high-bias regime.
3.5
Chapter Summary
In summary, we have investigated channel length scaling in GFETs down to 130-nm channel
lengths. When characterized with dc I-V measurements, we observe a systematic degradation of device performance with decreasing channel length and attribute this effect to
trapped charges in the gate dielectric. High-bias measurements made with a dual-channel
pulsed-measurement method show current saturation even at the shortest channel lengths.
Measured transconductances and output conductance are significantly improved, demonstrating the importance of trapped charge on the device performance. A method to functionalize graphene with PVA is demonstrated that enables reliable high−κ ALD growth
down to 5 nm thickness.
39
Chapter 4
Graphene field-effect transistors
based on boron nitride gate
dielectrics
In this Chapter, we describe graphene field-effect transistors utilizing single-crystal hexagonal boron nitride (h-BN) as the gate dielectric as published in Ref. [120] and [121]. The
devices exhibit mobility values exceeding 10,000 cm2 /V-sec and current saturation down
to 500 nm channel lengths with intrinsic transconductance values above 400 mS/mm. The
work demonstrates the favorable properties of using h-BN as a gate dielectric for graphene
FETs.
4.1
Introduction
One of the major obstacles to the development of graphene field-effect transistors (GFETs)
remains engineering the dielectric interfaces to the graphene. With the exception of suspended graphene samples [77, 78], which are not practical for devices due to limitations on
device architecture and functionality, most GFETs are fabricated on silicon dioxide substrates and top-gated with high−κ gate dielectrics grown on the graphene. The deposition
40
!"
#"
$"
&'(%
&*'(%
)'(%
!"#$%
Figure 4.1: h-BN structure. (a) Atomic structure of hexagonal boron nitride (b) optical
h-BN
structure. (a) Atomic structure of hexagonal boron nitride
micrograph of exfoliated h-BN (c) AFM image of h-BN showing different layer thickness.
(b) optical micrograph of exfoliated h-BN (c) AFM image of hthese top gate dielectrics often involves the initial deposition of a noncovalent functionBNofshowing
different layer thickness %
alization layer absorbed on the graphene surface such as in Chapter 3 and Ref. [107, 108].
Both the top-gate oxide and supporting oxide substrate significantly degrade the electronic
properties of the graphene. Charged impurities trapped in the dielectrics or at the graphenedielectric interfaces dope the graphene, form inhomogeneous networks of electron hole puddles [73], may significantly degrade mobility, and can result in hysteretic current-voltage
characteristics. Surface polar optical phonons from the substrate limit room temperature
transport [71] and achievable saturation velocities [34]. In this paper, we present the first
measurements of GFETs utilizing hexagonal boron nitride (h-BN) as both a gate dielectric and supporting substrate, resulting in dramatically improved transistor current voltage
characteristics.
4.2
Basic device structure
h-BN is an insulating isomorph of graphite with only %1.7 lattice mismatch [122] (Figure 4.1(a)) with boron and nitrogen atoms occupying the equivalent A and B sublattices
in the Bernal structure. The hexagonal structure with strong in-plane bonding makes the
surface chemically inert and free of dangling bonds and surface charge traps. The surface is
also atomically flat over large areas. The bandgap (5.97 eV) [123] and dielectric properties
NATURE NANOTECHNOLOGY
b
d Water-soluble
PMMA
Graphene
layer
DOI: 10.1038/NNANO.2010.172
41
Glass slide
Si/SiO2
DI water
(i)
Floating
PMMA
(iii)
BN
(ii)
(iv)
Graphene
er process. a–c, Optical
images
ofMechanical
graphene (a)transfer
and h-BN
(b) before
and after (c)
transfer. Scaleofbars,
mm. Inset: electrical
Figure
4.2:
process.
A schematic
representation
the 10
mechanical
!"#$%&'#%()*+%&,-"+).+/#",,0)!"#$%&'()$"
ation of the transfer process
to fabricate
graphene-on-BN
devices
text surface
for details).
transfer used
process.
(i) Mechanical
exfoliation
on (see
PMMA
that has a water-soluble
*&+*&#&,-().,"./"-%&"'&$%(,0$(1"-*(,#/&*"+*.$&##2"304"
layer underneath.
(ii) Water-soluble layer is dissolved on top of a DI water bath, (iii) the
floating film
is transferred over to a glass slide with a whole in it. (iv) The exfoliated flake
5&$%(,0$(1"&6/.10().,".,"755!"#8*/($&"-%(-"%(#"("
on the PMMA membrane bis aligned
under the microscope to the target and brought into
Graphene
BN
Graphene
9(-&*:#.18;1&"1(<&*"8,=&*,&(-%2"!11"(*&".,"-.+"./"("
contact.
BN
#010$.,"$%0+"3004">(-&*:#.18;1&"1(<&*"0#"=0##.1?&=".,"-.+"./"
SiO2
of h-BN (
∼3-4 and VBreakdown ∼ 0.7 V/nm) compare favorably with SiO2 . The excellent
("@A"9(-&*";(-%B"30004"-%&"C.(),D"E1'"0#"-*(,#/&**&=".?&*"
Frequency (a.u.)
thermal conductivity
of h-BN, 600 times higher then silicon dioxide, is also advantageous for
-."("D1(##"#10=&"90-%"("9%.1&"0,"0-2"30?4"F%&"&6/.10(-&="C(G&"
.,"-%&"755!"'&';*(,&"0#"(10D,&="8,=&*"-%&"
FET applications
to minimize device heating. To fabricate graphene-on-BN, we employ a
'0$*.#$.+&"-."-%&"-(*D&-"(,=";*.8D%-"0,-."$.,-($-2""""
mechanical transfer process in which h-BN layers are exfoliated from ultra-pure h-BN single
crystals that were grown by the method described in Ref. [124]. The optical contrast on
the SiO2 /Si substrate is sufficient to identify h-BN flakes less than 1 nm thick as shown in
Figure 4.1(b) [125]. The surface of every target h-BN flake is first characterized by atomic
−1.0
−0.5
0.0
0.5
1.0
force microscopy to ensure it is free of contaminants
step edges, and also to measure
Heightor
(nm)
its thickness. Figure 4.1(b-c) shows an example optical and AFM image of a clean h-BN
oscopy. a, AFM image
of monolayer
graphene
on BNWhile
with electrical
leads.
dashed
lines is
indicate
edge of the graphene
surface
on a SiO
the texture
ofWhite
the SiO
visiblythe
apparent,
2 substrate.
2 surface
ogram of the height distribution (surface roughness) measured by AFM for SiO2 (black triangles), h-BN (red circles) and
the h-BN is approximately three times less rough. The transfer process is illustrated in
es). Solid lines are Gaussian fits to the distribution. Inset: high-resolution AFM image showing a comparison of graphene and BN
e dashed square in a.Fig.
Scale
0.5 mam.metal gate (1nm Cr / 20 nm AuPd) electrode is patterned with e-beam
4.2.bar,
First,
lithography on SiO2 substrates. Next, we mechanical exfoliate h-BN single crystals onto
scattering rate due to charge impurities in the full-width at half-maximum (FWHM) of r(Vg) is !1 V,
silicon
wafers in
coated
onto a polymer
stack
consisting
a water-soluble
layer (PVA)
degree of short-range
scattering,
comparigiving an
upper
boundoffor
disorder-induced
carrierand
density fluctu10
22
ples. This suggests PMMA
that the(Fig.
sublinear
shape
d
n
,
7
×
10
cm
,
a
factor
of
!3
improvement
over
ation
of
4.2(i)) and the substrate was floated on the 12
surface of a deionized water bath.
reased short-range scattering on BN sub- SiO2-supported samples . An alternative estimate of this inhomsubstantially reduced charge impurity con- ogeneity is obtained from the temperature dependence of the
the effects of short-range scattering at minimum conductivity. In Fig. 3c, smin increases by a factor of
sities. Similar behaviour was observed in two between 4 K and 200 K. Such a strong temperature dependence
r graphene samples and, importantly, we has previously only been observed in suspended samples, with sub-
42
*%
3%
!"#$%
/012%
&'%
()*+,-.-%
Figure 4.3: Back-gated GFET with h-BN gate dielectric. (a) Schematic of the back-gated
GFET
with
h-BNIngate
dielectric.
(a)channel lengths
deviceBack-gated
structure. (b) Optical
image
of GFETs.
this case,
three different
are fabricated
out of of
thethe
sameback-gated
graphene/BN flakes.
Schematic
device structure. (b) Optical
image of GFETs. In this case, three different channel
lengths are fabricated out of the same graphene/BN flakes.
bath (Fig. 4.2(ii)), leaving the extremely hydrophobic PMMA floating on top. The PMMA
!
Once the water- soluble polymer had dissolved, the Si substrate sank to the bottom of the
membrane was adhered to a glass transfer slide (Fig. 4.2(iii)), which was clamped onto the
arm of a micromanipulator mounted on an optical microscope. Using the microscope to
optically locate the position of the h-BN flake on the suspended polymer film, the flake
was precisely aligned to the target metal gate and the two brought into contact. With this
technique, the h-BN could be positioned to within a few micrometres of the target position.
During transfer, the target substrate was heated to 130 ◦ C in an effort to drive off any
water adsorbed on the surface of the h-BN flake, as well as to promote good adhesion of
the PMMA to the target substrate. Once transferred, the PMMA was dissolved in acetone
(Fig. 4.2(iv)) and the sample was annealed in flowing H2 /Ar gas at 340◦ C for 3.5 hours. An
almost identical procedure is followed for graphene transfer that was exfoliated separately
on a similar surface where the PMMA thickness was precisely tuned to allow identification
of monolayer graphene by optical means. The devices shown in Figure 4.3 are measured
to have a dielectric thickness of approximately 8.5 nm. Because the h-BN can be made
arbitrarily thin (down to a single monolayer) our device geometry allows us to utilize the
43
Figure 4.4: Low-field transport characteristics of GFET device with h-BN. R = 1/gds at
offield-effect
GFETmobility can
Vds = 10 mVLow-field
as a function transport
of Vgs for W/Lcharacteristics
= 3.4 µm/2.8 µm. The
be extracteddevice
from the with
slope ash-BN.
µ ≈ 11, 000
cm2 /V sec. ds}$ at $V_{ds} =
$R=1/g$_{
10$ mV as a function of $V_{gs}$ for $W/
same h-BN dielectric layer as both a supporting substrate and local-gate dielectric. This,
L=3.4~\mu \rm m/2.8~\mu $m. The field-effect
therefore, allows
us to fabricate
theextracted
required FETfrom
structure
mobility
can be
thewithout
slopeanasadditional
$\mu top gate.
Cr/Pd/Au (1nm/20
nm/90
nm) electrodes
are usedsec.
as Ohmic contacts, producing p-type
\approx
11,000
$ cm$^2$/V
doping of the graphene under the contacts because of work-function differences. After transfer, the graphene on h-BN (as measured by atomic force microscopy) seems to conform to
the atomically flat h-BN, consistent with previous reports on both rippled [15] and flat [126]
surfaces.
4.3
Low-field transport
Figure 4.4 shows the channel resistance (Rds ) at Vds = 10 mV as a function of Vgs for a
W/L = 3.4 µm/2.8 µm device. Low-field mobility of these devices exceeds 10, 000 cm2 /V
sec, as extracted from fits to the low-field transport measurements using Eqn. 3.1. The
minimum sheet carrier concentration n0 as determined by disorder and thermal excitation
is approximately 2.2 × 1011 cm−2 . The gate capacitance, Cg ≈ 363 nF/cm2 , is given
by the parallel combination of the electrostatic capacitance of the gate and the quantum
capacitance of graphene (which ultimately limits achievable gate capacitances). There is
44
!"
#"
!"#$"
$"
&'(("#$"
%"#$"
Figure 4.5: Current-voltage characteristics of GFET devices with h-BN. (a) 3 µm channel
length, (b) 1 µm channel length, (c) 0.44 µm channel length for Vgs = −2V to 0V in 0.5V
steps.Current-voltage characteristics of GFET devices with h-BN. (a)
3 $\mu$m channel length, (b) 1 $\mu$m channel length, (c) 0.44 $
!" \mu$m channel length for
#" $V_{gs}= -2$V to 0V in
$" 0.5V steps.
!"#$%&!'
!"#$%&!'
!"#$%()*!'
!"#$%(!'
!"#$%+)*!'
!"#$%()*!'
!"#$%(!'
!"#$%+)*!'
!"#$%&!'
!"#$%()*!'
!"#$%(!'
!"#$%+)*!'
Figure 4.6: Intrinsic device IV characteristics. Intrinsic IV curves after the contact resischaracteristics.
Intrinsic
IV curves
after
the3 contact
tance Intrinsic
extraction device
from theIV
measured
curves of Fig.
4.5. Channel
length
of (a)
µm; (b) 1
resistance
extraction
from
the lines)
measured
curves
of Fig.~\ref{fig:bnIV}.
µm; and
(c) 0.44 µm.
Model fits
(solid
are shown
along
with measured data.
Channel length of (a) 3 $\mu$m; (b) 1 $\mu$m; and (c) 0.44 $\mu$m.
fitsof(solid
lines) are
shown
along
with measured
data.
almostModel
no doping
the graphene
channel
with
the location
of the Dirac
point given by V0 =
−0.07 V and with a gate-voltage hysteresis of less then 10 mV at room temperature. BNsupported devices appear to be more stable compared to their SiO2 -supported counterparts,
as heating and high-bias stress have virtually no effect on the transport characteristics.
For a p-type channel (matching the doping of the source and drain contacts), the contact
resistance is approximately 673 Ω/µm. n-type channels show a contact resistance that is
approximately 31% higher for this device geometry because of the additional resistance of
the p-n junction at the source/drain; therefore, subsequent large-signal characterization are
performed with these devices as pFETs.
45
!"
#"
!"#$%()*!'
!"#$%&!'
!"#$%(!'
!"#$%+)*!'
!"#$'+!'
Figure 4.7: Intrinsic small-signal transconductance. (a) gm as a function of drain-to-source
voltage
(Vsd ) for small-signal
0.44 µm channel transconductance.
length. (b) Maximum intrinsic
transconductance
as a
Intrinsic
(a) $g_
m$ as
function channel length. The dashed line shows the average value of 415 mS/mm.
a function of drain-to-source voltage ($V_{sd}$) for 0.44
channel length.on
(b)h-BN
Maximum
intrinsic
4.4$\mu$m
I-V characteristics
supported
devices
transconductance as a function channel length. The
Figure
4.5 shows
I-V characteristics
measured
from
with channel lengths of 3
dashed
linetheshows
the average
value
ofdevices
415 mS/mm.
µm, 1 µm, and 0.44 µm. In the unipolar regime, Vsd < Vsd−kink , the GFETs show satu-
'
rating I-V characteristics, where Vsd−kink is the drain bias at which the Dirac point enters
the channel as described in Chapter 2. Because these devices are still limited by contact
resistance, intrinsic device I-V characteristics are shown in Figure 4.6 after the extraction
of the measured contact resistance. The 0.44-µ-channel-length device shows an intrinsic
Ion of more than 1 mA/µm. Figure 4.7(a) shows the associated intrinsic transconductance
for this same 0.44-µm-channel-length device as a function of Vsd for different values of Vgs .
The peak intrinsic transconductance, obtained after the extraction of the contact resistance
exceeds 400 mS/mm and is independent of channel length as plotted in Figure 4.7(b), consistent with velocity-saturation-dominated transport. This value is approximately 2.6 times
higher than the value on SiO2 -supported samples in Chapter 2, even though the effective
gate capacitance is 30% lower.
46
!"#$%&'()&
Figure 4.8: Saturation velocity in GFETs with h-BN dielectric. Saturation velocity plotted
Saturation
indensity
GFETs
h-BN
dielectric.
Saturation
versus
square rootvelocity
of the drain
for with
different
channel
lengths as extracted
from the
model
fits.
The
dashed
line
shows
a
slope
corresponding
to
~Ω
=
40
meV.
velocity plotted versus square root of the drain density for different
channel lengths as extracted from the model fits. The dashed line shows
4.5
Device
modelingtoand
saturation
velocity
a slope
corresponding
$\hbar
\Omega=40$
meV.
The field-effect modeling of the devices is carriered out with a similar approach to Chapter 2 (these model fits are shown in Fig. 4.6). The carrier-dependent saturation velocity
(vsat ), which assumes a simple nonequilibrium Fermi surface is given by the expression
in Eqn. 2.11, and approaches vF for ~Ω EF . Furthermore, we explicitly include the
density-dependence of vsat self-consistently in the current-voltage model, which was not
√
done in previous analyses. Figure 4.8 shows vsat as a function of 1/ n (for an overdrive
sufficiently large to ensure a unipolar channel) where n is taken at the drain of the channel
for three different channel lengths. vsat exceeds 1.14 × 107 cm/sec at sheet densities of
more than 4.5 × 1012 cm−2 , more than two times higher than results on SiO2 -supported
devices with high−κ gate dielectrics. The slope of the curves indicates the optical phonon
energy of approximately 40 meV, significantly less than the surface polar optical phonon
energy (SPOPE) of 100 meV for h-BN. Such lower energies have been observed consistently
for GFET devices at high densities as shown in the previous chapters. The discrepancy
between the measured optical phonon energy and the SPOPE of BN remains the subject
47
of active investigation.
4.6
Chapter Summary
In summary, the implementation of h-BN as both the gate dielectric and substrate in
graphene FETs is presented. The excellent match of the graphene and h-BN crystal structures and the favorable properties of BN as a dielectric makes the presented devices an
ideal approach for GFET fabrication. The low-field transport measurements are clear evidence to the improved dielectric/dielectric-graphene interface with improved mobility and
reduced hysteresis. I-V measurements at high-bias support the improved device characteristics. GFETs show saturating output characteristics down to the shortest channel lengths
measured, with no degradation in small-signal parameters such as transconductance. The
enhanced transistor performance is also evident from the the fact that regular dc measurements are sufficient and pulsed measurements do not have any influence on the output
characteristics.
48
Chapter 5
High-frequency characterization of
GFETs
In this Chapter, the high-frequency performance of two different type of graphene fieldeffect transistors is investigated. The first ones are top-gated devices similar to the ones in
Chapter 2 and represent the first experimental high-frequency measurements of (GFETs)
as published in Ref. [35] . These FETs exhibit a unity cut-off frequency, fT , of 14.7 GHz
for a 500-nm-length device. The second type of GFETs, a heterostructures consisting of
graphene devices fabricated on h-BN, demonstrate substantially improved dc and highfrequency performance. These devices show saturating IV characteristics and fmax values
as high as 34 GHz at 600-nm-channel length. Bias dependence of fT and fmax and the effect
of the ambipolar channel on transconductance and output resistance are also examined. A
small-signal model is introduced to characterize the RF measurements.
5.1
Introduction
The interest in graphene for electronics is primarily on analog and RF applications of
graphene FETs (GFETs) because of the limited on-current-to-off-current ratios achievable
with this zero-bandgap material [106]. For RF applications the most widely used figure-ofmerit to quantify transistor performance is the unity cut-off frequency (fT ), defined in the
49
simplified small signal model to be [50]:
fT =
gm
2πCg
(5.1)
where gm and Cg are the transconductance and gate capacitance, respectively. If a velocity
saturation model is assumed–a realistic assumption for short channel devices–gm can be
expressed as gm = Cg W vsat [127], when plugged into Eqn. 5.1 reduces fT to:
fT =
1 vsat
2π L
(5.2)
From this simplified expression, it is straightforward to see that the high-frequency performance can be improved in two possible ways; the channel length L can be reduced, or
vsat can be increased. In fact, minimizing L has been the driving force for silicon channel
length scaling. However, the minimum possible channel lengths are rapidly approached
in semiconductor technology, leaving vsat as the only possible alternative to improve RF
performance. Graphene has emerged as a replacement material because of its potential for
high saturation velocity.
Within the last few years, the RF performance of GFETs, as determined by the
device current-gain cut-off frequency, has gone from 15 GHz [35] for 500-nm-length devices
in the first measurements to 155 GHz at 40-nm channel lengths in recent reports [128]. In
the rest of this chapter high-frequency performance of GFETs will be demonstrated.
5.2
RF performance of top-gated GFETs
In this section, we present the first RF measurements of graphene field-effect transistors,
demonstrating fT = 14.7 GHz operation of 500-nm-length devices. The dual-gated devices
are fabricated in a similar approach to Chapter 2, where the silicon wafer acts as the backgate and a high−κ dielectric separates the graphene channel from the metal top-gate.
5.2.1
Device structure and fabrication
Figure 5.1 shows the basic structure of a graphene field-effect transistors used here. Devices
have a ground-signal-ground (GSG) probe structure to support RF measurement. Fabri-
50
!"
#"
!"
!"
#"
$"
#"
!"
$"
!"
Figure 5.1: Graphene FET structure for RF measurements. (a) Optical microscope image
of the entire probed RF device structure. (b) SEM micrograph of the graphene transistor
with two gate fingers.
%&"'()*+,-,"&./"01(2312(,4"5)6"7*83)9":;3(<03<*,";:)',"<="
1+,",-8(,"*(<>,?"%&"?,@;3,"01(2312(,4"5>6"!.A":;3(<'()*+"<="
cation is similar to Chapter 2, where mechanically exfoliated graphene from Kish graphite
1+,"'()*+,-,"1()-0;01<("B;1+"1B<"')1,"C-?,(04"""
on a high-resistivity Si substrate (ρ = 20, 000 Ω−cm) with a 285-nm thermally grown
SiO2 layer is used. The substrate, though highly resistive, still functions as a back-gate.
Single-layer graphene pieces are identified optically and confirmed with Raman spectroscopy.
Source/drain electrodes are patterned onto the selected graphene pieces with electron-beam
lithography followed by a Cr/Au (3 nm/80 nm) deposition. A 30-nm HfO2 film is directly
grown with atomic layer deposition as the top-gate dielectric on the active device area,
followed by the patterning of a Cr/Au gate. The fabricated device has two fingers of
W/L = 2.5 µm/0.5 µm and the source/drain separation is 3 µm. The global back-gate
is used to modulate the carrier density of the resulting spacer regions outside the active
channel, while the top-gate defines the active device region.
5.2.2
DC characterization
DC measurements are carried out in ambient conditions. Figure 5.2(a) shows the measured I-V characteristics along with field-effect model from Chapter 2. The contact resistance is approximately 100 Ω, the low-field mobility approximately 105 cm2 /V sec, and
51
!"
#"
-0.5 V
-0.3 V
-0.1 V
Figure 5.2: Current-voltage characteristics of top-gated GFET device for RF. (a) Drain
current (Id ) as a function of source-to-drain voltage (Vsd ) at Vgs−top = −0.1 V, −0.3 V,
!"##$%&'()*&+,$-./+#+.&$#012.1-)3-4567-8$(0.$9"$!%":#+0%−0.5 V Both measured (solid curves) and simulated (dashed curves) results are shown. (b)
."##$%&-;<!"
#$=-+1-+-3"%.2)%-)3-1)"#.$'&)'8#+0%-()*&+,$-;<%"
Small-signal transconductance
(|gm |) as a function of drain-to-source voltage at the same
gate-to-source
voltages. /.*012$.%3.$*014$.%3.$*015$.%.>)&/&'#($
=-+&-<%"&
)'*+,-(.
?$+1"#$8-;1)*08-."#($1=-+%8-10?"*+&$8-;8+1/$8-."#($1=no = 5 × 1012 cm−2 . Because of this degraded mobility and trapped charge effects as demon#$1"*&1-+#$-1/)@%9-;A=-B?+**'10,%+*-&#+%1.)%8".&+%.$-;<)"
strated in Chapter 3, the device does not show significant velocity saturation. Figure 5.2(b)6
$=-+1-+-3"%.2)%-)3-8#+0%'&)'1)"#.$-()*&+,$-+&-&/$-1+?$-,+&$'
shows that the measured small-signal device transconductance. gm has a pronounced zero
&)'1)"#.$-()*&+,$19-at V
. The highest transconductances are observed in the unipolar regime away from
sd−kink
Vsd−kink , which can be achieved by proper choice of V0 and biasing. Therefore the device
is most likely to be operated in the high-transconductance, velocity-saturated region with
Vsd below Vsd−kink .
5.2.3
Device frequency response
S-parameter characterization of the device in the 50 MHz to 20 GHz range is carried out
with on-wafer probes and an Agilent N5230A PNA-L network analyzer. Bias-Ts are used
to apply the dc and RF signals through the same GSG probes. An open de-embedding
structure is measured and used to remove the effects of pad parasitic using a y-parameter
de-embedding procedure. The S-parameters of the GFET are measured at Vgs−back = −15
V, Vgs−top = −0.25 V, and Vsd = 1.5 V. Figure 5.3 shows the frequency response of the
52
Figure 5.3: Frequency response of top-gated GFET. Measured forward current gain of the
top-gated GFET before and after deembedding of pad parasitics.
!"#$%#&'()"#*+,&*#),-).,+/01.#2)3!456))7#1*%"#2)
-,"81"2)'%""#&.)019&),-).:#).,+/01.#2)3!45);#-,"#)
small-signal current gain h21 , giving a unity-gain frequency of 14.7 GHz. The measured
1&2)1<#")2##=;#229&0),-)+12)+1"1*9>'*6)
device fT is consistent with a measured gm of 550 µS and Cg of 5.95 fF. Because of the high
gds and poor contact resistance at this bias point, the power gain fmax < 1 GHz.
5.3
RF performance h-BN supported GFETs
RF measurements have generally been reported for top-gated device structures whose
current-voltage characteristics do not show strong current saturation due to relatively poor
gate-oxide interfaces or weak gate coupling [40, 100, 128]. As a result, device output conductance is high, power gain is limited, and the maximum oscillation frequency (fmax ) is
typically only one-tenth of fT . It is noteworthy that fmax is the more significant figureof-merit for analog applications as power gain determines the ultimate applicability of the
devices. Power gain has a slightly more complicated expression compared to fT :
fT
fmax = p
4Rg (1/ro + 2πgm )
(5.3)
as it also depends on the gate resistance (Rg ) and small-signal output resistance (ro ).
Contact resistance has a significant impact on fmax ; not included in the above equation for
!"#$%&'()''*!+,'-&."/&'01%$/1$%&!""#$%"&'()*$+,'"
,--./+0$+,12"13"+()"4$'567$+)8"9:;<"8)=,')!"#4%"&;>"
53
*,'0170$?("13"$"'1*?-)+)8"/+0.'+.0)!"
8#
6
Res. (:
30
Id (mA)
25
100
75
5
50
-2
20
4
0 2
Vgs (V)
Gain (dB)
&#
15
10
3
2
1
5
0
0
1
Vsd (V)
2
!"#$%&'2)''34'/56%6/1&%"01"/0)''@A $/"$"3.2'+,12"13"B/8
Figure 5.4: GFET device with h-BN for RF. 310"B
(a) Schematic
illustration of the locally back/7 301*"CB"+1"6D!EB",2"C!EB"/+)?/!"@2/)+F"
gated device. (b) IV characteristics of BN GFET
for RF. Id as a function of Vsd for Vsg
G)/,/+$2')",2"-,2)$0"+0$2/?10+"0)7,12"$/"$"3.2'+,12"13"
B7/!" in linear transport region as a function
from 0 V to −1.5 V in 0.5 V steps. Inset: Resistance
of Vgs .
GFET device with h-BN for RF. (a) Schematic illustration of
the locally back-gated device. (b) !"#$%&'&$()'*+,$+#-.#/0#
1234#.-'#526#7!"#$%&'%&%()*+,-*%-(%$."/'#0$%(-1%$."/'20$%
!"#
simplicity. In this section, by exploiting high-quality boron-nitride dielectrics, we realize
(1-3%4%.%5-%$6789$%.%:*%$489$%.%'5;<'8%!*';5=%>;':'5&*+;%:*%
improved fmax /fT ratios as high as 0.86 and fmax values as high as 34 GHz for a 600-nm?:*;&1%51&*'<-15%1;2:-*%&'%&%()*+,-*%-(%$."/2'0$8%
dependence of both fT and fmax and compare our results with small-signal models of our
device structures.
5.3.1
!$#
!" #"$%
length device, the highest value reported so far for GFETs. We further investigate the bias
!"#$%
(HD $2
30)K.
$28"!#
Device structure and fabrication
Hexagonal boron nitride has been previously demonsrated to be an outstanding gate dielectric for GFETs in Chapter 4, yielding interfaces nearly free of trapped charge and
maintaining high mobility and carrier velocities in the graphene channel. The GFETs char!"#$%&'>)''?"609-&@&<-&</&'A:'0B6CC90"#<6C'@6%6B&1&%0)'D6E <0$2/'12
acterized here are fabricated with a back gate as shown in Figure 5.4(a). A split gate
layout is employed, where tungsten metal gates are initially patterned into a 1-µm SiO2
layer using a Damascene-like process, followed by a chemical-mechanical polishing (CMP)
step to ensure a flat surface and expose the gate metal surface. h-BN (10 nm thick) is
mechanically transferred to form the gate dielectric, followed by the mechanical transfer
,'-&."/&'01%$/1$%&!""#$%"&'()*$+,'"
)"4$'567$+)8"9:;<"8)=,')!"#4%"&;>"
'1*?-)+)8"/+0.'+.0)!"
54
60
50
40
0 2
Vgs (V)
Gain (dB)
-2
20 dB/dec
30
20
10
0
1
Vsd (V)
U
h21
0.1
1
10
Frequency (GHz)
2
!"#$%&'7)''8"#59:%&;$&</='-&."/&'/56%6/1&%"01"/0)
6%6/1&%"01"/0)''@A $/"$"3.2'+,12"13"B/8
(HD $28"".2,-$+)0$-"?1I)0"7$,2"#J%"$/"$"3.2'+,12"13"
1"6D!EB",2"C!EB"/+)?/!"@2/)+F"
Figure 5.5: High-frequency
device characteristics. h21 and unilateral power gain (U ) as a
30)K.)2'L"$3+)0"8))*4)88,27M"L,)-8,27"!
$0"+0$2/?10+"0)7,12"$/"$"3.2'+,12"13"
" N"OO"9PQ"
function of frequency after
deembedding, yielding fT = 44 GHz
and fmax = 34 GHz.
$28"!#$% N"RO"9PQ!""
!"#$%&'()*(+,-./(0",(.,$1'1,2('"34,35.!"#$%&'"()*+(
,*-.)/01).(23401(5)-*(678()9()(:,*;<3*(3:(:10=,0*;>(
of the)?01(+00@A0++-*5B(>-0.+-*5("!"#$C(DD"(EFG()*+("!"
graphene channel similar to the process in Chapter 4. GFET fabrication ends with
%&'()$C(HD"(EFGI(
e-beam
patterning of !$#
source and drain contacts with approximately 50-nm gate-to-source
DC characterization
&' #:%
5.3.2
!" #"$%
and gate-to-drain spacings.
Figure 5.4(b) shows the DC current-voltage (IV) characteristic of a representative GFET
device with a effective width of approximately 38 µm and channel length of 0.6 µm. The
inset of Fig. 5.4(b) shows the accompanying source-drain resistance in the triode region at
Vsd = 10 mV, from which the contact resistance and low-field mobility can be extracted.
The total contact resistance (including both source and drain) is approximately 25 Ω, or
950 Ω − µm when normalized to contact width. The low-field mobility is 3, 300 cm2 /V
@&<-&</&'A:'0B6CC90"#<6C'@6%6B&1&%0)'D6E <0$2/'128.'+$2') $28"DFE 1.+?.+"0)/,/+$2')!
sec. The charge neutrality point (V0 ), the gate-to-source voltage at which the maximum
low-field triode resistance is achieved, is at 0.6 V. IV characteristics are plotted for gate
voltages (Vsg ) from 0 to -1.5V, demonstrating both saturating current characteristics for
the unipolar hole channel and the kink associated with the transition to the ambipolar holeelectron channel. Figure 5.6 gives the transconductance (gm ) and output resistance (ro ) as
Frequency
(GHz)
Frequency
(GHz)
Vsd (V)
Vsd (V)
!"#$%&'7)''8"#59:%&;$&</='-&."/&'/56%6/1&%"01"/0)
!"#$%&'7)''8"#59:%&;$&</='-&."/&'/56%6/1&%"01"/0)
(HD $28"".2,-$+)0$-"?1I)0"7$,2"#J%"$/"$"3.2'+,12"13"
(HD $28"".2,-$+)0$-"?1I)0"7$,2"#J%"$/"$"3.2'+,12"13"
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55
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<0$2/'128.'+$2')
$28"DFE
1.+?.+"0)/,/+$2')!
Figure 5.6: Bias-dependence of small-signal
parameters.
(a)$28"DFE
Transconductance
and (b)
$%!&'()*)+()+,)"-."&/!00'&%1+!0"*!2!/)3)2&4"5!6"
!"#$%&'$()&*#$&+,#$(,5#6"')*-)*,"+%.%*#$&+/,
output resistance plotted versus Vsd and Vsg .
a function of bias; both are strongly influenced by the kink behavior in the IV characteristic.
The peak gm of 10.5 mS and peak ro of 460 Ω occur at different bias points. This limits
transistor performance both in dc and high-frequency by limiting voltage gain (Av ≈ gm ro )
at dc and fT ,fmax at RF. The devices show no hysteresis and unchanged characteristics
after repeated measurements.
!()* #$%&'
!()* #$%&'
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!" #$%&'
!"
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" ",<$!;#$!
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!#"!#"
rs rs
rs ,rrds ,rd
12.5
ȍ ȍ
12.5
60
50
40
30
20
10
UI (dB)
I (dB)
GG
Figure 5.7: Bias dependence of high-frequency figures-of-merit. (a) fT and (b) fmax .
*#+*#+
*-+*-+
rg rg
Cgd
rd rd
Cgd
$%!&"'()(*'(*+(",-".%/.0-1(23(*+4"5/31(&0,-06(1%78"!"#$%!"#$%
DD
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!('")
!"#!"#
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60
50
40
30
20
10
measured
measured
model
model
!""!""
!##!
!"#$%&'6)''7",/'2&8&02&04&'19':"#:.9%&;$&04<'9"#$%&/.19.+&%"=)''!"#$!" ",<$!;#$!#$%8
!"#$%&'6)''7",/'2&8&02&04&'19':"#:.9%&;$&04<'9"#$%&/.19.+&%"=)''!"#$!
" ",<$!;#$!#$%8
!"#$%&'6)''7",/'2&8&02&04&'19':"#:.9%&;$&04<'9"#$%&/.19.+&%"=)''!"#$!" ",<$!;#$!
#$%8
g
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m
#"*,+S*,+
*,+
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*-+ *-+
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50
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60
measured
measured
5060
model
50
model
40 measured
3040
30model
20
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10
10
0 0
-10-10
0.10.11 10
1 100
10 100
!"" !
""
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12.5ȍȍ
40
gm
rs ,rrds ,rd 12.5
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30
##
gm
19 mS ro
rs98
,rdȍ
12.5
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20
C
17
fF
gd
ro
98 ȍ
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17 fF
!##
10
0
ro
98r ȍ rg 19 C
17 fF 3434fFfF
gd ȍ
ȍ19
CgsCgs
g
-10
Frequency (GHz)
0.1 1Frequency
10 100 (GHz)
rg
19 ȍ
Cgs
34 fF
Frequency (GHz)
!"#$%&'()''*+,--./"#0,-'+12&-"0#)''!"#$%&"''()*+,"'$-./*0"'-,1$2*32/*1$453$"$3-63-)-,1"1*0-$789(P&$13",)*)153):$!;#$
!"#$%&'()''*+,--./"#0,-'+12&-"0#)''!"#$%&"''()*+,"'$-./*0"'-,1$2*32/*1$453$"$3-63-)-,1"1*0-$789(P&$13",)*)153):$!;#$
6"3"&-1-3$0"'/-)$/)-<$*,$1=-$&5<-':$",<$345
&-")/3-<$%(6"3"&-1-3)$"'5,+$>*1=$1=-$3-)/'1)$54$1=-$&5<-'8$?,)-1@
A,*'"1-3"'$
6"3"&-1-3$0"'/-)$/)-<$*,$1=-$&5<-':$",<$345 &-")/3-<$%(6"3"&-1-3)$"'5,+$>*1=$1=-$3-)/'1)$54$1=-$&5<-'8$?,)-1@
A,*'"1-3"'$
!"#$%&'()''*+,--./"#0,-'+12&-"0#)''!"#$%&"''()*+,"'$-./*0"'-,1$2*32/*1$453$"$3-63-)-,1"1*0-$789(P&$13",)*)153):$!;#$
+"*,$54$;51=$&-")/3-<$",<$&5<-'-<$<-0*2-8$
+"*,$54$;51=$&-")/3-<$",<$&5<-'-<$<-0*2-8$
6"3"&-1-3$0"'/-)$/)-<$*,$1=-$&5<-':$",<$345 &-")/3-<$%(6"3"&-1-3)$"'5,+$>*1=$1=-$3-)/'1)$54$1=-$&5<-'8$?,)-1@ A,*'"1-3"'$
IUI (dB)
gm 19 mS
19 mS
!"#$%&"'
!"#$%&"'
!('")
!"#$%&"'
!('")
!('")
!"#!
!#" !
#"
!#"
rs rs
IUI (dB)
G
G
rG
g
CgdCgd
IUI (dB)
*#+
*#+ !"*#+
r rg
56
Cut-Off Frequency (GHz)
20
Cut-Off Frequency (GHz)
30
IUI (dB)
IUI (dB)
40
IUI (dB)
50
Cut-Off Frequency (GHz)
Figure 5.8: Small-signal and RF modeling. (a) Small-signal equivalent circuit for a rep%&!''()*+,!'"!,-"./"&0-1'*,+2"!"#$%&"''()*+,"'$-./*0"'-,1$
50
resentative
0.6-mm transistors; (b) parameter values250
used
250 in the model; and (c) measured
fT f
r
=
98
:
r
=
98
:
o
S-parameters
along with
results of the model.
Inset: Unilateral gain of both
Tmeasured
o the
2*32/*1$453$"$3-63-)-,1"70-$89:(&&$13",)*)153);$!<#$
40
250
40
200
f
200
f
r
=
460
:
and modeled device.
ro= 98 :
f
ro=o460 :
Tmax max
6"3"&-1-3$0"'/-)$/)-=$*,$1>-$&5=-';$",=$3$4"&-")/3-=$%(
30 30
200
r = 460 :
./0 f
150
+"*,$54$;51=$&-")/3-<$",<$&5<-'-<$<-0*2-8$
50
o
6"3"&-1-3)$"'5,+$?*1>$1>-$3-)/'1)$54$1>-$&5=-'9$@,)-1A$
5.3.3
Device
frequency response
20 20
150
max
./0
./0
150 100
100
B,*'"1-3"'$+"*,$54$<51>$&-")/3-=$",=$&5=-'-=$=-0*2-9$
10 10 1 3456789
1!#23456789
Device S-parameters
are measured to 40 GHz. Standard open-short de-embedding methods
!#2
100 50
50
0 1 3:;6789
10
03456789
1are
1!#23:;6789
!#2employed
!#2
[129]. In Figure 5.5, current-gain (h21 ) and unilateral power gain (U ) are plot50
-10
00
0 1 -10
3:;6789
!#2at
ted
the bias
point
of
peak
g
,
yielding
f
and
fmax of 44
GHz
and
34
1
10
100
100100
200200
300 300
400GHz,
500 respectively.
600
m
T
1
10
100
400
500 600
-10
0
Frequency
(GHz)
Channel
Length
(nm) (nm)
Frequency
(GHz)
Channel
Length
(Without
de-embedding
fT and f18="+"D,="10)''
GHz,
Figure 5.7
max are 24 GHz and
1
10
100
10017200
300respectively.)
400 500 600
!"#$%&'>)''?+8%1@&+&0=/'81//"A-&'B"=:'C
18="+"D,="10)''
!"#$%&'>)''?+8%1@&+&0=/'81//"A-&'B"=:'C
1 1
!"#$%&'E)''F&@"4&'/4,-"0#)'C3-<*21-<$=*+=(43-./-,2D$
!"#$%&'E)''F&@"4&'/4,-"0#)'C3-<*21-<$=*+=(43-./-,2D$
A$2"'2/'"1-<$435&$1=-$&5<-'$>*1=$6"3"&-1-3$0"'/-)$54$B*+8$
A$2"'2/'"1-<$435&$1=-$&5<-'$>*1=$6"3"&-1-3$0"'/-)$54$B*+8$
Frequency (GHz)
Channel Length (nm)
6-3453&",2-$"1$<*44-3-,1$2=",,-'$'-,+1=)8
6-3453&",2-$"1$<*44-3-,1$2=",,-'$'-,+1=)8
shows
fT and fmax as a function
of bias; the peak high-frequency
response closely matches
9;$!<")=-<$;'/-#$",<$>*1=$5/16/1$3-)*)1",2-$)-1$15$=*+=-)1$
9;$!<")=-<$;'/-#$",<$>*1=$5/16/1$3-)*)1",2-$)-1$15$=*+=-)1$
!"#$%&'>)''?+8%1@&+&0=/'81//"A-&'B"=:'C
18="+"D,="10)''
1
&-")/3-<$0"'/-$!3-<#8$
&-")/3-<$0"'/-$!3-<#8$
A$2"'2/'"1-<$435&$1=-$&5<-'$>*1=$6"3"&-1-3$0"'/-)$54$B*+8$
the peak transconductance of the device.
9;$!<")=-<$;'/-#$",<$>*1=$5/16/1$3-)*)1",2-$)-1$15$=*+=-)1$
&-")/3-<$0"'/-$!3-<#8$
!"#$%&'E)''F&@"4&'/4,-"0#)'C3-<*21-<$=*+=(43-./-,2D$
6-3453&",2-$"1$<*44-3-,1$2=",,-'$'-,+1=)8
The small-signal model of Figure 5.8(a) is used to model the high-frequency be-
havior of the GFETs. The measured S-parameters are shown in Figure 5.8(c), showing
good agreement with the results of the small signal model with the parameters given in
Figure 5.8(b). These small-signal values are in good agreement with values derived from
the IV characteristics. The gm here is the intrinsic value, exclusive of contact resistance, in
good agreement with previous chapters results of approximately 0.5 mS/µm.
The model derived from this representative 0.6-µm device can be used to further
understand device optimization and scaling. Figure 5.9(a) shows how the fmax performance
ro
98 rȍo
Cgd
98
ȍ
17
fF
Cgd
17 fF
rg
19 rȍg
Cgs
19
ȍ
34
fF
Cgs
34 fF
0
-10
0.1
0
-10
1 10 0.1
100 1
10 100
Frequency Frequency
(GHz)
(GHz)
!"#$%&'()''*+,--./"#0,-'+12&-"0#)''!"#$%&"''()*+,"'$-./*0"'-,1$2*32/*1$453$"$3-63-)-,1"1*0-$789(P&$13",)*)153):$!;#$
!"#$%&'()''*+,--./"#0,-'+12&-"0#)''!"#$%&"''()*+,"'$-./*0"'-,1$2*32/*1$453$"$3-63-)-,1"1*0-$789(P&$13",)*)153):$!;#$
57
6"3"&-1-3$0"'/-)$/)-<$*,$1=-$&5<-':$",<$345
&-")/3-<$%(6"3"&-1-3)$"'5,+$>*1=$1=-$3-)/'1)$54$1=-$&5<-'8$?,)-1@
A,*'"1-3"'$ A,*'"1-3"'$
6"3"&-1-3$0"'/-)$/)-<$*,$1=-$&5<-':$",<$345
&-")/3-<$%(6"3"&-1-3)$"'5,+$>*1=$1=-$3-)/'1)$54$1=-$&5<-'8$?,)-1@
+"*,$54$;51=$&-")/3-<$",<$&5<-'-<$<-0*2-8$
+"*,$54$;51=$&-")/3-<$",<$&5<-'-<$<-0*2-8$
40
30
30
ro= 98 : ro= 98 :
ro= 460 :ro= 460 :
20
10
1!#210
3456789
1!#23456789
0
0 1 3:;6789
1!#23:;6789
!#2
-10
20
-10
1
10
100
1
10
100
FrequencyFrequency
(GHz)
(GHz)
250
200
150
100
50
0
Cut-Off Frequency (GHz)
40
#"
IUI (dB)
IUI (dB)
50
Cut-Off Frequency (GHz)
!"
50
250
200
150
./0
fT
fT
fmax
fmax
./0
100
50
0
100 200 100
300 200
400 300
500 400
600 500 600
Channel Length
(nm)
Channel Length (nm)
!"#$%&'>)''?+8%1@&+&0=/'81//"A-&'B"=:'C
!"#$%&'>)''?+8%1@&+&0=/'81//"A-&'B"=:'C
1 18="+"D,="10)''
1 18="+"D,="10)''
!"#$%&'E)''F&@"4&'/4,-"0#)'C3-<*21-<$=*+=(43-./-,2D$
!"#$%&'E)''F&@"4&'/4,-"0#)'C3-<*21-<$=*+=(43-./-,2D$
A$2"'2/'"1-<$435&$1=-$&5<-'$>*1=$6"3"&-1-3$0"'/-)$54$B*+8$
A$2"'2/'"1-<$435&$1=-$&5<-'$>*1=$6"3"&-1-3$0"'/-)$54$B*+8$
6-3453&",2-$"1$<*44-3-,1$2=",,-'$'-,+1=)8
6-3453&",2-$"1$<*44-3-,1$2=",,-'$'-,+1=)8
9;$!<")=-<$;'/-#$",<$>*1=$5/16/1$3-)*)1",2-$)-1$15$=*+=-)1$
9;$!<")=-<$;'/-#$",<$>*1=$5/16/1$3-)*)1",2-$)-1$15$=*+=-)1$
Figure
5.9: Improvements possible with device optimization. (a) U calculated from the
&-")/3-<$0"'/-$!3-<#8$
&-")/3-<$0"'/-$!3-<#8$
model
with parameter values of Figure 5.8 (dashed blue) and with output resistance set
$%&'()*%*+,-"&(--.#/*"0.,1"2*).3*"(&4%.5!4(+6"7!8"!"!#
to highest measured value (red). (b) Predicted high-frequency performance at different
$%&$'&%()*#+,-.#(/)#.-*)&#01(/#2%,%.)(),#3%&')4#-+#516',)7
channel lengths using the RF model.
8,)+9:6;<=>5?.-*)&@#A*%4/)*#B&')C#%D*#01(/#-'(2'(#
could be improved to 58 GHz for this same channel length if the V0 of the device could be
,)414(%D$)#4)(#(-#/16/)4(#.)%4',)*#3%&')#A,)*CE#ABC#F,)*1$()*#
adjusted (through a secondary gate or channel doping) to align peak gm and ro . The model is
/16/G+,)H')D$I#2),+-,.%D$)#%(#*1J),)D(#$/%DD)&#&)D6(/4#
also used to estimate the performance at shorter channel lengths by scaling gate capacitance
'41D6#(/)#>5#.-*)&E#
while keeping other small-signal parameters constant as shown in Figure 5.9(b). fmax values
close to 250 GHz are possible at 100 nm channel length. Higher frequency performance will
require significant improvements in device parasitics, most notably the contact resistance.
5.4
Chapter Summary
In summary, we have fabricated and measured two types of GFETs at high frequencies.
The first RF GFET device, yields fT performance exceeding 14 GHz for a 500-nm-length
channel. The second type with h-BN dielectric has greatly improved performance and yields
fmax of 34 GHz. We have elucidated unique features in the current-voltage characteristics
of these devices and their effect on the RF performance. Especially, the ”kink” in the IV
characteristics is crucial to align the maximum transconductance and output resistance. A
small-signal model is developed that can closely match the measured RF data up to 40
58
GHz. Wider device structures and lower contact resistance will be necessary to utilize these
devices in simple RF circuits, such as low-noise amplifiers (LNAs).
59
Chapter 6
Conclusion
The recent discovery of graphene has created a large interest in using this material for electronic applications. Favorable properties of graphene such as its two-dimensional structure,
large current carrying capability, and high carrier velocities support this interest. While
the zero-bandgap of graphene restricts any digital electronic applications, analog applications that do not require low off currents show significant promise. In this thesis, the
current-voltage characteristics of graphene FETs have been experimentally investigated at
high-bias. The implications of the zero-bandgap on the IV characteristics are observed and
modeled. Other FET characteristics such as the effect of channel length scaling as well as
high-frequency performance are demonstrated.
6.1
Summary of contributions
In summary, GFETs with highly efficient gates are fabricated. The importance of large gate
coupling in the high-bias regime is demonstrated. The first high-bias IV-measurements of
graphene reveal a “kink” that is attributed to the zero-bandgap ambipolar channel. For
device applications, we find that the kink is undesirable as the transconductance becomes
zero at this point. The saturation velocity is investigated and a unique density dependence
is observed for the first time and interpreted with respect to the linear density-of-states in
graphene. [34]
60
Channel length scaling in GFETs is studied systematically for the first time down to
∼100-nm channel length. We find that trapped charges surrounding the graphene channel
become increasingly important with decreasing length and can mask the intrinsic graphene
characteristics. A dual-channel pulsed measurement method is employed to mitigate the
effects of such extrinsic factor, resulting in saturating current characteristics down to the
shortest channel length devices measured. The small-signal parameters such as transconductance and output conductance remain constant with scaling; a favorable result for GFET
applications. [98]
Alternative approaches for device fabrication have also been investigated. Specifically, integrating graphene with a gate dielectric in an FET structure, a fundamental
problem in graphene research, has been demonstrated in two possible ways. A polymer
functionalization layer has been developed to assist high−κ ALD growth. While the process results in very high gate coupling, the trapped charges between the graphene/dielectric
interface degrades device performance significantly. A superior method is developed, where
hexagonal boron nitride was used as the dielectric. These devices exhibit improved low-field
transport properties, such as high mobility and reduced hysteresis, and high-field transport
with current saturation without the need for pulsed measurements. [120]
The high-frequency performance of GFETs fabricated with the two different methods
above is studied. The RF measurements on the top-gates devices are the first in the field and
demonstrate the possibility of graphene FETs for analog/RF applications. While the initial
measurements yield a fT ≈ 15 GHz [35], with improved devices with h-BN dielectric these
increase to 44 GHz at 600-nm channel length. The bias dependence of the high-frequency
characteristics and a RF model were also among the unique contributions of this work [130].
6.2
Future work
Significant progress has been made in both understanding GFET operation and increasing
GFET performance. There are, however, numerous remaining questions that will determine
whether graphene transistor will become a commercially viable technology. Certainly, tran-
61
sistor performance will be an impact factor. Equally important will be the development of
techniques for efficient manufacturing.
To make GFETs viable for RF applications, a number of problems that were pointed
out throughout this work have to be resolved. Contact resistance in these devices remains
high compared to the channel resistance and has a clear impact on transistor operation. The
gate dielectric is another issue that requires intensive research. h-BN is a good candidate;
however, a wafer scale process will be required to make it a potential solution. For deeplyscaled channel lengths, higher dielectric constant materials will be required to approach the
gate efficiency of state-of-the-art silicon transistors. Controlling the channel doping will
also be necessary to ensure unipolar device operation.
In terms of GFET operation, many questions remain unanswered. It is unclear at
this point what the limiting phonon energy is for velocity saturation. A better understanding of this quantity could enable enhances channel velocities. It remains unknown how the
device will behave once channel lengths on the order of the mean-free-path are approached.
Theoretical models predict that band-to-band tunneling could become significant at channel lengths less than 100 nm [131]. How this will effect device performance is yet to be
determined.
The small quantum capacitance will most certainly affect attainable effective gate
capacitance. Especially in deeply scaled devices that require high gate coupling to minimize short channel effects, the small quantum capacitance might pose another limit on
minimum channel length. Additionally, the density-dependent quantum capacitance is a
source of nonlinearity, an undesirable feature for analog amplifier applications. The density
dependence of the saturation velocity will also be an additional source of nonlinearity.
Further evaluation of other transistor characteristics is necessary to determine the
usefulness of GFETs for analog/RF applications. The noise performance remains unknown.
A careful investigation of the noise figure, which might be related to the unique energy
dispersion of graphene, needs to be performed. The transconductance per unit current will
also require significant improvements for analog applications.
62
Finally, the true potential of graphene transistors could become possible in novel
applications such as flexible electronics that would benefit from both the electrical and
mechanical properties. An ideal GFET structure could be envisioned as a self-aligned
device with deeply scaled h-BN dielectric on a wafer-scale flexible substrate.
63
Bibliography
[1] P. Avouris, Z. Chen, and V. Perebeinos, “Carbon-based electronics,” Nature Nanotechnology, vol. 2, no. 10, pp. 605–615, Oct. 2007.
[2] K. S. Novoselov, A. K. Geim, S. V. Morozov, D. Jiang, Y. Zhang, S. V. Dubonos, I. V.
Grigorieva, and A. A. Firsov, “Electric field effect in atomically thin carbon films,”
Science (New York, NY), vol. 306, no. 5696, pp. 666–669, Oct. 2004.
[3] K. S. Novoselov, D. Jiang, F. Schedin, T. J. Booth, V. V. Khotkevich, S. V. Morozov,
and A. K. Geim, “Two-dimensional atomic crystals,” Proceedings of the National
Academy of Sciences of the United States of America, vol. 102, no. 30, pp. 10 451–
10 453, Jul. 2005.
[4] W. Sommer, “Liquid Helium as a Barrier to Electrons,” Physical Review Letters,
vol. 12, no. 11, pp. 271–273, Mar. 1964.
[5] H. Kroto, J. Heath, S. O’Brien, R. Curl, and R. Smalley, “C60: Buckminsterfullerene,”
Nature, vol. 318, pp. 162–163, 1985.
[6] K. S. Novoselov, A. K. Geim, S. V. Morozov, D. Jiang, M. I. Katsnelson, I. V.
Grigorieva, S. V. Dubonos, and A. A. Firsov, “Two-dimensional gas of massless Dirac
fermions in graphene,” Nature, vol. 438, no. 7065, pp. 197–200, Nov. 2005.
[7] Y. Zhang, Y.-W. Tan, H. L. Stormer, and P. Kim, “Experimental observation of the
quantum Hall effect and Berry’s phase in graphene.” Nature, vol. 438, no. 7065, pp.
201–204, Nov. 2005.
[8] K. S. Novoselov, Z. Jiang, Y. Zhang, S. V. Morozov, H. L. Stormer, U. Zeitler, J. C.
Maan, G. S. Boebinger, P. Kim, and A. K. Geim, “Room-temperature quantum Hall
effect in graphene,” Science (New York, NY), vol. 315, no. 5817, p. 1379, Mar. 2007.
[9] A. F. Young and P. Kim, “Quantum interference and Klein tunnelling in graphene
heterojunctions,” Nature Physics, vol. 5, no. 3, pp. 222–226, Mar. 2009.
[10] N. Stander, B. Huard, and D. Goldhaber-Gordon, “Evidence for Klein Tunneling in
Graphene p-n Junctions,” Physical Review Letters, vol. 102, no. 2, p. 26807, Jan.
2009.
[11] K. I. Bolotin, F. Ghahari, M. D. Shulman, H. L. Stormer, and P. Kim, “Observation
of the fractional quantum Hall effect in graphene,” Nature, vol. 462, no. 7270, pp.
196–199, Nov. 2009.
64
[12] X. Du, I. Skachko, F. Duerr, A. Luican, and E. Y. Andrei, “Fractional quantum Hall
effect and insulating phase of Dirac electrons in graphene,” Nature, vol. 462, no. 7270,
pp. 192–195, Nov. 2009.
[13] C. R. Dean, A. F. Young, P. Cadden-Zimansky, L. Wang, H. Ren, K. Watanabe,
T. Taniguchi, P. Kim, J. Hone, and K. L. Shepard, “Multicomponent fractional quantum Hall effect in graphene,” Nature Physics, vol. 7, pp. 1–4, May 2011.
[14] E. Stolyarova, K. T. Rim, S. Ryu, J. Maultzsch, P. Kim, L. E. Brus, T. F. Heinz,
M. S. Hybertsen, and G. W. Flynn, “High-resolution scanning tunneling microscopy
imaging of mesoscopic graphene sheets on an insulating surface.” Proceedings of the
National Academy of Sciences of the United States of America, vol. 104, no. 22, pp.
9209–9212, May 2007.
[15] M. Ishigami, J. H. Chen, W. G. Cullen, M. S. Fuhrer, and E. D. Williams, “Atomic
structure of graphene on SiO2.” Nano Letters, vol. 7, no. 6, pp. 1643–1648, Jun. 2007.
[16] Y. Zhang, V. W. Brar, F. Wang, C. Girit, Y. Yayon, M. Panlasigui, A. Zettl, and M. F.
Crommie, “Giant phonon-induced conductance in scanning tunnelling spectroscopy
of gate-tunable graphene,” Nature Physics, vol. 4, no. 8, pp. 627–630, Jul. 2008.
[17] R. R. Nair, P. Blake, A. N. Grigorenko, K. S. Novoselov, T. J. Booth, T. Stauber,
N. M. R. Peres, and A. K. Geim, “Fine Structure Constant Defines Visual Transparency of Graphene,” Science (New York, NY), vol. 320, no. 5881, pp. 1308–1308,
Jun. 2008.
[18] C. Casiraghi, A. Hartschuh, E. Lidorikis, H. Qian, H. Harutyunyan, T. Gokus, K. S.
Novoselov, and A. C. Ferrari, “Rayleigh Imaging of Graphene and Graphene Layers,”
Nano Letters, vol. 7, no. 9, pp. 2711–2717, Sep. 2007.
[19] K. F. Mak, M. Y. Sfeir, J. A. Misewich, and T. F. Heinz, “The evolution of electronic
structure in few-layer graphene revealed by optical spectroscopy.” Proceedings of the
National Academy of Sciences, vol. 107, no. 34, pp. 14 999–15 004, Aug. 2010.
[20] A. Ferrari, J. Meyer, V. Scardaci, and C. Casiraghi, “Raman Spectrum of Graphene
and Graphene Layers,” Physical Review Letters, 2006.
[21] A. Das et al., “Monitoring dopants by Raman scattering in an electrochemically topgated graphene transistor,” Nature Nanotechnology, vol. 3, no. 4, pp. 210–215, Apr.
2008.
[22] K. S. Novoselov, E. McCann, S. V. Morozov, V. I. Fal’ko, M. I. Katsnelson, U. Zeitler,
D. Jiang, F. Schedin, and A. K. Geim, “Unconventional quantum Hall effect and
Berry’s phase of 2 in bilayer graphene,” Nature Physics, vol. 2, no. 3, pp. 177–180,
Feb. 2006.
[23] T. Ohta, A. Bostwick, T. Seyller, K. Horn, and E. Rotenberg, “Controlling the electronic structure of bilayer graphene.” Science (New York, NY), vol. 313, no. 5789, pp.
951–954, Aug. 2006.
[24] E. Castro, K. Novoselov, S. Morozov, N. Peres, J. dos Santos, J. Nilsson, F. Guinea,
A. Geim, and A. Neto, “Biased Bilayer Graphene: Semiconductor with a Gap Tunable
by the Electric Field Effect,” Physical Review Letters, vol. 99, no. 21, Nov. 2007.
65
[25] J. B. Oostinga, H. B. Heersche, X. Liu, A. F. Morpurgo, and L. M. K. Vandersypen,
“Gate-induced insulating state in bilayer graphene devices,” Nature Materials, vol. 7,
no. 2, pp. 151–157, Dec. 2007.
[26] Y. Zhang, T.-T. Tang, C. Girit, Z. Hao, M. C. Martin, A. Zettl, M. F. Crommie,
Y. R. Shen, and F. Wang, “Direct observation of a widely tunable bandgap in bilayer
graphene,” Nature, vol. 459, no. 7, pp. 820–823, Jun. 2009.
[27] T. J. Booth et al., “Macroscopic graphene membranes and their extraordinary stiffness,” Nano Letters, vol. 8, no. 8, pp. 2442–2446, Aug. 2008.
[28] J. S. Bunch, S. S. Verbridge, J. S. Alden, A. M. Van Der Zande, J. M. Parpia,
H. G. Craighead, and P. L. Mceuen, “Impermeable atomic membranes from graphene
sheets,” Nano Letters, vol. 8, no. 8, pp. 2458–2462, Aug. 2008.
[29] J. S. Bunch, A. M. van der Zande, S. S. Verbridge, I. W. Frank, D. M. Tanenbaum,
J. M. Parpia, H. G. Craighead, and P. L. McEuen, “Electromechanical Resonators
from Graphene Sheets,” Science (New York, NY), vol. 315, no. 5811, pp. 490–493,
Jan. 2007.
[30] C. Chen, S. Rosenblatt, K. I. Bolotin, W. Kalb, P. Kim, I. Kymissis, H. L. Stormer,
T. F. Heinz, and J. Hone, “Performance of monolayer graphene nanomechanical resonators with electrical readout,” Nature Nanotechnology, vol. 4, no. 12, pp. 861–867,
Sep. 2009.
[31] F. Schedin, A. K. Geim, S. V. Morozov, E. W. Hill, P. Blake, M. I. Katsnelson,
and K. S. Novoselov, “Detection of individual gas molecules adsorbed on graphene.”
Nature Materials, vol. 6, no. 9, pp. 652–655, Sep. 2007.
[32] Y. Dan, Y. Lu, N. J. Kybert, Z. Luo, and A. T. C. Johnson, “Intrinsic response of
graphene vapor sensors,” Nano Letters, vol. 9, no. 4, pp. 1472–1475, Apr. 2009.
[33] Y. Ohno, K. Maehashi, Y. Yamashiro, and K. Matsumoto, “Electrolyte-gated
graphene field-effect transistors for detecting pH and protein adsorption.” Nano Letters, vol. 9, no. 9, pp. 3318–3322, Sep. 2009.
[34] I. Meric, M. Y. Han, A. F. Young, B. Ozyilmaz, P. Kim, and K. L. Shepard, “Current saturation in zero-bandgap, top-gated graphene field-effect transistors,” Nature
Nanotechnology, vol. 3, no. 11, pp. 654–659, Nov. 2008.
[35] I. Meric, N. Baklitskaya, P. Kim, and K. Shepard, “RF performance of top-gated,
zero-bandgap graphene fiel-effect transistors,” Electron Devices Meeting, 2008. IEDM
2008. IEEE International, pp. 1–4, Nov. 2008.
[36] Y.-M. Lin, K. A. Jenkins, A. Valdes-Garcia, J. P. Small, D. B. Farmer, and P. Avouris,
“Operation of graphene transistors at gigahertz frequencies,” Nano Letters, vol. 9,
no. 1, pp. 422–426, 2009.
[37] J. Chauhan and J. Guo, “High-field transport and velocity saturation in graphene,”
Applied Physics Letters, vol. 95, no. 2, p. 023120, 2009.
66
[38] S. A. Thiele, J. A. Schaefer, and F. Schwierz, “Modeling of graphene metal-oxidesemiconductor field-effect transistors with gapless large-area graphene channels,”
Journal of Applied Physics, vol. 107, p. 094505, May 2010.
[39] V. Perebeinos and P. Avouris, “Inelastic scattering and current saturation in
graphene,” Physical Review B, vol. 81, p. 195442, Apr. 2010, (c) 2010: The American
Physical Society.
[40] Y.-M. Lin, C. Dimitrakopoulos, K. A. Jenkins, D. B. Farmer, H.-Y. Chiu, A. Grill,
and P. Avouris, “100-GHz transistors from wafer-scale epitaxial graphene,” Science
(New York, NY), vol. 327, no. 5966, p. 662, Feb. 2010.
[41] L. Liao, Y.-c. Lin, M. Bao, R. Cheng, J. Bai, Y. Liu, Y. Qu, K. L. Wang, Y. Huang,
and X. Duan, “High-speed graphene transistors with a self-aligned nanowire gate,”
Nature, vol. 467, no. 7313, pp. 305–308, Sep. 2010.
[42] A. K. Geim and K. S. Novoselov, “The rise of graphene,” Nature Materials, vol. 6,
no. 3, pp. 183–191, Mar. 2007.
[43] A. K. Geim, “Graphene: status and prospects,” Science (New York, NY), vol. 324,
no. 5934, pp. 1530–1534, Jun. 2009.
[44] A. H. Castro Neto, F. Guinea, N. M. R. Peres, K. S. Novoselov, and A. K. Geim,
“The electronic properties of graphene,” Reviews of Modern Physics, vol. 81, p. 109,
2009.
[45] F. Bonaccorso, Z. Sun, T. Hasan, and A. C. Ferrari, “Graphene photonics and optoelectronics,” Nature Photonics, vol. 4, p. 611, Aug. 2010.
[46] A. Javey, H. Kim, M. Brink, Q. Wang, A. Ural, J. Guo, P. Mcintyre, P. Mceuen,
M. Lundstrom, and H. Dai, “High-kappa dielectrics for advanced carbon-nanotube
transistors and logic gates,” Nature Materials, vol. 1, no. 4, pp. 241–246, Dec. 2002.
[47] A. Javey, J. Guo, D. B. Farmer, Q. Wang, E. Yenilmez, R. G. Gordon, M. Lundstrom,
and H. Dai, “Self-Aligned Ballistic Molecular Transistors and Electrically Parallel
Nanotube Arrays,” Nano Letters, vol. 4, p. 1319, Jul. 2004.
[48] S. J. Kang, C. Kocabas, T. Ozel, M. Shim, N. Pimparkar, M. A. Alam, S. V. Rotkin,
and J. A. Rogers, “High-performance electronics using dense, perfectly aligned arrays
of single-walled carbon nanotubes,” Nature Nanotechnology, vol. 2, no. 4, pp. 230–236,
Apr. 2007.
[49] D. Akinwande, G. Close, and H.-S. Wong, “Analysis of the Frequency Response of
Carbon Nanotube Transistors,” Nanotechnology, IEEE Transactions on, vol. 5, no. 5,
pp. 599–605, 2006.
[50] Y. Tsividis and C. McAndrew, Operation and modeling of the MOS transistor, ser.
The Oxford Series in Electrical and Computer Engineering. Oxford University Press,
2010.
[51] Z. Chen, D. Farmer, S. Xu, R. Gordon, P. Avouris, and J. Appenzeller, “Externally
Assembled Gate-All-Around Carbon Nanotube Field-Effect Transistor,” Electron Device Letters, IEEE, vol. 29, no. 2, pp. 183–185, Feb. 2008.
67
[52] B. Doyle, B. Boyanov, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios, and R. Chau, “Tri-Gate fully-depleted CMOS transistors: fabrication,
design and layout,” VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on, pp. 133–134, 2003.
[53] C. Berger, Z. Song, T. Li, X. Li, A. Ogbazghi, R. Feng, Z. Dai, A. Marchenkov,
E. Conrad, and W. De Heer, “Ultrathin epitaxial graphite: 2D electron gas properties
and a route toward graphene-based nanoelectronics,” J. Phys. Chem. B, vol. 108,
no. 52, pp. 19 912–19 916, 2004.
[54] C. Berger et al., “Electronic confinement and coherence in patterned epitaxial
graphene.” Science (New York, NY), vol. 312, no. 5777, pp. 1191–1196, May 2006.
[55] K. S. Kim, Y. Zhao, H. Jang, S. Y. Lee, J. M. Kim, K. S. Kim, J.-H. Ahn, P. Kim, J.-Y.
Choi, and B. H. Hong, “Large-scale pattern growth of graphene films for stretchable
transparent electrodes.” Nature, vol. 457, no. 7230, pp. 706–710, Feb. 2009.
[56] X. Li et al., “Large-area synthesis of high-quality and uniform graphene films on
copper foils,” Science (New York, NY), vol. 324, no. 5932, pp. 1312–1314, Jun. 2009.
[57] X. Li, Y. Zhu, W. Cai, M. Borysiak, B. Han, D. Chen, R. D. Piner, L. Colombo, and
R. S. Ruoff, “Transfer of large-area graphene films for high-performance transparent
conductive electrodes.” Nano Letters, vol. 9, no. 12, pp. 4359–4363, Dec. 2009.
[58] S. Bae et al., “Roll-to-roll production of 30-inch graphene films for transparent electrodes.” Nature Nanotechnology, vol. 5, no. 8, pp. 574–578, Aug. 2010.
[59] P. R. Wallace, “The Band Theory of Graphite,” Physical Review, vol. 71, no. 9, pp.
622–634, May 1947.
[60] R. Saito, G. Dresselhaus, and M. Dresselhaus, Physical properties of carbon nanotubes,
2nd ed. Imperial College Press, 1998.
[61] S. Ilani, L. A. K. Donev, M. Kindermann, and P. L. McEuen, “Measurement of the
quantum capacitance of interacting electrons in carbon nanotubes,” Nature Physics,
vol. 2, p. 687, Oct. 2006.
[62] J. Xia, F. Chen, J. Li, and N. Tao, “Measurement of the quantum capacitance of
graphene,” Nature Nanotechnology, vol. 4, no. 8, pp. 505–509, Jul. 2009.
[63] M. Y. Han, B. Ozyilmaz, Y. Zhang, and P. Kim, “Energy band-gap engineering of
graphene nanoribbons,” Physical Review Letters, vol. 98, no. 20, p. 206805, May 2007.
[64] Z. Chen, Y.-M. Lin, M. J. Rooks, and P. Avouris, “Graphene nano-ribbon electronics,”
Physica E, vol. 40, no. 2, pp. 228–232, Dec. 2007.
[65] Q. Yan, B. Huang, J. Yu, F. Zheng, J. Zang, J. Wu, B.-L. Gu, F. Liu, and W. Duan,
“Intrinsic current-voltage characteristics of graphene nanoribbon transistors and effect
of edge doping,” Nano Letters, vol. 7, no. 6, pp. 1469–1473, Jun. 2007.
[66] G. Liang, N. Neophytou, D. Nikonov, and M. Lundstrom, “Performance Projections
for Ballistic Graphene Nanoribbon Field-Effect Transistors,” Electron Devices, IEEE
Transactions on, vol. 54, no. 4, pp. 677–682, 2007.
68
[67] L. Liao, J. Bai, Y. Qu, Y.-c. Lin, Y. Li, Y. Huang, and X. Duan, “High-kappa oxide
nanoribbons as gate dielectrics for high mobility top-gated graphene transistors,”
Proceedings of the National Academy of Sciences, vol. 107, no. 15, pp. 6711–6715,
Apr. 2010.
[68] X. Li, X. Wang, L. Zhang, S. Lee, and H. Dai, “Chemically Derived, Ultrasmooth
Graphene Nanoribbon Semiconductors,” Science (New York, NY), vol. 319, no. 5867,
pp. 1229–1232, Feb. 2008.
[69] X. Wang, Y. Ouyang, X. Li, H. Wang, J. Guo, and H. Dai, “Room-Temperature AllSemiconducting Sub-10-nm Graphene Nanoribbon Field-Effect Transistors,” Physical
Review Letters, vol. 100, p. 206803, May 2008.
[70] S. Fratini and F. Guinea, “Substrate-limited electron dynamics in graphene,” Physical
Review B, vol. 77, no. 1, p. 195415, May 2008.
[71] J.-H. Chen, C. Jang, S. Xiao, M. Ishigami, and M. S. Fuhrer, “Intrinsic and extrinsic
performance limits of graphene devices on SiO2,” Nature Nanotechnology, vol. 3, no. 4,
pp. 206–209, Apr. 2008.
[72] S. Adam, E. H. Hwang, V. M. Galitski, and S. D. Sarma, “A self-consistent theory for
graphene transport,” Proceedings of the National Academy of Sciences of the United
States of America, vol. 104, no. 47, pp. 18 392–18 397, Nov. 2007.
[73] J. Martin, N. Akerman, G. Ulbricht, T. Lohmann, J. H. Smet, K. von Klitzing, and
A. Yacoby, “Observation of electron-hole puddles in graphene using a scanning singleelectron transistor,” Nature Physics, vol. 4, no. 2, pp. 144–148, Feb. 2008.
[74] J.-H. Chen, C. Jang, S. Adam, M. S. Fuhrer, E. D. Williams, and M. Ishigami,
“Charged-impurity scattering in graphene,” Nature Physics, vol. 4, p. 377, May 2008.
[75] Y. Zhang, V. W. Brar, C. Girit, A. Zettl, and M. F. Crommie, “Origin of spatial
charge inhomogeneity in graphene,” Nature Physics, vol. 5, p. 722, Oct. 2009.
[76] K. I. Bolotin, K. J. Sikes, J. Hone, H. L. Stormer, and P. Kim, “TemperatureDependent Transport in Suspended Graphene,” Physical Review Letters, vol. 101,
p. 096802, Aug. 2008.
[77] K. I. Bolotin, K. J. Sikes, Z. Jiang, M. Klima, G. Fudenberg, J. Hone, P. Kim,
and H. L. Stormer, “Ultrahigh electron mobility in suspended graphene,” Solid State
Communications, vol. 146, p. 351, Jun. 2008.
[78] X. Du, I. Skachko, A. Barker, and E. Y. Andrei, “Approaching ballistic transport in
suspended graphene,” Nature Nanotechnology, vol. 3, no. 8, pp. 491–495, Aug. 2008.
[79] A. Khakifirooz and D. Antoniadis, “Transistor Performance Scaling: The Role of
Virtual Source Velocity and Its Mobility Dependence,” Electron Devices Meeting,
2006. IEDM ’06. International, pp. 1–4, 2006.
[80] F. Schwierz and J. Liou, “RF transistors: Recent developments and roadmap toward
terahertz applications,” Solid State Electronics, vol. 51, p. 1079, Aug. 2007.
69
[81] F. Xia, V. Perebeinos, Y.-M. Lin, Y. Wu, and P. Avouris, “The origins and limits of
metal-graphene junction resistance,” Nature Nanotechnology, vol. 6, no. 3, pp. 179–
184, Mar. 2011.
[82] C. Lee, X. Wei, J. W. Kysar, and J. Hone, “Measurement of the elastic properties
and intrinsic strength of monolayer graphene,” Science (New York, NY), vol. 321, no.
5887, pp. 385–388, Jul. 2008.
[83] J. H. Seol et al., “Two-dimensional phonon transport in supported graphene,” Science
(New York, NY), vol. 328, no. 5975, pp. 213–216, Apr. 2010.
[84] L. Liu, S. Ryu, M. R. Tomasik, E. Stolyarova, N. Jung, M. S. Hybertsen, M. L.
Steigerwald, L. E. Brus, and G. W. Flynn, “Graphene oxidation: thickness-dependent
etching and strong chemical doping,” Nano Letters, vol. 8, no. 7, pp. 1965–1970, Jul.
2008.
[85] P. Blake, E. W. Hill, A. H. Castro Neto, K. S. Novoselov, D. Jiang, R. Yang, T. J.
Booth, and A. K. Geim, “Making graphene visible,” Applied Physics Letters, vol. 91,
no. 6, p. 3124, Aug. 2007.
[86] M. Lemme, T. Echtermeyer, M. Baus, and H. Kurz, “A Graphene Field-Effect Device,” Electron Device Letters, IEEE, vol. 28, no. 4, pp. 282–284, 2007.
[87] B. Huard, J. A. Sulpizio, N. Stander, K. Todd, B. Yang, and D. Goldhaber-Gordon,
“Transport Measurements Across a Tunable Potential Barrier in Graphene,” Physical
Review Letters, vol. 98, p. 236803, Jun. 2007.
[88] J. R. Williams, L. DiCarlo, and C. M. Marcus, “Quantum Hall Effect in a GateControlled p-n Junction of Graphene,” Science (New York, NY), vol. 317, no. 5, pp.
638–, Aug. 2007.
[89] B. Ozyilmaz, P. Jarillo-Herrero, D. Efetov, and P. Kim, “Electronic transport in
locally gated graphene nanoconstrictions,” Applied Physics Letters, vol. 91, no. 1, p.
2107, Nov. 2007.
[90] Y.-F. Chen and M. S. Fuhrer, “Electric-Field-Dependent Charge-Carrier Velocity in
Semiconducting Carbon Nanotubes,” Physical Review Letters, vol. 95, p. 236803, Nov.
2005.
[91] P. Richman, MOS field-effect transistors and integrated circuits.
Wiley, 1973.
[92] Z. Yao, C. Kane, and C. Dekker, “High-field electrical transport in single-wall carbon
nanotubes,” Physical Review Letters, vol. 84, no. 13, pp. 2941–2944, Mar. 2000.
[93] J.-Y. Park, S. Rosenblatt, Y. Yaish, S. Braig, T. Arias, P. Brouwer, and P. McEuen,
“Electron Phonon Scattering in Metallic Single-Walled Carbon Nanotubes,” Nano
Letters, vol. 4, no. 3, pp. 517–520, 2004.
[94] J. Brews, “A charge-sheet model of the MOSFET,” Solid State Electronics, vol. 21,
no. 2, pp. 345–355, Feb. 1978.
[95] C. Canali, G. Majni, R. Minder, and G. Ottaviani, “Electron and hole drift velocity
measurements in silicon and their empirical relation to electric field and temperature,”
Electron Devices, IEEE Transactions on, vol. 22, no. 11, pp. 1045–1047, 1975.
70
[96] M. Lundstrom and Z. Ren, “Essential physics of carrier transport in nanoscale MOSFETs,” Electron Devices, IEEE Transactions on, vol. 49, no. 1, pp. 133–141, 2002.
[97] M. V. Fischetti, D. A. Neumayer, and E. A. Cartier, “Effective electron mobility in
Si inversion layers in metal-oxide-semiconductor systems with a high- insulator: The
role of remote phonon scattering,” Journal of Applied Physics, vol. 90, p. 4587, Nov.
2001, (c) 2001: American Institute of Physics.
[98] I. Meric, C. R. Dean, A. F. Young, N. Baklitskaya, N. J. Tremblay, C. Nuckolls,
P. Kim, and K. L. Shepard, “Channel length scaling in graphene field-effect transistors
studied with pulsed current-voltage measurements,” Nano Letters, vol. 11, no. 3, pp.
1093–1097, Mar. 2011.
[99] A. Barreiro, M. Lazzeri, J. Moser, F. Mauri, and A. Bachtold, “Transport Properties
of Graphene in the High-Current Limit,” Physical Review Letters, vol. 103, p. 76601,
Aug. 2009.
[100] J. Moon et al., “Epitaxial-Graphene RF Field-Effect Transistors on Si-Face 6H-SiC
Substrates,” Electron Device Letters, IEEE, vol. 30, no. 6, pp. 650–652, 2009.
[101] M.-H. Bae, Z.-Y. Ong, D. Estrada, and E. Pop, “Imaging, Simulation, and Electrostatic Control of Power Dissipation in Graphene Devices,” Nano Letters, vol. 10, p.
4787, Nov. 2010.
[102] M. Freitag, H.-Y. Chiu, M. Steiner, V. Perebeinos, and P. Avouris, “Thermal infrared
emission from biased graphene,” Nature Nanotechnology, vol. 5, p. 497, Jun. 2010, (c)
2010: Nature.
[103] A. M. DaSilva, K. Zou, J. K. Jain, and J. Zhu, “Mechanism for Current Saturation
and Energy Dissipation in Graphene Transistors,” Physical Review Letters, vol. 104,
p. 236601, Jun. 2010, (c) 2010: The American Physical Society.
[104] V. E. Dorgan, M.-H. Bae, and E. Pop, “Mobility and saturation velocity in graphene
on SiO2,” Applied Physics Letters, vol. 97, p. 082112, Aug. 2010.
[105] B. W. Scott and J.-P. Leburton, “High-field Carrier Velocity and Current Saturation
in Graphene Field-Effect Transistors,” arXiv, vol. cond-mat.mes-hall, Jul. 2010.
[106] F. Schwierz, “Graphene transistors,” Nature Nanotechnology, vol. 5, no. 7, pp. 487–
496, Jul. 2010.
[107] S. Kim, J. Nah, I. Jo, D. Shahrjerdi, L. Colombo, Z. Yao, E. Tutuc, and S. K. Banerjee,
“Realization of a high mobility dual-gated graphene field-effect transistor with Al2O3
dielectric,” Applied Physics Letters, vol. 94, p. 062107, Feb. 2009, (c) 2009: American
Institute of Physics.
[108] D. B. Farmer, H.-Y. Chiu, Y.-M. Lin, K. A. Jenkins, F. Xia, and P. Avouris, “Utilization of a buffered dielectric to achieve high field-effect carrier mobility in graphene
transistors,” Nano Letters, vol. 9, no. 12, pp. 4474–4478, Dec. 2009.
[109] S. Jin, J. Yu, C. Lee, J. Kim, B.-G. Park, and J. Lee, “Pentacene OTFTs with PVA
gate insulators on a flexible substrate,” Journal of the Korean Physical Society, vol. 44,
no. 1, pp. 181–184, 2004.
71
[110] G. Giovannetti, P. A. Khomyakov, G. Brocks, V. M. Karpan, J. van den Brink, and
P. J. Kelly, “Doping Graphene with Metal Contacts,” Physical Review Letters, vol.
101, p. 26803, Jul. 2008.
[111] K. Nagashio, T. Nishimura, K. Kita, and A. Toriumi, “Contact resistivity and current
flow path at metal/graphene contact,” Applied Physics Letters, vol. 97, p. 3514, Sep.
2010, (c) 2010: American Institute of Physics.
[112] S. V. Morozov, K. S. Novoselov, M. I. Katsnelson, F. Schedin, D. C. Elias, J. A.
Jaszczak, and A. K. Geim, “Giant intrinsic carrier mobilities in graphene and its
bilayer,” Physical Review Letters, vol. 100, no. 1, p. 016602, Jan. 2008.
[113] H.-Y. Chiu, V. Perebeinos, Y.-M. Lin, and P. Avouris, “Controllable p-n Junction
Formation in Monolayer Graphene Using Electrostatic Substrate Engineering,” Nano
Letters, vol. 10, p. 4634, Oct. 2010.
[114] C. D. Young, Y. Zhao, M. Pendley, B. H. Lee, K. Matthews, J. H. Sim, R. Choi,
G. A. Brown, R. W. Murto, and G. Bersuker, “Ultra-Short Pulse Current-Voltage
Characterization of the Intrinsic Characteristics of High- Devices,” Japanese Journal
of Applied Physics, vol. 44, p. 2437, Apr. 2005.
[115] D. Estrada, S. Dutta, A. Liao, and E. Pop, “Reduction of hysteresis for carbon nanotube mobility measurements using pulsed characterization,” Nanotechnology, vol. 21,
no. 8, p. 85702, Feb. 2010.
[116] K. K. Thornber, “Relation of drift velocity to low-field mobility and high-field saturation velocity,” Journal of Applied Physics, vol. 51, p. 2127, Apr. 1980.
[117] B. Huard, N. Stander, J. A. Sulpizio, and D. Goldhaber-Gordon, “Evidence of the role
of contacts on the observed electron-hole asymmetry in graphene,” Physical Review
B, vol. 78, no. 1, p. 121402, Sep. 2008.
[118] Z. Chen and J. Appenzeller, “Mobility extraction and quantum capacitance impact in
high performance graphene field-effect transistor devices,” Electron Devices Meeting,
2008. IEDM 2008. IEEE International, pp. 1–4, Dec. 2008.
[119] M. Freitag, M. Steiner, Y. Martin, V. Perebeinos, Z. Chen, J. C. Tsang, and
P. Avouris, “Energy Dissipation in Graphene Field-Effect Transistors,” Nano Letters,
vol. 9, p. 1883, Apr. 2009.
[120] I. Meric, C. Dean, A. Young, J. Hone, P. Kim, and K. Shepard, “Graphene fieldeffect transistors based on boron nitride gate dielectrics,” Electron Devices Meeting
(IEDM), 2010 IEEE International, pp. 23.2.1–23.2.4, 2010.
[121] C. R. Dean et al., “Boron nitride substrates for high-quality graphene electronics.”
Nature Nanotechnology, vol. 5, no. 10, pp. 722–726, Oct. 2010.
[122] G. Giovannetti, P. A. Khomyakov, G. Brocks, P. J. Kelly, and J. van den Brink,
“Substrate-induced band gap in graphene on hexagonal boron nitride: Ab initio density functional calculations,” Physical Review B, vol. 76, no. 7, p. 73103, Aug. 2007.
72
[123] K. Watanabe, T. Taniguchi, and H. Kanda, “Direct-bandgap properties and evidence
for ultraviolet lasing of hexagonal boron nitride single crystal.” Nature Materials,
vol. 3, no. 6, pp. 404–409, Jun. 2004.
[124] T. Taniguchi and K. Watanabe, “Synthesis of high-purity boron nitride single crystals
under high pressure by using Ba BN solvent,” Journal of Crystal Growth, vol. 303,
no. 2, pp. 525–529, May 2007.
[125] C. Lee, Q. Li, W. Kalb, X.-Z. Liu, H. Berger, R. W. Carpick, and J. Hone, “Frictional
characteristics of atomically thin sheets.” Science (New York, NY), vol. 328, no. 5974,
pp. 76–80, Apr. 2010.
[126] C. H. Lui, L. Liu, K. F. Mak, G. W. Flynn, and T. F. Heinz, “Ultraflat graphene.”
Nature, vol. 462, no. 7271, pp. 339–341, Nov. 2009.
[127] Y. Taur and T. Ning, Fundamentals of modern VLSI devices, 2nd ed.
University Press, 2009.
Cambridge
[128] Y. Wu, Y.-M. Lin, A. A. Bol, K. A. Jenkins, F. Xia, D. B. Farmer, Y. Zhu, and
P. Avouris, “High-frequency, scaled graphene transistors on diamond-like carbon,”
Nature, vol. 472, no. 7341, pp. 74–78, Apr. 2011.
[129] Q. Liang, J. Cressler, G. Niu, Y. Lu, G. Freeman, D. Ahlgren, R. Malladi, K. Newton,
and D. Harame, “A simple four-port parasitic deembedding methodology for highfrequency scattering parameter and noise characterization of SiGe HBTs,” Microwave
Theory and Techniques, IEEE Transactions on, vol. 51, no. 11, pp. 2165–2174, 2003.
[130] I. Meric, C. R. Dean, S.-J. Han, L. Wang, K. A. Jenkins, J. Hone, and K. L. Shepard,
“High-frequency performance of graphene field effect transistors with saturating IVcharacteristics,” Electron Devices Meeting, 2011. IEDM 2011. IEEE International, to
appear, 2011.
[131] J. Chauhan and J. Guo, “Assessment of High-Frequency Performance Limits of
Graphene Field-Effect Transistors,” arXiv, vol. cond-mat.mes-hall, Feb. 2011.