University of Zagreb
Faculty of Electrical Engineering and Computing
Department of Electronics, Microelectronics,
Computer and Intelligent Systems
El t
i
Electronics
1
Ž. Butković, J. Divković Pukšec, A. Barić
5 Field-Effect Transistors
5.
Field-Effect Transistor
An active electronic device with three terminals
‰ input, output and a common terminal
‰ voltage change in the input terminal controls the current in the
output terminal
‰ applications: amplifier, digital switch
‰ advantage:
d
iinfinite
fi i iinput resistance
i
– electronic
l
i controll without
ih
power consumption
5. Field-Effect Transistors (FETs)
2
Nomenclature
Name
‰ field-effect transistor – electric field (voltage) in the input terminal
is used to modulate the resistance of the semiconductor resistor in
the output
‰ FET – abbreviation for Field Effect Transistor
‰ unipolar transistor – current is carried by only one type of carriers
Types
‰ MOSFET – Metal-Oxide-Semiconductor FET
‰ JFET – Junction
J
ti FET
‰ MESFET – Metal-Semiconductor FET
5. Field-Effect Transistors (FETs)
3
Structure of a MOSFET (1)
Structure of an n-channel MOSFET
Terminals
‰ source → S
‰ drain → D
‰ gate → G
‰ body → B
Channell di
Ch
dimensions
i
‰ L → length
‰ W → width
5. Field-Effect Transistors (FETs)
4
Structure of a MOSFET (2)
For n-channel → p-substrate
(body)
The main
Th
i partt off the
th structure
t t
is MOS
‰ M → metal
‰ O → oxide SiO2
‰ S → semiconductor
Current through a MOS
structure equals IG = 0
n+ regions – for source and
drain contacts
The body (B) is usually connected to source (S)
5. Field-Effect Transistors (FETs)
5
Applying a Small Voltage UDS
Voltage UDS > 0 → pn junction drain-body is reverse-biased
No current between source and drain contacts
For small UDS → depletion regions on the source and drain side of the
channel have equal widths
5. Field-Effect Transistors (FETs)
6
Influence of Applying UGS –
Formation of the Channel
Voltage UGS > 0 attracts electrons
towards the Si-SiO2 interface,
and repels holes away from
the interface
When UGS > 0 is large enough,
yp
the surface becomes n-type
→ inversion layer – n-type
channel
Formation of n-channel → an
n-type semiconductor resistor
is formed between source
and drain
Channel is formed when: UGS = UGS0 → electron concentration in the
channel is equal to hole concentration in the substrate
UGS0 → threshold voltage
5. Field-Effect Transistors (FETs)
7
I-U Characteristics for Small UDS
For UGS > UGS0 and for small UDS > 0
there exists a non-zero drain
current ID
For small UDS > 0 the voltage
g drop
p
across the channel is negligible;
MOSFET is a linear resistor
UGS0 = 1 V
5. Field-Effect Transistors (FETs)
When UGS increases, electron
concentration in the channel
and channel conductivity
increases; MOSFET is a
voltage-controlled linear resistor
8
Applying a Higher UDS –
Decrease of Channel Thickness
When UDS increases, voltage drop
occurs inside the channel
Electron concentration in the channel is
determined by:
UGS - on the source end
UGD = UGS − UDS - on the drain end
Channel thickness decreases towards
the drain end → channel resistance
increases
5. Field-Effect Transistors (FETs)
9
Applying a Higher UDS –
Channel Pinch-Off
For UDSS = UGS − UGS0 → UGD = UGS0 →
the channel vanishes at the drain
end of the channel (pinch-off)
5. Field-Effect Transistors (FETs)
10
ID Change with UDS
For low UDS → ID increases linearly with
UDS → linear region
For higher UDS < UGS − UGS0 → channel
resistance increases; ID increases
slowly with UDS → triode region
For UDS = UGS − UGS0 = UDSS → pinch-off;
drain current reaches maximum
value IDS
For UDS > UGS − UGS0 → the channel is
closed; current remains constant
ID = IDS → saturation region
5. Field-Effect Transistors (FETs)
11
Derivation of the Current-Voltage
Characteristic (1)
UGS > UGS0, UDS < UGS − UGS0
Oxide capacitance per unit area:
Cox = εox/tox
Charge:
d Q = − Cox (d y ⋅ W ) [U GS − U GS 0 − U ( y )]
Drift current:
I Fn =
dQ dQ d y dQ
vdn ( y )
=
=
dt d y dt d y
vdn ( y ) = − μ n F ( y) = μ n d U ( y ) /d y
I Fn = − μ n Cox W [U GS − U GS 0 − U ( y ) ]
Drain current:
5. Field-Effect Transistors (FETs)
d U ( y)
dy
I D = − I Fn
12
Derivation of the Current-Voltage
Characteristic (2)
Differential equation:
I D d y = μn Cox W [U GS − U GS 0 − U ( y )]d U ( y )
Integration over the channel: from y = 0 to y = L; from U(0) = 0 to U(L) = UDS
2 ⎤
U DS
⎡
→ currentt ID in
i triode
t i d region
i
I D = K ⎢(U GS − U GS 0 )U DS −
⎥
2 ⎦
⎣
K = μn Cox
W
L
→ transconductance p
parameter
For UDS = UDSS = UGS − UGS0
I D = I DS =
K
(U GS − U GS 0 ) 2 → current ID in saturation region
2
5. Field-Effect Transistors (FETs)
13
Output Characteristics
triode region
for 0 ≤ UDS ≤ UGS − UGS0
2 ⎤
U DS
⎡
I D = K ⎢(U GS − U GS 0 )U DS −
2 ⎥⎦
⎣
saturation region
for UDS ≥ UGS − UGS0
K
(U GS − U GS 0 ) 2
2
linear region for low UDS
I D = I DS =
I D ≈ K (U GS − U GS 0 )U DS
enhancement-type → UGS0 = 1 V
5. Field-Effect Transistors (FETs)
cutoff region for UGS < UGS0
ID = 0
14
Transfer Characteristics
for UDS = 3 V → saturation region
f UDS = 1 V → saturation
for
t ti and
d
triode region
for the saturation region – nonlinear transfer characteristic →
output characteristics are not
equidistant
5. Field-Effect Transistors (FETs)
15
Connection between the Transfer
and Output Characteristics
Transfer characteristics can be constructed from the output characteristics
5. Field-Effect Transistors (FETs)
16
Types of n-Channel MOSFETs
enhancement-type → channel is
formed by a positive voltage
UGS = UGS0
depletion-type → conducts
current when UGS = 0 V;
channel is closed by a negative
voltage UGS = UGS0
n-channel MOSFET → conducts
current for UGS > UGS0
5. Field-Effect Transistors (FETs)
17
Circuit Symbols
for n-Channel MOSFETs
depletion-type
enhancement-type
full line between source and drain → channel exists when UGS = 0 V
dashed line between source and drain → no channel when UGS = 0 V
arrow → from
f
p-substrate
b t t towards
t
d n-channel
h
l
5. Field-Effect Transistors (FETs)
18
Example 5.1
Transfer characteristic of a MOSFET in the
saturation region is shown in the figure.
Thickness of the SiO2 layer above the
channel is 20 nm, while the mobility of
majority carriers in the channel equals
400 cm2/Vs.
a) Find the aspect (width-to-length) ratio W/L
of the channel.
b) Determine the channel length L if the gate
capacitance to the channel must be
CG ≤ 20 fF.
5. Field-Effect Transistors (FETs)
19
p-Channel MOSFET
MOSFET cross-section →
same as the cross
cross-section
section
of the n-channel MOSFET,
but with opposite impurity
yp
types
for p-channel → n-substrate
(body)
p+ regions – source and drain
contacts
5. Field-Effect Transistors (FETs)
20
Circuit Symbols
for p-Channel MOSFETs
depletion-type
enhancement-type
full line between source and drain → channel exists when UGS = 0 V
dashed line between source and drain → no channel when UGS = 0 V
arrow → from
f
p-channel
h
l ttowards
d n-substrate
b t t
5. Field-Effect Transistors (FETs)
21
Types of p-Channel MOSFETs
current ID is negative
Enhancement-type
E
h
tt
→ channel
h
l iis
formed by a negative voltage
UGS = UGS0
Depletion-type → conducts
current when UGS = 0 V;
channel is closed with a
positive voltage UGS = UGS0
p-channel
h
l MOSFET → conducts
d t
current for UGS < UGS0
5. Field-Effect Transistors (FETs)
22
Output Characteristics of
p-Channel MOSFETs
triode region
for UGS − UGS0 ≤ UDS ≤ 0
2 ⎤
U DS
⎡
I D = K ⎢(U GS − U GS 0 )U DS −
2 ⎥⎦
⎣
saturation region
g
for UDS ≤ UGS − UGS0
K
(UGS − UGS 0 )2
2
transconductance parameter
ID =
K = −μ pCox
enhancement-type → UGS0 = − 1 V
5. Field-Effect Transistors (FETs)
W
L
cutoff region for UGS > UGS0
ID = 0
23
CMOS Structure
nMOS → on p-substrate
pMOS → in a separate n
n-well
well
In order to achieve electrical insulation, p-substrate is connected to the
lowest, whereas the n-well is connected to the highest voltage available
in the circuit
5. Field-Effect Transistors (FETs)
24
Example 5.2 (1)
MOSFET has a threshold voltage UGS0 = − 1 V and a value of transconductance
parameter K of 0,4 mA/V2. Plot the output characteristics in the case that
MOSFET is:
a) n-channel,
b) p-channel.
a))
U GS , V
−1
0
1
2
3
U GS − U GS 0 , V
0
1
2
3
4
I D , mA
0
02
0,2
08
0,8
18
1,8
32
3,2
U GS , V
−1
−2
−3
−4
−5
U GS − U GS 0 , V
0
−1
−2
−3
−4
I D , mA
0
− 0,2
− 0,8
− 1,8
− 3,2
b)
5. Field-Effect Transistors (FETs)
25
Example 5.2 (2)
5. Field-Effect Transistors (FETs)
26
Drain Current Increase
in the Saturation Region
n-channel enhancement-type MOSFET → UGS0 = 1 V
5. Field-Effect Transistors (FETs)
27
Channel-Length Modulation
Pinch-off point moves towards the
source end of the channel
Channel length decreases
I the
In
th channel,
h
l electrons
l t
move d
due
to voltage UDS = UDSS = UGS − UGS0
In the saturation region, ID increases with UDS
1
1
W
(U GS − U GS 0 )2 = I DS
I D = μn Cox
2
L − ΔL
1 − (ΔL / L)
5. Field-Effect Transistors (FETs)
28
Junction FET Structure
Structure of an n-channel junction FET (JFET)
Terminals
‰ source → S
‰ drain → D
‰ gate → G
‰ second gate → G2
Channell
Ch
‰ L → length
‰ W → width
‰ 2a → channel thickness
5. Field-Effect Transistors (FETs)
29
Circuit Symbols of JFETs
n-channel
p-channel
arrow → from p-type towards n-type semiconductor
for n-channel → from p-gate towards n-channel
f p-channel
for
h
l → from
f
p-channel
h
l ttowards
d n-gate
t
5. Field-Effect Transistors (FETs)
30
Pinch-Off Voltage
and Linear Region
UGS < 0 → pn-junction gate-channel is
reverse-biased
For low UDS → voltage drop across the channel
is negligible
When UGS increases → depletion layers widen
→ channel narrows down
F UGS = UP → the
For
th channel
h
l iis closed
l
d ((pinch-off)
i h ff)
UP ≡ pinch-off voltage
For low UDS, JFET is a linear resistor
⎡ ⎛ U 0 − U GS ⎞1/2 ⎤
I D = G0 ⎢1 − ⎜
⎟ ⎥ U DS
U
U
−
P ⎠ ⎥
⎢⎣ ⎝ 0
⎦
U0 → built-in voltage gate-channel
G0 → conductance of a completely open channel
5. Field-Effect Transistors (FETs)
31
Applying a Higher UDS
Increase of UDS causes a voltage drop
in the channel
pn junction gate
gate-channel
channel is more
strongly reverse-biased on the drain
side
Channel narrows down near the drain
→ channel resistance increases
Current ID slowly rises with increasing
UDS → triode region
⎡⎛ U 0 − U GS + U DS ⎞3/2 ⎛ U 0 − U GS ⎞3/2 ⎤ ⎫⎪
U 0 − U P ⎧⎪ U DS
− 2 ⎢⎜
I D = G0
⎨3
⎟ − ⎜ U − U ⎟ ⎥⎬
3
U
−
U
U
−
U
P
0
P
P ⎠
⎠
⎝ 0
⎢⎣⎝
⎥⎦ ⎪⎭
⎪⎩ 0
The current ID depends on UDS and UGS
5. Field-Effect Transistors (FETs)
32
Channel Pinch-Off
For UDSS = UGS − UP → UGD = UP → the
channel vanishes (pinch-off) on
the drain end of the channel
The current reaches the maximum
value ID = IDS → saturation region
I D = I DS
3/2
⎡
⎤
⎛
⎞
U0 − U P
U 0 − U GS
U 0 − U GS
= G0
+ 2⎜
⎢1 − 3
⎟ ⎥
3
U
U
U
U
−
−
0
P
P ⎠
⎝ 0
⎢⎣
⎥⎦
The current ID depends only on voltage UGS
5. Field-Effect Transistors (FETs)
33
Channel-Length Modulation
Pinch-off point moves toward source
The channel becomes shorter
In the channel, the electrons move due
to voltage UDS = UDSS = UGS − UP
In the saturation region, the drain current ID increases with UDS
I D = I DS
L
L − ΔL
5. Field-Effect Transistors (FETs)
34
JFET Characteristics
transfer characteristic
output characteristics
IDSS → maximum current of a JFET
for UDS = UDSS < UGS − UP → triode region
for UDS = UDSS > UGS − UP → saturation region
5. Field-Effect Transistors (FETs)
35
JFET in Saturation Region
JFET is mostly used in amplifiers – operates in saturation region
Instead of the correct but impractical
expression, a simpler equation is
used in circuit analysis:
I D = I DS
⎛ U ⎞
= I DSS ⎜1 − GS ⎟
UP ⎠
⎝
2
full line – exact expression
dashed line – simpler equation
5. Field-Effect Transistors (FETs)
36
MESFET
Implemented with gallium-arsenide – high speed device
Similar to JFET
Gate-channel
Gate
channel junction is a rectifying metal-semiconductor
metal semiconductor junction
For proper operation → UGS < 0
5. Field-Effect Transistors (FETs)
37
Temperature Dependence
MOSFET – an increase of temperature
results in a decrease of K and UGS0
JFET – mobility decreases and
depletion layers narrow down when
temperature increases
For both types of FETs →
when
h ttemperature
t
increases,
i
the
th
current ID increases for lower current
values, whereas the current
decreases for higher current values
5. Field-Effect Transistors (FETs)
38
Breakdown Types in FETs
MOSFET
‰ avalanche breakdown of the drain-substrate junction
‰ punch-through
‰ oxide breakdown
JFET
‰ avalanche breakdown of the
drain-channel junction; if the
breakdown voltage is designated
as UB the breakdown happens for
UDS = UB + UGS
5. Field-Effect Transistors (FETs)
39
Dynamic Parameters of FETs
Describe the relations between ac signals in the small-signal operation
For the small signal: iD = f(uGS, uDS)
d iD =
∂ iD
∂i
d uGS + D d uDS
∂ uGS
∂ uDS
→ id = g m u gs + g d uds
Dynamic
D
i parameters:
t
‰ transconductance
gm =
d iD
d uGS
=
uDS = konst
id
u gs
uds = 0
‰ output dynamic conductance
i
d iD
gd =
= d
d uDS u = konst uds u = 0
GS
5. Field-Effect Transistors (FETs)
ggs
output dynamic resistance
rd =
1
gd
40
Small-Signal FET Model
Used in the saturation region
Follows from: id = gm ugs + uds/rd
voltage gain factor
In another form:
uds = − μ ugs + rd id , μ = gm rd
μ =−
d uDS
d uGS
=−
iD = konst
uds
u gs
id = 0
No load in the output → id = 0 uds = − gm rd ugs = − μ ugs
maximum voltage
g g
gain of a FET
5. Field-Effect Transistors (FETs)
41
High Frequency Model
Capacitances Cgs and Cgd:
for MOSFETs → capacitance of a MOS structure
for JFETs → capacitance of reverse
reverse-biased
biased pn
pn-junctions
junctions
for MESFETs → capacitance of a reverse-biased metal-semiconductor
junction
5. Field-Effect Transistors (FETs)
42
Dynamic Parameters –
Graphical Determination (1)
Transconductance:
gm =
5. Field-Effect Transistors (FETs)
Δ iD
Δ uGS
U DS = const
43
Dynamic Parameters –
Graphical Determination (2)
Output dynamic resistance:
rd =
5. Field-Effect Transistors (FETs)
Δ u DS
Δ iD
U GS = const
44
Dynamic Parameters –
Analytical Determination (1)
Transconductance:
‰ MOSFET
K
(uGS − UGS 0 )2
2
di
gm = D = K (U GS − UGS 0 ) = 2 K I D
d uGS
iD =
‰ JFET
⎛ u ⎞
iD = I DSS ⎜1 − GS ⎟
⎝ UP ⎠
gm =
2
d iD
2I
2
⎛ U ⎞
= DSS ⎜1 − GS ⎟ =
I DSS I D
UP ⎠ − UP
d uGS −U P ⎝
5. Field-Effect Transistors (FETs)
45
Dynamic Parameters –
Analytical determination (2)
Output dynamic resistance:
a model defined from the slope of
output characteristics in the
saturation region
‰ MOSFET
K
(uGS − UGS 0 )2 (1 + λ uDS )
2
d iD
K
2
gd =
= λ (U GS − U GS 0 )
d uDS
2
iD =
‰ JFET
2
⎛ u ⎞
iD = I DSS ⎜1 − GS ⎟ (1 + λ uDS )
⎝ UP ⎠
gd =
for both FETs
5. Field-Effect Transistors (FETs)
rd =
d iD
d uDS
⎛ U ⎞
= λ I DSS ⎜1 − GS ⎟
UP ⎠
⎝
2
1 1 + λ U DS
1
=
≈
gd
λ ID
λ ID
46
Example 5.3
Parameters of an n-channel MOSFET are given as follows: transconductance
parameter K = 80 μA/V
A/V2, threshold voltage UGS0 = 2 V and channel
channel-length
length
modulation factor λ = 0,005 V-1. Gate bias of UGS = 5 V is applied. Find the
drain current ID, transconductance gm, output dynamic resistance rd and
voltage gain factor μ if:
a)
UDS1 = (UGS − UGS0)/2,
b)
UDS2 = 2(UGS − UGS0).
)
5. Field-Effect Transistors (FETs)
47
Example 5.4
Threshold voltage of a p-channel MOSFET is UGS0 = − 1,5 V. If the MOSFET is
biased in saturation region with gate voltage of UGS = − 4 V, the drain current
is 1 mA. Find voltage UGS and transconductance gm for that FET in saturation
region if the current equals 4 mA. Assume that the current does not increase
in saturation.
5. Field-Effect Transistors (FETs)
48
Example 5.5
Output characteristics of a realistic
MOSFET, obtained by
measurements, are shown in the
figure.
figure
a) Determine the dynamic parameters
in the operation point A:
transconductance gm, output
dynamic resistance rd and voltage
gain factor μ.
b) Find the channel-length modulation
parameter λ that approximates the
slope of the output characteristic in
saturation.
c)) Using
U i λ,
λ calculate
l l t th
the output
t t
dynamic resistance for UDS = 7 V
and for all three UGS shown in the
figure.
g
5. Field-Effect Transistors (FETs)
49
Summary of Important
Equations (1)
MOSFET – current-voltage characteristics
cut-off region
ID = 0 for UGS < UGS0 (n-channel) and for UGS > UGS0 (p-channel)
triode region
2
⎡
⎤
U DS
I D = K ⎢ (U GS − U GS 0 )U DS −
⎥ for 0 ≤ U DS ≤ U GS − U GS 0
2
⎣
⎦
saturation
t
ti region
i for
f UDS ≥ UGS − UGS0
I D = I DS =
K
(U GS − U GS 0 ) 2 for U DS ≥ U GS − U GS 0
2
transconductance parameter → K = μ Cox
5. Field-Effect Transistors (FETs)
W
L
50
Summary of Important
Equations (2)
MOSFET – dynamic parameters
drain current
K
2
iD = ( uGS − U GS 0 ) (1 + λ uDS )
2
transconductance
di
g m = D = K (U GS − U GS 0 ) = 2 K I D for λU DS << 1
d uGS
output
t td
dynamic
i resistance
i t
gd =
d iD
K
2
= λ (U GS − U GS 0 )
d u DS
2
→ rd =
1 1 + λ U DS
=
gd
λ ID
voltage gain factor → μ = gm rd
5. Field-Effect Transistors (FETs)
51