Department of Electrical and Information Engineering
Seoul National University of Science and Tech nology
Seoul, Korea
E-mail: schoi@seoultech.ac.kr
Abstract —This paper proposes a non-isolated soft-switching bidirectional DC-DC converter suitable for high step-up and step-down applications. The proposed converter can achieve
ZVS turn on of all switches and ZCS turn off of some switches in both CCM boost and buck operations. An optimized switching strategy is presented to minimize switch current rating and achieve soft-switching in wider range. An intermediate switching pattern is introduced to carry out seamless mode change.
Experimental results from a 5kW prototype are provided to validate the proposed concept. converters, in general, the effort to overcome the problem associated with leakage inductor of the coupling inductor is non-trivial, and the capacity of the magnetic core should substantially be increased as the required output power is increased. Therefore, these topologies incorporating the coupling inductor are not suitable for high power applications.
Also, the input current ripple is considerable due to the operation of coupling inductor.
I.
I
NTRODUCTION
In hybrid electric vehicles(HEV) the input voltage of the inverter has a tendency to increase in order to use high speed high power motor and improve the efficiency and power density of the inverter. For example, the input voltage has increased from 500V to 650V in 3rd generation PCU of
Toyota Prius HEV where a Ni-MH battery of nominal voltage of 201.6V has been installed[1]. In the meantime the battery voltage is preferred to be low since parallel strings of storage batteries not only enhance the redundancy of the back-up system but also alleviate the problems associated with charge imbalance compared to series strings. Therefore, high efficiency bidirectional DC-DC converter (BDC) with high voltage gain is necessary in the aforementioned systems. The non-isolated BDC based on the half-bridge topology has a simple structure but should operate at high duty cycle to provide high step-up gain (greater than 4) when the battery voltage is low. Then, the boost diode must sustain a short pulse current with high amplitude, resulting in severe reverse
The BDC using switched-capacitor converter cells could have more modular structure and higher power handling capability, but the required number of switches becomes high
[6]-[8]. They are hard-switched, and high current pulse occurs since two capacitors with different voltages are connected in parallel at each switching instant. A major drawback of the switched-capacitor based converter is that ESR drop of the active and passive devices is considerable due to high number of series connected devices in the current path, resulting in reduced output voltage. This may restrict the power level to which the switched-capacitor converter can be applied.
Soft switched BDCs with a auxiliary circuit have been proposed to achieve ZVS or ZCS of main switches in both boost and buck modes of operations [9],[10]. The converter in
[10] shows high efficiency despite of its circuit complexity.
However, they are not suitable for applications where high voltage conversion ratio in both buck and boost operations is required. So far, the non-isolated BDC with high voltage gain that can be applied to high power level has rarely been proposed. recovery as well as high EMI problems. Using an extreme duty cycle may also lead to poor dynamic responses to line and load variations. Moreover, the switch should sustain high output voltage, and hence switch conduction losses resulting from the high on drop voltage of the high-voltage-rated switches are considerable. These make the conventional halfbridge topology inefficient in the applications where high voltage gain is required.
BDCs based on coupled or tapped inductors [2]-[5] can provide high output voltage without extreme duty cycle and yet reduce the switch voltage stress. In these coupled inductor
In this paper a new non-isolated BDC for high step-up/step down and high power applications is proposed. The optimized
PWM switching technique for buck and boost operation and smooth mode transition is also presented. The proposed converter has the following advantages:
• High voltage gains for both boost and buck mode operations.
• Reduced voltage stresses of switches.
• ZVS turn-on of switches in CCM operation.
• Reduced energy volumes of passive components
• Seamless mode transition
This work was supported by the National Research
Foundation of Korea(NRF) grant funded by the Korea government(MEST) (No. 2012-0005045).
978-1-4673-4355-8/13/$31.00 ©2013 IEEE 1776

II.
P ROPOSED C ONVERTER
Fig. 1 shows the circuit diagram of the proposed BDC.
The proposed converter consist of a general buck/boost converter as the main circuit and an auxiliary circuit which includes capacitor
(HVS) switches S
3
C a
, inductor L
and S
4 a
and two high voltage side
. The goal of control in this paper is assumed to regulate the HVS voltage V
H
while allowing bidirectional power flow according to the direction of inductor current I
Lf
.
A.
Operating Principle
Assume that capacitances C
1
, C
2 so that voltages V
C 1
, V
C 2
and V during the switching period T
S
.
Ca
and C a
are large enough
across them are constant
1) Boost Operation
Fig. 2 and Fig. 3 show key waveforms and operation states of the boost mode, respectively. In this mode, low voltage side
(LVS) switches S
1
and S
2
are operated with asymmetrical complementary switching with duty cycles of D and 1D , respectively, as shown in Fig. 2. In the mean time HVS switches S
3
and S
4
are turned on with delay times of t d 3
and t d 4 divided into five modes, as shown in Fig. 3
, respectively. The operation of the proposed converter can be
Mode I [t and S
4
0
~ t
1
] : This mode begins with turning off of S
2
. Then the body diodes of S
1
and S
4
are turned on. The gating signal for S
1
is applied with appropriate dead-time during this mode, and then S condition. Inductor currents following equations:
1
could be turned on under ZVS i
Lf
and i
La
start to increase and decrease, respectively, with the slopes determined by the d dt i
Lf
=
V
L f
L (1)
Fig. 1. Proposed high step-up soft-switched bidirectional dc-dc converter. t
0
~ t
1
L f
S
2
C a
L a
S
4
S
3
C
2
V
H
V
L
S
1
C
1
V
L t
1
~ t
2
L f
S
2
S
1
C a
L a
S
4
S
3
C
2
V
H
C
1
V
L t
2
~ t
3
L f
S
2
S
1
C a
L a
S
4
S
3
C
2
V
H
C
1
Fig. 2. Key waveforms of the proposed converter(boost mode).
V
L t
3
~ t
4
L f
S
2
S
1
C a
L a
S
4
S
3
C
2
V
H
C
1 t
4
~ t
5
L f
S
2
C a
L a
S
4
S
3
C
2
V
L
S
1
C
1
Fig. 3. Operation states of the proposed converter(boost mode).
V
H
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d dt i
La
=
V
Ca
− V
C 1
− V
C 2
L a
. (2) completely discharged. Inductor current with the slope determined by equation(1). i
Lf
starts to decrease
Mode II [t
1
~ t
2
] : When the increasing current i
Lf greater than the decreasing current i
La
becomes
, current flowing through
S
1
is reversed, and the main channel of S mode ends when the decreasing current i
Note that switch S
4
La
1
conducts. This
reaches to 0A.
is also turned off under ZCS condition.
Mode III [t
2
~ t body diode of S
3
3
] : At t
2
current i
La
is reversed and the
is turned on. For synchronous rectification the gating signal for S
3
can be applied after t
2
. Note that S turned on under ZVS condition. Inductor current i
3
is
La
linearly increases with the slope determined by the following equations:
Mode II [t
1
~ t
2
] : At t
1
inductor current decrease with the slope determined by equation(3). i
La starts to
After appropriate dead-time switches S on. The gate signal for S
3 current i
La
for ZVS turn on. Note S
1
1
and S
3 are turned
should be applied before reversal of
is turned on without any delay for synchronous rectification. This mode ends when the decreasing current i
La
reaches to 0A.
Mode III [t
2
~ t
3
] : At t
2
inductor current i starts increasing with slope determined by equation (3). From equation (3) the positive peak value of i
La follows:
La
is reversed and
can be obtained as d dt i
La
=
V
Ca
− V
C 1
L a
. (3)
I
La +
=
V
Ca
− V
C 1
L a
⋅ DT
S
+ V
C 2
⋅
2 ⋅ C
OSS
L a
. (7)
Both inductor currents i
Lf
and i
La
flow through switch S
1
.
Mode IV [t current i
La
are turned on. Inductor
starts to decrease with the slope determined by equation (2).
3
~ t
4
] : Switches S and then body diodes of S
1
and S
1
and S
4
3
are turned off at t
3
,
Mode IV [t
3
~ t
4
] : At t
3
switches S
1 and then body diodes of S
2
and S
3 currents i
Lf
and i
La
and S
3
are turned off,
are turned on. Both inductor
start to decrease with the slopes determined by the following equations: d dt i
Lf
=
V
L
−
L f
V
C 1
Note that S
(4)
4 gate signal for S
could be turned on under ZVS condition if the
4
is applied with appropriate dead-time before reversal of current i
La
. This mode ends when the decreasing d dt i
La
=
V
Ca
L a
. (5) i
La
The gating signal for S
2
is applied with appropriate deadtime during this mode, and then S
2
could be turned on under
ZVS condition. This mode ends when the decreasing current
reaches to 0A. Note that switch S
3
is also turned off under
ZCS condition.
Mode V [t
4
~ t
5
] : This mode begins when current i
La
is reversed and the body diode of S
4
is turned on. For synchronous rectification the gating signal for S applied after t
4
. Note that S
Inductor current i
La
4 determined by the following equation:
4
can be
is turned on under ZVS condition.
linearly increases with the slope d dt i
La
=
V
Ca
− V
C
L a
2 .
This is the end of one complete cycle.
(6)
2) Buck Operation
Fig. 4 and Fig. 5 show key waveforms and operation states of the buck mode, respectively. In this mode, HVS switches S and S
4 with delay time of t d 2 can be divided into six modes, as shown in Fig. 5.
3 switching with duty cycles of D and 1D , respectively, as shown in Fig. 4. In the mean time LVS switch S
2
is turned on
. The operation of the proposed converter
are operated with asymmetrical complementary
Mode I [t
0
~ t
1 switches S
2
and S
4
] : This mode begins with turning off of
. Then the body diodes of S
1
and S turned on after the parasitic capacitors of S
1
and S
3
3
are
are
Fig. 4. Key waveforms of the proposed converter(buck mode).
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t
0
~ t
1
L f
S
2 t
1
~ t
2
L f
S
2
L a
S
4
The negative peak value of i
La following equation:
is determined by the
V
L
V
L
S
1
S
1
C a
C a
L a
S
4
S
3
S
3
C
2
C
1
C
2
V
H
V
H
I
La −
= I
Lf
+
Δ I
Lf
2
−
L a
V
C 1
/ (2 ⋅ C
OSS
)
. (8)
For ZVS turn on of S
2 the gate signal for S
2 applied before the decreasing current i
La the increasing current i
Lf
.
should be
becomes smaller than
Mode VI [t
5
~ t
Inductor currents i
La
6
] : At t
5
and i with slopes determined by equations (6) and (4), respectively.
At the end of this mode S end of one complete cycle.
2
Lf switch current i
S2
is reversed.
keep decreasing and increasing
and S
4
are turned off. This is the
C
1
V
L
V
L
V
L t
2
~ t
3
L f
S
2
S
1 t
3
~ t
4
L f
S
2
S
1 t
4
~ t
5
L f
S
2
S
1
C a
C a
C a
L a
S
4
S
3
L a
S
4
S
3
L a
S
4
S
3
C
2
C
1
C
2
C
1
C
2
C
1
V
H
V
H
V
H
B.
Voltage Conversion Ratio
The HVS voltage is given by the following equation:
V
H
=
1 −
2
D eff
⋅ V
L
(9) where the effective duty is defined as follows(See Fig. 2):
D eff
D ( d
3
+ d
4
) (10) where d
3
+ d
4
means duty loss. The output voltage can also be expressed as follows:
V
H
=
1 −
2
D
V
L
V (11) where Δ V is the voltage drop caused by the duty loss. From
(9), (10) and (11) the voltage drop Δ V can be obtained as follows:
2 ⋅ ⋅ ( d
3
+ d
4
)
(1 − D )(1 − + + d
4
)
. (12)
Voltage V
C 1 that is same as output voltage of the general boost converter can be expressed as follows:
V
L t
5
~ t
6
L f
S
2
S
1
C a
L a
S
4
S
3
C
2
C
1
Fig. 5. Operation states of the proposed converter(buck mode).
V
H
V
C 1
=
1 −
1
D
⋅ V
L
. (13)
By applying volt-second principle to inductor L a
, we can obtain the minimum delay times for ZVS turn on of S
3 and S
4 by the following equations:
S
=
I
La +
⋅ L a
V
C 1
(14) current i
La
reaches to 0A. S
=
I
La
V
−
C 1
⋅ L a . (15)
Mode V [t greater than the decreasing current i
Lf currents i
La
4
~ t
5
] : When the increasing current i
La
2
are completely charged and discharged, respectively, the body diode of S
2 with slopes determined by equations (6) and(4).
becomes
, body diode of S
1
is turned off under ZCS condition. Then after parasitic capacitors of S
1
and S
and i
Lf
is turned on and inductor
start to decrease and increase, respectively,
Since the average value of switch currents i
S3
and i
S4 same as that of HVS current I
H
= V
H duty losses d
3
and d
4
/ positive and negative peak values of the inductor current i can be approximated, respectively, by
R
H
is the
and the difference in
are much smaller than duty cycle D ,
La
1779

I
La +
I
La −
≅
1 −
2 V
H
D R
H
⋅ T
S
10
2 V
D R
H
H
T
S
8
The actual delay times for S
3 determined, respectively, as follows:
and S
4
, t d 3
and t d 4
, are
6 t d 3
= d T
S
+ dead-time t d 4
=
S
+ dead-time
From (9), (10), (13), (14) and (15) the voltage gain can be obtained as follows:
0
0 0.1
0.2
0.3
0.4
0.5
Duty
0.6
0.7
V
H
V
L
=
2 (1 − D ) 2 + 4 where
= DR
H
and
= 4 L a
.
D )
(20)
Fig. 6. Voltage gain of the proposed converter.
Using (20) the voltage gain of the proposed converter is plotted as shown in Fig. 6.
0.8
0.9
1
C.
Mode Change Strategy
The optimized switching patterns for boost and buck operations are different as we can see from Fig. 7(a) and (c).
In this section a mode change strategy is proposed for seamless transfer from buck mode to boost mode, and vice versa. In order to carry out seamless transfer during mode change an intermediate switching pattern (See Fig. 7(b)) is inserted between the two switching patterns for boost and buck modes. The switching sequence for transfer from boost mode to buck mode is Pattern1 → Pattern2 → Pattern3. The switching sequence for transfer from buck mode to boost mode is Pattern3 → Pattern2 → Pattern1. Fig. 8 and Fig. 9 show the switching sequence and control block diagram for the proposed BDC, respectively. The moment at which the switching pattern is changed is determined by comparing the instantaneous average value I
Lf,avg
of the inductor current to the preset values of I
Lf ,upper
or I
Lf ,lower
.
Pattern 1 Pattern 2
(a)
(b)
(c)
Fig. 7. Switching pattern for each operation. (a) Pattern 1 (boost operation). (b) Pattern 2 (intermediate operation). (c) Pattern 3 (buck operation).
Pattern 3 Pattern 2 Pattern 1
S
1
, S
2
S
3
, S
4
I
Lf ,avg i
Lf
I
Lf ,upper
0
I
Lf ,lower
Boost Mode
Fig. 8. Switching sequence for seamless mode change.
Buck Mode Boost Mode
1780

III.
E XPERIMENTAL R ESULTS
The interleaving technique can be applied to reduce the size of passive components and current stresses. A 5kW prototype of the two-phase interleaved version of the proposed converter shown in Fig. 10 was built according to the following specification:
• P o
= 5kW • V
H
= 400V • V
L
= 72V
• f s
= 20kHz • L a
= 4uH • C a
= C
1
= C
2
= 30uF
Both LVS and HVS switches are implemented with
IXFN100N50P(500V, 90A, and 49m Ω ) MOSFET. The nominal duty cycle of 0.64 was used to achieve voltage gain of 5.5 in the both buck and boost modes of operation. The actual delay times t d 2
, t d 3
and t d 4
were chosen to be 1500ns,
1500ns and 1200ns, respectively. The pre-set values I
Lf ,upper
for mode change were used as 1.5A and -1A, and I
Lf ,lower respectively. Experimental waveforms of mode change are also shown in Fig. 11. It is seen that there are no transients caused by change of switching patterns during the mode change. Experimental waveforms of the proposed converter for boost and buck operations are shown in Figs. 12 and 13, respectively. Figs. 12 (a) to (d) show voltage and current waveforms of switches S
1
to S
4
in boost mode. Figs. 13 (a) to
(d) show voltage and current waveforms of switches S
1
to S
4 in buck mode. It can be seen that all switches are turned on with ZVS in both operations. The measured efficiency is shown in Fig. 14. The efficiency was measured by
YOKOGAWA WT3000. The maximum efficiency in boost mode and buck mode is 97.3% at 1kW and 97.2% at 2kW, respectively.
IV.
C
ONCLUSION
In this paper a non-isolated soft switching BDC has been proposed for high voltage gain and high power applications.
V
H
* i *
Lf
I
Lf
V
H i
Lf
Fig. 9. Control block diagram of proposed converter for regulating HVS voltage under bidirectional operation.
Fig. 10. Circuit diagram of the two-phase interleaved prototype converter.
Fig. 11. Experimental waveforms of mode change.
Fig. 12. Experimental waveforms of the proposed converter in boost mode. (a) voltage and current of switch S
1
. (b) voltage and current of switch S
2
. (c)voltage and current of switch S
3
. (d) voltage and current of switch S
4
.
(a) (b) (c) (d)
Fig. 13. Experimental waveforms of the proposed converter in buck mode. (a) voltage and current of switch S
1
. (b) voltage and current of switch S
2
. (c)voltage and current of switch S
3
. (d) voltage and current of switch S
4
.
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97.5
97
96.5
96
95.5
95
1k 2k
Fig. 14. Measured efficiency.
Boost Mode
Buck Mode
The proposed converter can achieve ZVS turn on of all switches and ZCS turn of some switches in both boost and buck operations. An optimized switching sequence is presented along with an intermediate switching pattern to carry out seamless mode change. A 5kW prototype of the proposed converter has been built and tested to verify the validity of the proposed operation. A nominal duty cycle of
0.64 was used to achieve voltage gain of 5.5 in the both buck and boost modes of operation.
R
3k
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4k 5k
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