Interleaved Power Factor Correction
(IPFC)
© 2009 Microchip Technology Incorporated. All Rights Reserved.
Interleaved Power Factor Correction
Slide 1
Welcome to the Interleaved Power Factor Correction Reference Design Web
Seminar.
My name is ___, I am an Applications Engineer for the High Performance
Microcontroller Division at Microchip.
1
Agenda
Introduction to Power Factor Correction
IPFC Design Overview
IPFC Reference Design
Conclusion
© 2009 Microchip Technology Incorporated. All Rights Reserved.
Interleaved Power Factor Correction
Slide 2
Here is the agenda for the today’s seminar: we will briefly talk about Power Factor
Correction and its importance.
We will also do an overview of what Interleaved PFC is and key design factors will
be discussed.
Finally Microchip’s IPFC reference design will be discussed
2
Agenda
Introduction to Power Factor Correction
IPFC Design Overview
IPFC Reference Design
Conclusion
© 2009 Microchip Technology Incorporated. All Rights Reserved.
Interleaved Power Factor Correction
Slide 3
We will have a short introduction to power factor correction terminology and why it
is important
3
Introduction to PFC
Applied Voltage
Resulting Current
Φ
Φ
S = P2 + Q2
S
cos(Φ) = power factor
© 2009 Microchip Technology Incorporated. All Rights Reserved.
Φ
Interleaved Power Factor Correction
Q
P
Slide 4
The Power Factor is defined as the ratio between the Real Power and the Apparent
Power in an AC circuit. The Real Power represents the net transferred energy
transferred to the load over one complete AC cycle while the Reactive Power
represents the fraction that is only temporarily stored by the load. The Real Power is
the one measured and monitored for power consumption, and its associated energy
being is used to produce mechanical work and heating. Traditionally, the power
factor is associated with the cosine of angle between the real and apparent power
components. For simplicity the apparent power can be represented as the vector sum
of the real and reactive power, but in the case of non sinusoidal periodical signals a
more complex relationship between these components is considered.
4
Introduction to PFC
Un-utilized
power
Applied Voltage
Resulting Current
Φ
Φ
S = P2 + Q2
S
cos(Φ) = power factor
© 2009 Microchip Technology Incorporated. All Rights Reserved.
Φ
Interleaved Power Factor Correction
Q
P
Slide 5
The Power Factor is defined as the ratio between the Real Power and the Apparent
Power in an AC circuit. The Real Power represents the net transferred energy
transferred to the load over one complete AC cycle while the Reactive Power
represents the fraction that is only temporarily stored by the load. The Real Power is
the one measured and monitored for power consumption, and its associated energy
being is used to produce mechanical work and heating. Traditionally, the power
factor is associated with the cosine of angle between the real and apparent power
components. For simplicity the apparent power can be represented as the vector sum
of the real and reactive power, but in the case of non sinusoidal periodical signals a
more complex relationship between these components is considered.
5
Agenda
Introduction to Power Factor Correction
IPFC Design Overview
IPFC Reference Design
Conclusion
© 2009 Microchip Technology Incorporated. All Rights Reserved.
Interleaved Power Factor Correction
Slide 6
In the following section we will have an overview of the proposed solution for
power factor correction. We will talk about three different topologies that allow
power factor correction, and we will also show a simplified electric diagram of an
interleaved Power Factor Correction circuit
6
IPFC Design Overview
AC Supply
PFC
Rectifier
Load
Converter
Vac
Iac
PWM
Vdc
Controller
Specifications:
•Input AC voltage: 85 to 265V
•Power factor: > 0.99
•Output voltage: 400V (±
± 2%)
•THD: <5%
•Output power: 350W
•Efficiency: > 0.95
© 2009 Microchip Technology Incorporated. All Rights Reserved.
Interleaved Power Factor Correction
Slide 7
A power factor correction block diagram can be divided into 3 main blocks: First,
the rectifier which provides DC voltage to the PFC converter stage, then we have
the PFC converter itself which provides the control over the current shape and phase
lag while regulating the output voltage. Finally we have the controller block. The
PFC converter can be implemented using different circuit topologies, each of them
with their advantages and disadvantages. As it may be observed, the input is an AC
supply, the output of the PFC is a DC voltage. An ideal PFC makes sure that its
input impedance is purely resistive. This allows maximum use of usable power, or
real power. The feedback signals needed for the control loop are the rectified AC
voltage, input AC current and output DC voltage. The output of the control block is
a Pulse Width Modulation (PWM) signal.
7
IPFC Design Overview
© 2009 Microchip Technology Incorporated. All Rights Reserved.
Interleaved Power Factor Correction
Slide 8
In this slide, three of the most common topologies of PFC implementation are
presented. We will highlight advantages and disadvantages for each of them. These
topologies are: buck, boost and buck-boost converters.
8
IPFC Design Overview
V1
Buck Converter
S
V2 < V1
ωt
L
+
i
V1
D
C
+
-
i
V2
ωt
0 ̟- ̟
-
© 2009 Microchip Technology Incorporated. All Rights Reserved.
Interleaved Power Factor Correction
Slide 9
Starting with the Buck converter, the output voltage provided to the load is always
less than the input terminals (also known as step down converter). For the purpose
of power factor correction, the buck converter will function in discontinuous
conduction mode.
9
IPFC Design Overview
V1
Buck Converter
S
V2 < V1
ωt
L
+
i
D
V1
C
+
-
-
i
V2
ωt
0 Boost Converter
L
̟- ̟
V2 > V1
V1
D
+
ωt
i
V1
S
-
© 2009 Microchip Technology Incorporated. All Rights Reserved.
C
+
-
V2
i
0
Interleaved Power Factor Correction
ωt
̟
Slide 10
The Boost converter has the output voltage greater than the input (also known as
step up converter). When using this topology for power factor correction the current
is continuous. As shown in the current diagram, Continuous Conduction Mode
allows a continuous current through the inductor.
10
IPFC Design Overview
V1
Buck Converter
S
V2 < V1
ωt
L
+
i
D
V1
C
+
-
-
i
V2
ωt
0 Boost Converter
L
̟- ̟
V2 > V1
V1
D
+
ωt
i
S
V1
C
+
V2
-
i
-
V2 > V1
Buck-Boost Converter
V1
S
D
i
L
© 2009 Microchip Technology Incorporated. All Rights Reserved.
V2 < V1
ωt
+
V1
ωt
̟
0
C
+
V2
i
0
Interleaved Power Factor Correction
ωt
̟
Slide 11
The combination of the Buck Boost converter, as the name suggests, is a
combination of a buck converter and a boost converter, so that the characteristics of
both are achievable. The output voltage can be greater of lower that the input
voltage.
One disadvantage of the buck and buck-boost topologies is that the switch is not
referenced to ground, which makes the driver circuitry more complex. The buckboost topology also inverts the sign of the output voltage, which brings another
disadvantage when comes to a cost effective implementation of the sensing
circuitry.
The preferred method for implementing PFC and Interleaved PFC is the boost
converter due to the reduced current ripple, simplicity of gate driver implementation
and also because it meets our requirements of output voltage. The discontinuous
conduction mode of buck and buck-boost topologies would have a negative
influence on the total harmonic distortion, or THD, and higher gate driver cost.
11
IPFC Design Overview
Primary
(Live) Side
Boost
Diode
PFC
Inductor
L1
D1
+HV_BUS
R4
R1
Vac ~
Q1
PWM1H
+
~
~
R2
-
|VAC|
C3
R5
C2
VDC
Sense
Sense
C1
R3
LIVE_GND
© 2009 Microchip Technology Incorporated. All Rights Reserved.
C4
R6
Rsense
IAC
Sense
PFC
MOSFET
PFC
MOSFET
Interleaved Power Factor Correction
-HV_BUS
Slide 12
The boost converter’s operation is based on the energy stored in inductance L1 as shown.
When Q1 transistor is ON, the current through the inductance is raising and fly-back
diode D1 stops conduction. As soon as Q1 switch opens, there’s no path for the current
that was flowing through the inductor, except the diode D1, the output capacitor C3 and
the load. D1 diode closes and starts conducting since the voltage on its anode is higher
than the rectified voltage of AC source. The voltage across inductance L1 reverses its
sign to maintain current flow. This way, both the energy supplied by the AC source and
the one previously stored in the inductor are transferred to the load and the output
capacitor through diode D1.
The input rectified voltage Vac and the output DC voltage Vdc are measured using resistor
dividers, while the input current is measured using a shunt resistor.
The role of the inductance in this power factor correction topology is essential. The physical
size of the inductor increases with the power rating.
Component size is one of the main reason for implementing an Interleave PFC design.
12
IPFC Design Overview
ID1
PWM1H
IC
90 -265V AC
Is1
Esinglestage =
ID2
IL2
IOUT
PFC output
IL1
IIN
Einterleaved =
PWM1L
1 2
LI
2
1 2 1 2
LI + LI
2
2
Is2
© 2009 Microchip Technology Incorporated. All Rights Reserved.
Interleaved Power Factor Correction
Slide 13
An interleaved PFC consists of a two boost converter sharing the same load
capacitor.
As we can see in the simplified schematic, if we assume we have the same
inductance for each boost converter, we can see that the energy stored by the system
is doubled. Since the energy stored in the inductors is a key factor for determining
the output power capabilities of the system, the output power provided by single
stage PFC can be provided by an Interleaved PFC with much lower inductance
values. Lower inductance means smaller inductors for a given power rating.
13
Agenda
Introduction to Power Factor Correction
IPFC Design Overview
IPFC Reference Design
Conclusion
© 2009 Microchip Technology Incorporated. All Rights Reserved.
Interleaved Power Factor Correction
Slide 14
An Interleaved PFC reference design is presented next
14
IPFC Reference Design
AC Supply
PFC
Rectifier
Load
Converter 1
PFC
Converter 2
Vac Iac
Im1 PWM1 Im2 PWM2
Vdc
Controller
© 2009 Microchip Technology Incorporated. All Rights Reserved.
Interleaved Power Factor Correction
Slide 15
A simplified block diagram of a dual phase interleaved PFC is shown. As mentioned
earlier, a second PFC converter is added sharing the same inputs and outputs.
15
IPFC Reference Design
VDC
VDCref
IAC
VAC
VErr
IErr
IACref
ICAPref
PI Controller
PI Controller
1
Voltage Error Loop
Postscaler
Current Error Loop
PWM1
VAVG
VAC
PWM2
PWM
IErr
IRef = 0
PI Controller
Postscaler
Im1
Load Balance Loop
Im2
© 2009 Microchip Technology Incorporated. All Rights Reserved.
Interleaved Power Factor Correction
Slide 16
The difference between an Interleaved PFC and a single stage PFC is that two
inductors are used for energy storage. Since energy should be distributed equally, a
load balancing controller is added to the interleaved PFC to make sure the system
compensates for variation in inductance values or feedback circuits.
The Interleaved PFC system has three main compensators: one for voltage, one for
current and one for load balance. Additionally, a feed-forward controller is
implemented to compensate for sudden input voltage changes.
The voltage error controller makes sure that the output voltage is not affected by
load variations. The inputs to this controller are DC output voltage and the
corresponding reference. The output of this controller is the current compensator
reference.
The current error controller regulates the phase and shape of the input current. This
input current is the sum of both inductors currents, and it is measured using a shunt
resistor. The output of this controller is a Pulse Width Modulation (PWM) duty
cycle which will be applied to the power MOSFETS.
To balance the currents through both inductors, a Load Balance Loop is
implemented. The inputs to this compensator are the two currents Im1 and Im2. If
these currents are different an unbalance is detected. The PI controller will regulate
this error and adjust the MOSFETs duty cycles. The output of the load balance
control loop will be a duty cycle correction term (or delta PWM), which is
subtracted from ‘PWM1’ to get the final duty cycle of the first boost converter, and
it is added to ‘PWM2’ to determine the balanced duty cycle of the second boost
converter.
16
IPFC Reference Design
12V and
3.3V Power
Supply
Interleaved PFC
boost circuitry
Fault Circuitry
dsPIC
PIM
AC input circuitry
© 2009 Microchip Technology Incorporated. All Rights Reserved.
Interleaved Power Factor Correction
User Interface
Slide 17
The IPFC reference design board can be divided into 6 main functional blocks: the
PFC boost circuitry, the AC input block, the power supply block, the fault circuitry
block and user’s interface and programming block.
The two inductors can be seen for both stages, and MOSFETS with their respective
diodes are mounted underneath the board with a heatsink for better heat dissipation.
17
IPFC Reference Design
Semiconductor selection
− Voltage and current rating
− Conduction and commutation losses
Inductance selection
− Power output rating
− Input current ripple
Capacitor selection
− Output voltage ripple (holdup time)
− ESR value
© 2009 Microchip Technology Incorporated. All Rights Reserved.
Interleaved Power Factor Correction
Slide 18
This is a brief description about component selection for the Interleaved PFC
reference design.
For the semiconductor components selection, voltage and current rating is
important. Besides power rating, conduction and commutation losses are also
important factors for component selection. These losses will determine the overall
efficiency of the system. Semiconductor components losses represent about half of
the total system losses.
The inductance selection is also related to the output power rating. The higher the
output power, the bigger the inductance will be. Another aspect to consider in the
inductor selection is the required input current ripple.
The output capacitor is chosen so that the output voltage ripple is within
specifications. It also depends on the minimum holdup time so that controllers can
act before the output capacitor losses its charge. The Effective Series Resistance
(ESR) of the capacitor also affects the output voltage ripple. Therefore, the
capacitor with the lowest possible ESR is recommended. The ESR of the capacitor
can be lowered by coupling two capacitors in parallel if the board layout dimensions
permit it.
18
Agenda
Introduction to Power Factor Correction
Overview on IPFC Design
IPFC Reference Design
Conclusion
© 2009 Microchip Technology Incorporated. All Rights Reserved.
Interleaved Power Factor Correction
Slide 19
As a conclusion for this web seminar, we will talk about overall advantages of
interleaved PFC compared to single stage PFC, as well as references from our web
site that will help users understand the technical details of interleaved PFC.
19
Conclusion
IPFC represents a cost and space efficient
solution VS single stage PFC (considering a
certain power limit)
IPFC reference design using dsPIC ® DSC
offers the possibility of high integration
factor
© 2009 Microchip Technology Incorporated. All Rights Reserved.
Interleaved Power Factor Correction
Slide 20
Interleaved PFC allows a more efficient power factor correction design. It also
allows space savings since with a much smaller inductors are needed compared to
single stage PFC design. Interleaved PFC also reduces output current ripple since
two inductors are sharing one load at different times.
dsPIC® digital signal controllers combine the right set of peripherals and
computational power to enable Interleaved PFC control with a single device.
This reference design offers a starting platform for these types of applications and
the modular design of the software makes it easy to understand and to add other
functions
20
Resources
For resources and information for Switch
Mode Power Supply applications, visit
Microchip’s SMPS Design Center at:
www.microchip.com/smps
For a single stage PFC implementation
please refer to application note: AN1106
For a detailed description of the interleaved
PFC reference design, please refer to
application note: AN1278, visit
www.microchip.com/ipfc
© 2009 Microchip Technology Incorporated. All Rights Reserved.
Interleaved Power Factor Correction
Slide 21
For resources and information for Switch Mode Power Supply applications, please
visit Microchip’s SMPS Design Center at
www.microchip.com/smps
For details about our single stage PFC implementation please refer to application
note: AN1106
And for a detailed description of the interleaved PFC reference design, please refer
to application note: AN1278, or visit www.microchip.com/ipfc
This wraps up our Interleaved Power Factor Correction web seminar. Thank you for
your interest in the dsPIC® Digital Signal Controllers.
21