EDI8L32512C
512Kx32 CMOS High Speed Static RAM
FEATURES
DESCRIPTION
 DSP Memory Solution
The EDI8L32512C is a high speed, 5V, 16Mb SRAM. The device is
available with access times of 12, 15, 17 and 20ns allowing the creation
of a no wait state DSP memory solution. The high speed, 5v supply
voltage and control lines make the divice ideal for creating floating
point DSP memory solutions.
• Motorola DSP96002
• Analog SHARC DSP
• Texas Instruments TMS320C3x, TMS320C4x
 Random Access Memory Array
The device can be configured as a 512K x 32 and used to create
a single chip external data memory solution for TI's TMS320C30/
C31 (Figure 8), TMS320C32 (Figure 9) or TMS320C4x (Figure
10), Motorola's DSP96002 and Analog's SHARC DSP (Figure 11).
Alternatively, the device's chip enables can be used to configure it
as a 1M x 16. A 1M x 48 program memory array for Analog's SHARC
DSP is created using three devices (Figure 12). If this memory is too
deep, two 512K x 24s (EDI8L24512C) can be used to create a 512K
x 48 array or two 128K x 48 array.
• Fast Access Times: 12*, 15, 17, and 20ns
• TTL Compatible I/O
• Fully Static, No Clocks
 Surface Mount Package
• 68 Lead PLCC, No. 99 JEDEC M0-47AE
• Small Footprint, 0.990 Sq. In.
• Multiple Ground Pins for Maximum Noise Immunity
 Single +5V (±5%) Supply Operation
The device provides a 56% space savings when compared to four
512K x 8, 36 pin SOJs. In addition the EDI8L32512C has only a 10pF
load on the data lines vs. 32pF for four plastic SOJs.
* This product is subject to change without notice.
The device provides a memory upgrade of the EDI8L32256C (256K
x 32) or the EDI8L32128C (128K x 32). For additional upgrade
information see Figure 13.
Note: Solder Reflow Temperature should not exceed 230°C for 10 seconds.
FIGURE 1 – PIN CONFIGURATION
PIN NAMES
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
DQ16
A18
A17
E3#
E2#
E1#
E0#
NC
VCC
NC
NC
G#
W#
A16
A15
A14
DQ15
A0-A18
E0#-E3#
W#
G#
DQ0-DQ31
VCC
VSS
NC
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
VCC
DQ7
DQ6
DQ5
DQ4
VSS
DQ3
DQ2
DQ1
Chip
Enable
E0#
E1#
E2#
E3#
Byte
Control
DQ0-7
DQ8-15
DQ16-23
DQ24-31
BLOCK DIAGRAM
A0-18
19
G#
W#
E0#
E1#
E2#
E3#
DQ31
A6
A5
A4
A3
A2
A1
A0
VCC
A13
A12
A11
A10
A9
A8
A7
DQ0
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
DQ17
DQ18
DQ19
VSS
DQ20
DQ21
DQ22
DQ23
VCC
DQ24
DQ25
DQ26
DQ27
VSS
DQ28
DQ29
DQ30
Address Inputs
Chip Enables
Write Enables
Output Enable
Common Data Input/Output
Power (+5V ±10%)
Ground
No Connection
BYTE CONTROL
TABLE
512K x 32
Memory
Array
DQ0-DQ7
DQ8-DQ15
DQ16-DQ23
DQ24-DQ31
Note: For memory upgrade information, refer to Pg 8, Fig 13 "EDI MCM-L Upgrade Path"
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2011
Rev. 8
© 2011 Microsemi Corporation. All rights reserved.
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EDI8L32512C
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to VSS
Operating Temperature tA (Ambient)
Commercial
Industrial
Storage Temperature, Plastic
Power Dissipation
Output Current
Junction Temperature, TJ
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
-0.5V to 7.0V
0°C to +70°C
-40°C to +85°C
-55°C to +125°C
5.0 Watts
20 mA
175°C
Sym
VCC
VSS
VIH
VIL
Min
4.75
0
2.2
-0.3
Typ
5.0
0
---
Max
5.25
0
VCC+0.5V
0.8
Units
V
V
V
V
AC TEST CONDITIONS
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any
other conditions greater than those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
VSS to 3.0V
5ns
1.5V
Figure 2
Note: For tEHQZ,tGHQZ and tWLQZ, CL = 5pF)
DC ELECTRICAL CHARACTERISTICS
Parameter
Operating Power Supply Current
Standby (TTL) Power Supply Current
Full Standby Power Supply Current
CMOS
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Sym
Conditions
ICC1
ICC2
W# = VIL, II/O = 0mA, Min Cycle
E# ≥ VIH, VIN ≤ VIL or VIN ≥VIH, f = 0MHz
E# ≥ VCC-0.2V
VIN ≥ VCC-0.2V or VIN ≤ 0.2V
VIN = 0V to VCC
V I/O = 0V to VCC
IOH = -4.0mA
IOL = 8.0mA
ICC3
ILI
ILO
VOH
VOL
TRUTH TABLE
Units
Max
Min
12-25
800
200
17/20
720
200
ns
mA
mA
40
40
mA
±10
±10
2.4
0.4
μA
μA
V
V
CAPACITANCE
G#
X
E#
H
W#
X
Mode
Standby
Output
HIGH Z
H
L
X
L
L
L
H
H
L
Output Deselect
Read
Write
HIGH Z
DOUT
DIN
(f=1.0MHz, VIN=VCC or VSS)
Power
ICC2
ICC3
ICC1
ICC1
ICC1
Parameter
Address Lines
Data Lines
Write & Output Enable Line
Chip Enable Line
FIGURE 2 – AC TEST CONDITIONS
Sym
CI
CD/Q
W#, G#
E0#-E3#
Max
30
10
30
8
Unit
pF
pF
pF
pF
FIGURE 3 – AC TEST CONDITIONS
Vcc
Vcc
480Ω
480Ω
Q
Q
255Ω
30pF
255Ω
5pF
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2011
Rev. 8
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EDI8L32512C
AC CHARACTERISTICS READ CYCLE
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access
Chip Enable to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z (1)
Symbol
JEDEC
Alt.
tAVAV
tRC
tAVQV
tAA
tELQV
tACS
tELQX
tCLZ
tEHQZ
tCHZ
tAVQX
tOH
tGLQV
tOE
tGLQX
tOLZ
tGHQZ
tOHZ
12ns*
Min
12
15ns
Max
Min
15
12
12
3
17ns
Max
3
6
3
3
9
3
7
6
Max
20
20
9
3
0
Min
20
17
17
7
3
0
20ns
Max
15
15
6
3
Min
17
9
0
9
0
7
9
9
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
*Advanced Information
Note: 1. Parameter guaranteed, but not tested.
FIGURE 4 – READ CYCLE 1 – W# High, G#, E# Low
tAVAV
A
ADDRESS 1
ADDRESS 2
tAVQV
tAVQX
Q
DATA 1
DATA 2
FIGURE 5 – Read Cycle 2 – W# High
tAVAV
A
tAVQV
E#
tELQV
tEHQZ
tELQX
G#
tGLQV
t GHQZ
tGLQX
Q
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May 2011
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EDI8L32512C
AC CHARACTERISTICS WRITE CYCLE
Parameter
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
Output Active from End of Write (1)
Symbol
JEDEC
Alt.
tAVAV
tWC
tELWH
tCW
tELEH
tCW
tAVWL
tAS
tAVEL
tAS
tAVWH
tAW
tAVEH
tAW
tWLWH
tWP
tELEH
tWP
tWHAX
tWR
tEHAX
tWR
tWHDX
tDH
tEHDX
tDH
tWLQZ
tWHZ
tDVWH
tDW
tDVEH
tDW
tWHQX
tWLZ
12ns
Min
12
8
8
0
0
8
8
8
10
0
0
0
0
0
6
6
3
15ns
Max
6
Min
15
10
10
0
0
10
10
10
12
0
0
0
0
0
7
7
3
17ns
Max
7
Min
17
11
11
0
0
11
11
11
13
0
0
0
0
0
8
8
3
20ns
Max
8
Min
20
12
12
0
0
12
12
12
14
0
0
0
0
0
9
9
3
Units
Max
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*Advanced Information.
Note 1: Parameter guaranteed, but not tested.
FIGURE 6 – WRITE CYCLE 1 – W# CONTROLLED
tAVAV
A
E#
tELWH
tWHAX
tAVWH
tWLWH
W#
tAVWL
tDVWH
D
tWHDX
DATA VALID
tWLQZ
HIGH Z
Q
tWHQX
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2011
Rev. 8
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EDI8L32512C
FIGURE 7 – WRITE CYCLE 2 – E# CONTROLLED
tAVAV
A
tAVEL
tELEH
E
tAVEH
tEHAX
tWLEH
W#
tDVEH
D
tEHDX
DATA VALID
HIGH Z
Q
ORDERING INFORMATION
Industrial (-40°C to +85°C)
Commercial (0°C to +70°C)
Part Number
EDI8L32512C12AC*
EDI8L32512C15AC
EDI8L32512C17AC
EDI8L32512C20AC
Speed
(ns)
12
15
17
20
Package
No.
99
99
99
99
Part Number
Speed
(ns)
15
17
20
EDI8L32512C15AI*
EDI8L32512C17AI
EDI8L32512C20AI
Package
No.
99
99
99
PACKAGE DRAWING – PACKAGE NO. 99 – 68 LEAD PLCC – JEDEC MO-47AE
Weight = 4.2g – Theta JA = 40°C/W – Theta JC = 15°C/W
0.995
Max
0.956
Max
Package No. 99
68 lead PLCC
0.180
Max
0.995 0.956
Max Max
0.040
Max
0.020
0.015
0.930
0.890
0.050
BSC
0.115
Max
Coplanarity (lowest lead to highest lead)0.004
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2011
Rev. 8
© 2011 Microsemi Corporation. All rights reserved.
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Microsemi Corporation • (602) 437-1520 • www.microsemi.com
EDI8L32512C
FIGURE 8 – INTERFACING THE TEXAS INSTRUMENT TMS320C 30/31 WITH THE EDI8L32128C (128KX32)
OR THE EDI8L32512C (512KX32)
Primary Address Bus
A23-0
EDI8L32128/512C
A18 8L32512C only
A17 }
A16
A15 A
A14 D
A13 D
A12 R
E
S
S
A4
B
A3
U
A2
S
A1
A0
TI TMS320C30/31
B
U
S
DQ4
DQ3
DQ2
DQ1
DQ0
E0#
E1#
E2#
E3#
STRB#
R/W#
Primary Databus
D31-0
D
A
T
A
DQ31
DQ30
DQ29
DQ28
DQ27
W#
G#
FIGURE 9 – INTERFACING THE TEXAS INSTRUMENT TMS320C32 WITH THE EDI8L32128C (128KX32)
OR THE EDI8L32512C (512KX32)
Primary Address Bus
A23-0
EDI8L32128/512C
A18 8L32512C only
A17 }
A16
A15 A
A14 D
D
R
E
A6
S
A5
S
A4
A3
B
A2
U
A1
S
A0
TI TMS320C32
PRGW
STRBX_B0
STRBX_B1
STRBX_B2
STRBX_B3
E0#
E1#
E2#
E3#
R/W#
W#
G#
Primary Databus
D31-0
D
A
T
A
B
U
S
DQ31
DQ30
DQ29
DQ28
DQ27
DQ4
DQ3
DQ2
DQ1
DQ0
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2011
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EDI8L32512C
FIGURE 10 – INTERFACING THE TEXAS INSTRUMENT TMS320C4x WITH THE EDI8L32128C (128KX32)
OR THE EDI8L32512C (512KX32)
Global Address Bus
A30-0
EDI8L32128/512C
A18 8L32512C only
A17 }
A16
A15 A
A14 D
A13 D
A12 R
E
S
S
A4
B
A3
U
A2
S
A1
A0
TI TMS320C4X
D
A
T
A
B
U
S
DQ4
DQ3
DQ2
DQ1
DQ0
E0#
E1#
E2#
E3#
STRB0#
Global Databus
D31-0
DQ31
DQ30
DQ29
DQ28
DQ27
R/W0#
W#
G#
FIGURE 11 – INTERFACING THE ANALOG SHARC DSP WITH THE EDI8L32512C (512KX32)
Address Bus
A31 - A0
EDI8L32512C
A18
A17
A16
A15
A14
Analog Device
A4
A3
A2
A1
A0
ADSP-2106X
D47 D46 . . D31 D30 .
.
.
.
DQ31
DQ30
D DQ29
A DQ28
DQ27
T
A
B
U
S
B
U
S
DQ4
DQ3
DQ2
DQ1
DQ0
E0#
E1#
E2#
E3#
W#
G#
MS0#
Databus
D47 - D0
A
D
D
R
E
S
S
WR#
RD#
D5 D4 D3 D2 D1 D0
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May 2011
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EDI8L32512C
FIGURE 12 – INTERFACING THE ANALOG SHARC DSP WITHTHE EDI8L32512C (1MX48)
EDI8L32512C
(Configured as 1Mx16)
Address Bus
A31-A0
MS0#
A17-A0
E0#
E1#
E2#
E3#
MS1#
W#
G#
D
A
T
A
B
U
S
DQ31
DQ15
DQ16
DQ15
WORD1
DQ0
DQ0
WR#
EDI8L32512C
RD#
(Configured as 1Mx16)
D
A
T
A
A17-A0
E0#
E1#
E2#
E3#
Analog Device
ADSP-2106x
B
U
S
W#
G#
DQ31
DQ31
DQ16
DQ15
WORD2
DQ16
DQ0
EDI8L32512C
(Configured as 1Mx16)
D
A
T
A
A17-A0
E0#
E1#
E2#
E3#
Databus
D47-D0
B
U
S
W#
G#
DQ31
DQ47
DQ16
DQ15
WORD3
DQ17
DQ0
DQ16
A18
A17
E3#
E2#
E1#
E0#
NC
VCC
NC
NC
G#
W#
A16
A15
A14
DQ15
FIGURE 12 – EDI MCM-L-UPGRADE PATH
128K x 32
8L32128C
DQ16
NC
NC
E3#
E2#
E1#
E0#
NC
VCC
NC
NC
G#
W#
A16
A15
A14
DQ15
8L32256C
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
DQ16
NC
NC
BS3#
BS2#
BS1#
BS0#
E1#
VCC
NC
E0#
G#
W#
NC
A15
A14
DQ15
256K x 32
DQ16
NC
A17
B53#
B52#
B51#
B50#
E1#
VCC
NC
E0#
G#
W#
A16
A15
A14
DQ15
512K x 32 8L32512C
DQ31
A6
A5
A4
A3
A2
A1
A0
VCC
A13
A12
A11
A10
A09
A08
A07
DQ00
DQ31
A6
A5
A4
A3
A2
A1
A0
VCC
A13
A12
A11
A10
A09
A08
A07
DQ00
DQ31
A6
A5
A4
A3
A2
A1
A0
VCC
A13
A12
A11
A10
A09
A08
A07
DQ00
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
DQ14
DQ13
DQ12
GND
DQ11
DQ10
DQ09
DQ08
VCC
DQ07
DQ06
DQ05
DQ04
GND
DQ03
DQ02
DQ01
DQ14
DQ13
DQ12
GND
DQ11
DQ10
DQ09
DQ08
VCC
DQ07
DQ06
DQ05
DQ04
GND
DQ03
DQ02
DQ01
DQ14
DQ13
DQ12
GND
DQ11
DQ10
DQ09
DQ08
VCC
DQ07
DQ06
DQ05
DQ04
GND
DQ03
DQ02
DQ01
DQ14
DQ13
DQ12
GND
DQ11
DQ10
DQ09
DQ08
VCC
DQ07
DQ06
DQ05
DQ04
GND
DQ03
DQ02
DQ01
DQ31
A6
A5
A4
A3
A2
A1
A0
VCC
A13
A12
A11
A10
A09
A08
A07
DQ00
DQ31
A6
A5
A4
A3
A2
A1
A0
VCC
A13
A12
A11
A10
A09
A08
A07
DQ00
DQ31
A6
A5
A4
A3
A2
A1
A0
VCC
A13
A12
A11
A10
A09
A08
A07
DQ00
DQ31
A6
A5
A4
A3
A2
A1
A0
VCC
A13
A12
A11
A10
A09
A08
A07
DQ00
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
DQ31
A6
A5
A4
A3
A2
A1
A0
VCC
A13
A12
A11
A10
A09
A08
A07
DQ00
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2011
Rev. 8
© 2011 Microsemi Corporation. All rights reserved.
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Microsemi Corporation • (602) 437-1520 • www.microsemi.com
EDI8L32512C
Document Title
512Kx32 CMOS High Speed Static RAM
Revision History
Rev #
History
Release Date
Status
Rev 8
Changes (Pg. 1-9)
May 2011
Final
8.1 Change document layout from White Electronic Designs to Microsemi
8.2 Add document Revision History page
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2011
Rev. 8
© 2011 Microsemi Corporation. All rights reserved.
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