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IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 4, NO. 8, AUGUST 2014
Ultraminiaturized WLAN RF Receiver
Module in Thin Organic Substrate
Srikrishna Sitaraman, Yuya Suzuki, Fuhan Liu, Nitesh Kumbhat, Sung Jin Kim,
Venky Sundaram, and Rao Tummala, Fellow, IEEE
Abstract— This paper presents the design, analysis, and
demonstration of an ultra-thin wireless local area network
(WLAN) RF receiver module with chip-last embedded actives and
embedded passives in a low-loss organic substrate using systemon-package approach. The overall thickness of the module,
including the embedded dies, is 160 µm– more than 3× thickness
reduction compared to current wire-bond and flip-chip packages.
The receiver module consists of gallium arsenide low-noise
amplifier (LNA) dies, chip-last embedded in an ultrathin, lowloss organic substrate, and connected to a substrate-embedded
three-metal-layer band-pass filter (BPF) in close proximity. Fullwave electromagnetic simulation was performed on a 3-D model
of the designed receiver module to obtain its two-port scattering parameters (S-parameters) and to study noise coupling
between the power-supply network and the signal path. The
receiver module was then fabricated, tested for yield of the
BPF, assembled and characterized, and the measured results
were correlated with simulation. The BPF dimensions in the
package were 1.5 mm × 2.9 mm × 0.15 mm, and its measured
pass-band insertion loss was 2.3 dB with more than 15 dB
return loss. The receiver module (LNA + BPF) dimensions were
5.5 mm × 2 mm × 0.16 mm, and it had a measured peak gain of
11 dB with more than 30 dB attenuation in the adjacent-band,
indicating excellent performance in a miniaturized form-factor.
Index Terms— Chip-last embedding, embedded passives,
low-noise amplifier (LNA), organic substrate, system-on-package
(SOP), wireless local area network (WLAN).
I. I NTRODUCTION
T
HE growing demand for smart mobile systems drives
the development of miniaturized electronic devices with
increased functional density. System-on-package (SOP) [1]
and system-on-chip (SoC) are two major approaches
for system integration. For digital integration, SoC and
through-silicon-via integration approaches have achieved
miniaturization with improved performance and low cost.
However, to miniaturize radio frequency (RF) components,
SoC-based solutions [2], [3] suffer from very low Q-factor and
Manuscript received October 26, 2013; revised March 20, 2014; accepted
March 27, 2014. Date of publication June 26, 2014; date of current version
July 31, 2014. Recommended for publication by Associate Editor A. Shapiro
upon evaluation of reviewers’ comments.
S. Sitaraman, F. Liu, N. Kumbhat, S. J. Kim, and V. Sundaram
are with the Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332 USA
(e-mail: srikrishna@gatech.edu; fliu@ece.gatech.edu; nitesh@gatech.edu;
sungjin.kim@prc.gatech.edu; vs24@mail.gatech.edu).
Y. Suzuki and R. Tummala are with the Department of Material Science
Engineering, Georgia Institute of Technology, Atlanta, GA 30332 USA
(e-mail: ysuzuki3@mail.gatech.edu; rao.tummala@ece.gatech.edu).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCPMT.2014.2325592
Fig. 1.
Components of a WLAN sub-system.
high cost. Alternately, SOP approach effectively addresses the
requirements of multifunctional wireless systems by enabling
miniaturized high-performance RF and mixed-signal integration at low cost [1]. Traditional SOP-based integration of
high-performance actives and passives for WLAN RF modules
was demonstrated on low-temperature co-fired ceramics
(LTCC) substrates [4]–[6]. Subsequently, to overcome the
large thickness of LTCC substrates, RF integration on organic
materials, such as liquid crystal polymer (LCP), was developed
with surface mounted actives [7], [8]. Further, to address the
requirement for low-profile form-factor and to improve RF
performance, embedded integration approaches, such as chipfirst fan-out wafer level packaging [9], have been pursued [10].
However, they face the following barriers: 1) yield loss issues
after die embedding causing loss of both substrate and dies;
2) technical challenges associated with embedding multiple
heterogeneous components having dissimilar thicknesses; and
3) thermal dissipation issues among densely integrated actives.
To mitigate such concerns in miniaturizing high-performance
modules, SOP approach using chip-last embedding was pioneered by and is currently being pursued at Georgia Tech
Packaging Research Center (GT-PRC) [11].
Chip-last embedded SOP has six essential advantages over
SoC and chip-first approaches: 1) ability to embed multiple
heterogeneous actives with minimal substrate yield loss;
2) intermediate-testability of substrates and components before
assembly; 3) shorter interconnections between components,
enabling superior electrical performance; 4) accessibility of
the die backside, facilitating improved thermal performance;
5) flexible choice of substrate materials to address the requirements of different components; and 6) low-cost manufacturability for market affordability. A typical WLAN RF receiver
module consists of an LNA and a BPF, as represented in
Fig. 1. Using chip-last SOP, functional WLAN RF receiver
modules were demonstrated in ultrathin six-metal-layer and
three-metal-layer organic substrates [12], [13]. This paper
extends on [13] by including the following: 1) extraction
of S-parameters of the low-noise amplifier (LNA) dies from
2156-3950 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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SITARAMAN et al.: ULTRAMINIATURIZED WLAN RF RECEIVER MODULE IN THIN ORGANIC SUBSTRATE
Fig. 2.
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Stack-up structure of the three-metal-layer substrate.
the LNA module [no band-pass filter (BPF)] measurement;
2) 3-D full-wave electromagnetic (EM) simulation and characterization of the embedded BPF; and 3) 3-D full-wave
EM simulation and analysis of the WLAN receiver module
(LNA + BPF) design. The receiver module demonstrated here
is more than 3× miniaturized in thickness compared to current
wire-bond and flip-chip packages [14].
This paper is organized into six sections. Section I is the
introduction. Section II details the design of the LNA module
and the receiver module (LNA + BPF). Section III presents
the simulation and analysis of the receiver module. Section IV
discusses the fabrication, assembly, and characterization
results. Correlation between the simulation and measurements
is presented in Section V, followed by the conclusion in
Section VI.
II. WLAN R ECEIVER M ODULE D ESIGN
Fig. 3.
LNA module design top view.
Fig. 4.
Simulated performance of the BPF.
Miniaturization of RF components involves electrical design
of miniaturized high-gain actives and high-Q passives, and
interconnecting these components with minimal substrate
losses and interconnection parasitics. While superior performance of RF actives can be achieved through optimal design
of GaAs and GaN dies, miniaturizing high-Q passives requires
substrate materials having high permittivity (Dk) and lowloss tangent (Df); and short interconnections with reduced
parasitics. For this paper, the dies were obtained from TriQuint
Semiconductor, Inc., [15].
A. Substrate Material, Stack-Up, and Design Rules
To realize miniaturized high-Q passives, ZEONIF ™ XL
(X-L)–a low-loss organic material–has been employed in
this paper. X-L, developed by Zeon Corp, is a halogen-free
glass–fiber-reinforced polymer laminate. The cross section of
the stack-up is illustrated in Fig. 2. The substrate stack-up
consists of a core layer and a build-up film. To achieve
this stack-up, a 100 μm-thick X-L prepreg (Dk = 6.5,
Df = 0.0035) was laminated onto one side of an X-L copperclad laminate (CCL) core (Dk = 6.2, Df = 0.0031) of
thickness 35 μm.
B. Design of LNA Module and Receiver Module
For this demonstration, two modules were designed, fabricated, and characterized: 1) an LNA module, designed with
only the LNA dies and without the filter– for comparison with
the original package from which the dies were sourced, and
2) a receiver module, designed by integrating the LNA dies
and an embedded BPF–to demonstrate miniaturization with
improved performance over the original LNA package (no
filter).
1) LNA Module Design: The LNA module consisted of
two embedded LNA dies along with RF signal transmission lines and DC power supply rails. The RF transmission
lines were designed for 50 impedance. EM simulation of
the transmission lines was performed using SONNET [16].
The dies were embedded in a cavity formed in the 100 μmthick build-up layer and were connected to landing pads on
metal layer M2 with very short (15 μm height) copper–copper
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Fig. 5.
WLAN receiver module. (a) Schematic cross section and 3-D view. (b) Top view.
Fig. 6.
Simulation flow used for analyzing the receiver module layout.
interconnections using thermo-compression bonding [17].
Since the separation between the active side of the die and
the ground plane (M3) was only 45 μm, the copper on
M3 was etched away under the dies to avoid eddy-current
losses in the on-chip inductors. Metal patches were added to
the power-supply rails on M1 to facilitate surface assembly
of the decoupling capacitors. The LNA module occupied an
area of 2.6 mm × 2.1 mm, as shown in Fig. 3. However, the
coupon for this module was designed bigger to accommodate
additional structures that aid in characterization. The thickness
of this module was 160 μm.
2) Receiver Module Design: The receiver module design
essentially integrated the LNA module with an embedded
band-pass filter. The circuit schematic of the filter was simulated using Agilent ADS [18]. Based on the schematic, the
layout of the filter was designed and optimized using SONNET
EM simulator [16]. To achieve the highest capacitance density,
the capacitors were designed between metal-layers M2–M3
across the thinner dielectric layer. The inductors were designed
as two-layered structures across M2–M3 as well to increase the
mutual inductance. The metal on layer M1 was assigned as the
filter ground plane. To minimize the effect of ground parasitics,
all the capacitors on M2–M3 were designed as stitched capacitors [19]. The filter occupied an area of 1.5 mm × 2.9 mm
and its simulated response is shown in Fig. 4.
For the receiver module design, this BPF was integrated
with the LNA module design, such that the BPF connected
the antenna to the LNA. For the characterization of this
module, the antenna was replaced with a set of RF-probe pads.
Fig. 7.
Top view of the WLAN receiver 3-D model.
The schematic cross section, 3-D view and top-view of the
receiver module layout, is shown in Fig. 5. Its dimensions
were 5.5 mm × 2 mm × 0.16 mm.
III. F ULL WAVE 3-D EM S IMULATIONS
The entire receiver module layout was simulated using
HFSS, a 3-D full-wave EM solver. The simulation flow shown
in Fig. 6 was employed.
The receiver module layout design was imported into HFSS
and set up for simulation. Setting-up the model included
the following: 1) specifying the substrate dimensions and
assigning stack-up materials; 2) creating tapered, conformallymetalized vias similar to the ones in the fabricated sample;
3) defining metal types and thicknesses; and 4) assigning ports.
The metal thickness was set as 10 μm on all the layers. Since
EM models of the dies were not available, the input and output
terminals of the dies were replaced with lumped ports. Further,
to include the effect of the die on the package resonances, a
perfect electric conductor (PEC) sheet was introduced at the
location of the die active surface. To capture any noise coupling from the power supply network to the receiver module
input, a lumped port was located at the DC pads as well. The
simulation was set-up for a driven terminal solution. A frequency sweep from 100 MHz to 20 GHz was defined in steps
SITARAMAN et al.: ULTRAMINIATURIZED WLAN RF RECEIVER MODULE IN THIN ORGANIC SUBSTRATE
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Fig. 8.
Characteristics of output RF signal path.
Fig. 11. Complete package model created in Agilent ADS indicating signal
flow.
Fig. 9.
Coupling from DC pad to RF signal path.
Fig. 12. Complete receiver model simulated using HFSS and Agilent ADS.
Fig. 10.
Agilent ADS set-up to extract the LNA die S-parameters.
of 100 MHz. The top view of the 3-D model in HFSS is shown
in Fig. 7, with the die cavity, the BPF, and the ports indicated.
This model was simulated and its S-parameters were obtained.
The signal loss in the input and output RF paths and the
coupling from the DC pads to the RF signal paths are studied.
The input signal path contains the BPF which has a loss of
1.7 dB, as observed from Fig. 4. The insertion loss of the
output signal path is shown in Fig. 8. It can be seen that
the insertion loss at 2.4 GHz was 0.3 dB and return loss
15 dB. Additionally, the noise coupling from the power supply
network to the signal input and output paths was also obtained,
as shown in Fig. 9. Very low-noise coupling at the input is
critical, since the input signal level is low and any additional
Fig. 13.
Image of the test vehicle mask layout.
interference would lower the signal-to-noise ratio (SNR) at
the input. It can be observed that even the worst-case noise
coupling at the input is as low as −40 dB up to 10 GHz.
Thus the low insertion loss of the signal path and low-noise
coupling inside the package indicate that the noise added by
the package is very low.
Next, to obtain the S-parameter model of the LNA dies,
the set-up shown in Fig. 10 was used. First, the S-parameters
of the package interconnections of the LNA module
(no filter) were obtained through the 3-D EM simulations
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Fig. 14.
IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 4, NO. 8, AUGUST 2014
Fabrication process steps.
Fig. 16. RF receiver module after assembly. (a) Top view. (b) X-ray image.
Fig. 15. Images of (a) substrate prior to assembly. (b) Top view of die cavity.
using HFSS. Following this, the LNA module (no filter) was
fabricated and characterized. Then, the simulated S-parameters
of the package interconnections were de-embedded from the
characterized results of the LNA module. This yielded the
S-parameter model of the LNA dies.
To simulate the complete receiver package along with
the dies, the simulated S-parameter model of the receiver
package, and the de-embedded S-parameter model of the LNA
dies were imported into Agilent ADS, as shown in Fig. 11.
The die model was connected to its corresponding
input–output port locations on the receiver package model.
This set-up was then simulated in Agilent ADS to obtain the
S-parameters of the complete package, as shown in Fig. 12.
IV. FABRICATION , A SSEMBLY, AND C HARACTERIZATION
A. Fabrication
The module layout was panelized and integrated into a testvehicle for fabrication. The top-view image of the test vehicle
layout is shown in Fig. 13.
The fabrication process steps are depicted in Fig. 14.
To achieve a good yield especially for the copper features
with 30 μm spacing, semi additive process was employed for
the metal patterning. The first step of substrate fabrication
was the drilling of through-vias in the XL CCL using laser
ablation to obtain vias of diameter 50 μm. Next, electro-less
plating was performed to metalize the vias with a seed layer
of 1 μm (steps 1–2). This was followed by the photoresist
lamination on the top side and photo-lithography to pattern the
photoresist, such that only the regions where the copper needs
to be retained are exposed (step 3). Subsequently, electrolytic
plating was performed to increase the thickness of the exposed
copper (step 4). Once the thickness of the plated copper was
close to 10 μm, the photoresist was stripped away and the
seed layer removed through microetching (step 5).
Then, the prepreg material was laminated on the top side
of the core (step 6) followed by blind via drilling and metal
patterning through subtractive etching (steps 7–8). Finally,
cavities were formed on the build-up layer for die embedding,
and nicked-gold surface finish was applied to the copper traces
(step 9). An image of the substrate just before assembly is
shown in Fig. 15 along with an image of the top view of the
cavity containing copper traces and die landing pads.
B. Assembly
The ability to perform intermediate testing with chip-last
approach helped to determine the yield of the BPFs through
characterization, prior to die assembly.
SITARAMAN et al.: ULTRAMINIATURIZED WLAN RF RECEIVER MODULE IN THIN ORGANIC SUBSTRATE
Fig. 17.
Cross-section view of the receiver module.
Fig. 18.
Measured response of the LNA module.
Fig. 19.
Measured response of the RF receiver module.
Fig. 20.
The two LNA dies and the decoupling capacitors were
assembled on tested known-good coupons. The top view of
the assembled receiver module and its X-ray image [13] are
shown in Fig. 16. The ground planes on the backside of the
dies were wire-bonded to each other and to the ground islands
on the substrate. Multiple wire-bonds were used to achieve a
low-inductance short between the substrate ground and the
dies’ ground. After assembly, the modules were characterized
using a vector network analyzer (VNA) to study the model-tohardware correlation. A cross section of the fabricated receiver
module is shown in Fig. 17.
C. Characterization
After assembly, the LNA and receiver modules were characterized using the following set-up.
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Comparison of filter response simulation versus measurement.
Fig. 21. Comparison of receiver performance simulation versus measurement.
GSG RF probes: 500 μm pitch.
DC supply: 3.3 V, 14 mA [15].
Two-port VNA.
Short open load thru (SOLT) calibration to isolate the
parasitics of the coaxial cables and probes.
The measured response of the LNA module is shown in
Fig. 18. The peak gain at 2.4 GHz was 14.13 dB with more
than 15 dB return loss. It is noteworthy that the measured
gain of the LNA module is comparable with its datasheet
performance [15], despite the fact that the LNA dies were
designed and optimized for a wire-bond package.
The measured response of the RF-probe design is shown
in Fig. 19. The peak gain of the receiver module was 11 dB,
and the gain at 2.4 GHz was 9.2 dB with more than 25 dB
adjacent band rejection (at 5.2 GHz). The isolation of GSM
1)
2)
3)
4)
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band at 1.9 GHz was 32.35 dB. The shift in peak gain was
attributed to the pass band of the BPF shifting to 2.6 GHz,
reducing the gain of the receiver module at 2.4 GHz.
V. A NALYSIS
A comparison between the performances of the 3-D fullwave EM simulation of the BPF and its measurement is
shown in Fig. 20. A slight drift in the performance toward
the higher frequencies was observed and is attributed to
process variations that potentially cause a reduction in the
capacitor or inductor values. Good correlation between the
complete receiver package simulation and its measurement can
be observed from Fig. 21.
VI. C ONCLUSION
This paper demonstrates a chip-last embedded WLAN
receiver module in a low-loss organic substrate. The LNA
module with dimensions 2.6 mm × 2 mm × 0.16 mm is
more than 3× smaller in volume compared with current
packages [14]. It has a measured peak gain of 14 dB. The
receiver module has a gain of 9 dB at 2.4 GHz. By comparing
the performance of the LNA and the receiver modules, very
good rejection of the adjacent frequency bands is observed in
the receiver module, validating the efficacy of the BPF. The
measured response of the receiver module correlates well with
the results of the 3-D EM simulations. The dimensions of the
receiver module are 5.5 mm × 2 mm × 0.16 mm. Compared
with current wire-bonded LNA packages without a filter [14],
this receiver module, including the filter, is more than 1.5×
smaller in volume. The receiver module thus demonstrated is
the thinnest known RF receiver organic package for WLAN
applications, demonstrated to date.
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[14] BGA622 Datasheet: Silicon Germanium Wide Band Low Noise Amplifier, Infineon, Neubiberg, Germany, 2008.
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Srikrishna Sitaraman received the B.E. degree in
electronics and communications engineering from
Anna University, Chennai, India, in 2010, and the
M.S. degree in electrical and computer engineering
from the Georgia Institute of Technology, Atlanta,
GA, USA, in 2012, where he is currently pursuing
the Ph.D. degree with the 3-D Systems Packaging
Research Center.
He was with Intel Corporation, Phoenix, AZ, USA,
as a Packaging Engineering Intern in 2012. His
current research interests include modeling, design,
and demonstration of ultraminiaturized high-performance wireless LAN radio
frequency packages using 3-D organic and glass substrates.
Yuya Suzuki received the degree from the University of Tokyo, Tokyo, Japan, in 2007, focusing on
polymer solar cell.
He was with Zeon Corporation, Tokyo, where he
was involved in polymer science. He is currently
with the Packaging Research Center, Georgia Institute of Technology, Atlanta, GA, USA, as a Visiting
Engineer. His main interests are polymer synthesis,
polymer processing, and organic–inorganic hybrid
materials. His current research interests include the
development of glass interposer and passive embedded RF module using low-loss polymer material.
Fuhan Liu is an Associate Program Manager of
Multilayer RDL Research with the 3D Systems
Packaging Research Center, Georgia Institute of
Technology, Atlanta, GA, USA. He is currently
involved in the research and development of systemon-a-package integrations, ultrafine pitch redistribution layer low-cost glass interposer and package,
low-cost organic interposer and package, low-cost
low-CTE ultrathin high I/Os chip-embedded fan-out
package, and embedded actives, passives, and optoelectronics integration technologies. He has developed and demonstrated various pioneer and leading edge technologies,
including 1.5–5-um copper circuit traces multilayer RDL on glass, organic,
and silicon packages using low-cost PCB and packaging facilities and
processes, 1–2 metal layer low-CTE (2–4 ppm/0 C) package substrate with
more than 500 I/Os chip assembly with overall package thickness less than
100 um, chip-last embedded IC chip in high-performance organic package for
1–110-GHz multiband applications, high-bandwidth integrated optoelectronics
systems with optical interconnect and high-density electrical interconnect,
and multispectral imaging using CMOS imager with mosaic filter for bio
application. He has been involved in the area for more than 18 years.
SITARAMAN et al.: ULTRAMINIATURIZED WLAN RF RECEIVER MODULE IN THIN ORGANIC SUBSTRATE
Nitesh Kumbhat received the B.Tech. degree in
metallurgical and materials engineering from IIT
Roorkee, Roorkee, India, and the M.S. degree in
materials science and engineering with a specialization in microelectronics packaging from the Georgia
Institute of Technology (Georgia Tech), Atlanta, GA,
USA, in 2003 and 2005, respectively.
He was with Intel, Phoenix, AZ, USA, from 2005
to 2007, as a Package Technology Development
Engineer, where he was involved in cutting-edge
flip-chip mobile chipset package technology development. He was with the Packaging Research Center at Georgia Tech as a
Research Engineer from 2008 to 2012, where he led the interconnections
research. He joined Avago Technologies, Singapore, in 2012, and has been
involved in the area of MEMS packaging. He has experience with substrate
fabrication and chip-embedding technologies, finite element analysis, flip-chip
assembly, and reliability analysis. He has several publications in journals,
conferences, and magazines. His current research interests include interactions
between MEMS devices and packages.
Sung Jin Kim received the B.S. and M.S. degrees
from Kookmin University, Seoul, Korea.
He has over 18 years of experience in the packaging industry as a Researcher, Developer, and
Team Manager with Amkor Technology, Gwangju,
Korea, the Vice President at UTAC Corporation,
Hsinch, Taiwan, the Managing Director at Daeduck
Electronics Company, Ltd., Ansan, Korea, and the
Business Unit Head at Foxconn Advanced Technology, Taipei, China. He built four factories in Asia
from the scratch to full production for packaging,
IC substrate, and embedded technology. He developed and delivered the
world’s first 0.48-mm thickness multichip stacked lead frame package for
NAND flash memory applications in 2004, lead system-in-package (SiP)
development for system miniaturization, and Rmask substrate (no solder mask
type substrate) development for JEDEC L-1 reliability packages in 2003,
and directed board-on-chip package development using liquid elastomer die
attach material with liquid encapsulation for DRAM applications in 2001. He
is the inventor of many international patents for plastic BGA, stacked CSP,
and SiP fields. He is currently with 3D Systems Packaging Research Center,
Georgia Institute of Technology, Atlanta, GA, USA, where he is developing
and commercializing leading-edge research programs with industry partners.
He also teaches packaging courses and mentors graduate students.
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Venky Sundaram received the B.S. degree from IIT
Bombay, Mumbai, India, and the M.S. and Ph.D.
degrees in materials science and engineering from
the Georgia Institute of Technology (Georgia Tech),
Atlanta, GA, USA.
He is the Director of Research and Industry Relations with the 3D Systems Packaging Research Center at Georgia Tech. He is the Program Director
for the Low-Cost Glass Interposer and Packages
industry consortium with more than 25 active global
industry members. He is a globally recognized an
expert in packaging technology and the Co-Founder of Jacket Micro Devices
Inc., Decatur, GA, USA, an RF/wireless startup acquired by AVX. He
holds more than 15 patents and more than 100 publications. His current
research interests include system-on-a-package technology, 3-D packaging and
integration, ultrahigh-density interposers, embedded components, and systems
integration research.
Dr. Sundaram is the Co-Chairman of the IEEE CPMT Technical Committee
on High Density Substrates, and is in the Executive Council of IMAPS as
the Director of Education Programs. He was a recipient of several best paper
awards.
Rao Tummala (F’93) received the B.S. degree from
the Indian Institute of Science, Bangalore, India, and
the Ph.D. degree from the University of Illinois at
Urbana-Champaign, Champaign, IL, USA.
He is a Distinguished and Endowed Chair Professor, and the Founding Director of the National
Science Foundation’s Engineering Research Center
at the Georgia Institute of Technology (Georgia
Tech), Atlanta, GA, USA, where he is involved in
Moore’s law for system integration. Prior to joining
Georgia Tech, he was an IBM Fellow, involved in
the first plasma display and multichip electronics for mainframes and servers.
He has authored about 500 technical papers, holds 74 patents and inventions,
and authored the first modern Microelectronics Packaging Handbook, the first
undergrad textbook Fundamentals of Microsystems Packaging, and the first
book introducing the system-on-package technology.
Prof. Tummala is a member of the National Academy of Engineering and
the Past President of the IEEE Components, Packaging, and Manufacturing
Technology Society and the International Microelectronics and Packaging
Society. He was a recipient of many industry, academic, and professional
society awards, including the Industry Week’s Award for improving U.S.
competitiveness, the IEEE’s David Sarnoff Award, the IMAPS’ Dan Hughes
Award, the Engineering Materials Award from the American Society for
Microbiology, and the Total Excellence in Manufacturing Award from SME.
He was also a recipient of the Distinguished Alumni Awards from the
University of Illinois, the Indian Institute of Science, and Georgia Tech in
2011. He was also a recipient of the Technovisionary Award from the Indian
Semiconductor Association and the IEEE Field Award for contributions in
electronics systems integration, and cross-disciplinary education.