Rose-Hulman Institute of Technology
Electrical and Computer Engineering
ECE 350
Lab Project 5
April 15, 2004
All material is due by 4 pm on Monday 4/26.
NOTE: The OrCad simulations and analysis will be checked at the START of lab.
Objective:
Components:
This project will focus on the use of FET current mirrors to provide the DC biasing for a
Common Source and Common Drain FET amplifier stages.
2N7000 FET
Introduction:
One of the primary differences between discrete and integrated amplifier design is the use
of biasing resistors. This project will examine the use of an FET current mirror to provide the
DC bias for a Common Source and Common Drain amplifier. The actual AC amplifier analysis
and design is the same for both discrete and integrated circuits once the related changes due to
the new biasing network have been incorporated. A discussion of the changes associated with
current biasing will be the focus of this project.
Figure 5 - 1 shows the Common Source Amplifier with the biasing current source in the
source branch. The drain current is equal to the bias current since there is no gate current for the
FET and it is therefore independent of the transistor device related parameters such as VT and K.
This independence removes the need to try and provide a stable bias circuit using gate resistors
in conjunction with a source resistor. The designer is then allowed to adjust RG to improve the
input impedance without having to worry about the relationship between RS and the gate bias
network or the dissipation power associated with very large gate resistors.
The small signal gain for this circuit is:
⎛ RG ⎞
⎟
AV = − gm rds || R D || R L ⎜⎜
' ⎟
+
R
R
⎝ G
I⎠
which shows how RG can be adjusted to improve the coupling of the source signal into the
amplifier and thus increase the overall voltage gain. Note that R'I in the gain equation is the
effective source resistance of R I + 50Ω . Feedback can still be provided by placing a resistor
(RS) in series with the current source by-pass capacitor (CS).
ECE 350 Spring 2004
Lab 5
-2-
A Common Drain amplifier with current source biasing is shown in Figure 5 -2. The
biasing current is again included in the source branch. The drain current and RG can be adjusted
effectively independent of the specific transistor parameters in order to meet design input,
output, and gain specifications. Notice that RS has also been eliminated from the circuit through
the use of current biasing. Again, as in the Common Source amplifier, the voltage gain for the
Common Drain amplifier is a strong function of the value chosen for RG. As seen from the
small signal gain equation:
AV =
⎛ RG ⎞
⎟
gm rds1|| rds 2 || R L ⎜⎜
' ⎟
⎝ RG + R I ⎠
(1 + g
r || rds 2 || R L
m ds1
)
the voltage gain approaches the theoretical limit of 1 for a large range of loads when R G >> R 'I .
The current source impedance and the transistor output impedance are represented by rds1 and
rds2 respectively in the above equation and R'I represents the effective source resistance of
R I + 50Ω .
V DD
R
D
Vout
C2
50 Ω
+
-
RI
Vs
VSS
C1
RG
IBias
VSS
Function
Generator
R in
RL
CS
R out
Figure 5 - 1: Common Source Amplifier with Current Source Biasing
ECE 350 Spring 2004
Lab 5
-3-
VDD
50 Ω
+
-
RI
Vs
Cx
VSS
C1
RG
Vout
C2
RL
IBias
VSS (<0)
Function
Generator
R in
R out
Figure 5 - 2: Common Drain Amplifier with Current Source Biasing
Design:
1.
Design a Common Source amplifier as shown in Figure 5-1 with the following
specifications:
A.
B.
C.
D.
E.
F.
G.
use a 2N7000 MOSFET and a 20 volt DC supply
midband gain VO/VS ≥ 5.0
low cutoff frequency FL between 100 Hz and 200 Hz
input impedance as seen by the source ≥ 20 kΩ
VO symmetric swing ≥ 3.0 volts peak (6 V p - p)
load resistor RL = 5 kΩ
source resistance RI = 50 Ω (this is in addition to the function generator's
internal resistance)
H. FET current mirror to meet bias current specifications. You may assume you
have a ± 20 V supply available.
2.
Determine the value of RS to place in series with the CS shown in Figure 5-1 in order to
provide feedback for the CS amplifier designed in step 1. The new voltage gain should
be approximately 2 while all other specifications remain unchanged.
ECE 350 Spring 2004
Lab 5
-4-
Note:
The MOSFET can be easily damaged by static electricity, so careful handling is important
1.
Find the value of the threshold voltage VT and conductivity parameter K from the digital
curve tracer (remember the relation ID = K[VGS - VT]2 in the saturation region).
2.
Determine the value of rds from the digital curve tracer. The slope of the transistor
ID-VDS curves in the active region is 1/rds.
3.
Construct the CS circuit shown in Figure 5-1. Remember, RI is installed in addition to the
internal 50 Ω resistance of the function generator.
4.
Verify that the specifications have been met by measuring the Q-point, midband voltage
gain, and peak symmetric output voltage swing. Note any distortion in the output signal.
5.
Adjust the output signal to obtain the maximum, non-distorted output voltage swing. Is the
design specification met?
6.
Observe the loading affect by replacing RL first by 500 Ω and then by 25 kΩ. Note any
changes in the output signal and comment on the loading affect.
7.
Use computer control to record and plot the frequency response. Find the corner
frequencies and bandwidth to verify that the specifications have been met.
8.
Measure the input impedance seen by the source [look at the current through RI and the
node voltage on the transistor side of RI] and the output impedance seen by the load
resistor [look at the open circuit voltage and the current through and voltage
across RL]. Verify that the input impedance specification has been met.
9.
Now insert the RS determined in step 2 of the design section in series with the by-pass
capacitor CS to form a series-series feedback configuration. Measure the Q-point and
midband voltage gain. Note any distortion in the output signal.
10.
Repeat steps 4 - 8.
Questions:
1.
Could these circuits be supplied with a current source without using both positive and
negative DC sources? Explain your answer.
2.
Why is the current source bypassed for the CS amplifier?
3.
What value of load resistance results in maximum voltage gain? What load resistance
results in maximum power transfer to the load?
4.
Compare the Lab measurements for each amplifier to the theoretical predictions (such as
those obtained using OrCAD). Note how increasing the feedback in the CS amplifier
affects the gain, bandwidth, and input and output impedances.