Department of Electrical Engineering
The City College of New York
The City University of New York (CUNY)
EE210: Switching Systems
Fall 2015
Instructor:
Prof. YingLi Tian
Email: ytian@ccny.cuny.edu
Tel: (212) 650-7046
TA:
Ms. Yang Xian
Email: xianyang1988@gmail.com
Tel: (212) 650-8917
Time:
Location:
Office Hours:
Monday, Wednesday: 2:00pm – 3:15pm
Shepard Hall, Room 75
Monday, Wednesday 3:20pm – 4:50pm
Room ST632/640 or by appointment
Course description
Analysis and synthesis of combinatorial circuits. Karnaugh maps. Analysis and design of
sequential circuits. Digital computer and industrial applications.
Prerequisite: Math 20200
Credits: 3
Textbook: Introduction to Logic Design by Alan B. Marcovitz (3rd Edition)
ISBN: 978-0-07-319164-5
Textbook Website: http://highered.mcgraw-hill.com/sites/0073191647/
Chapters: Chapters 1, 2, 3, 5, 6, 7, 8
Course materials
Lecture notes, HW, and other course materials will be posted on the web site:
http://www-ee.ccny.cuny.edu/www/web/yltian/EE2210.html
Important announcements and class updates will be sent to the class either via email
and/or the course webpage. Please check both regularly.
Please put "EE2210" in the title of any email correspondences you send with the
instructor and the TA.
Homework
Homework problems from the textbook and instructor will be periodically assigned. You
will be provided solutions to some of the assigned homework problems. You must work
“all” assigned homework problems to do well in this course. On-time homework
(homework will be collected in the class on the due date or email to TA in the same
day before midnight – please keep your email receipt in case the email system has a
problem) exhibits a good-faith effort to work the problem(s). Late homework
submissions (after the midnight of the due day) will receive 0% credit.
Make-up Examinations:
Make-up examinations will only be given to students who miss examinations as a result
of excused absences according to applicable current University policy. The student
should provide the necessary documents. Make-up examinations may be in a different
format from the missed examination.
Grade Policy:
Homework:
Mid Exam:
Final Exam:
40%
25%
35%
A+: 97~100; A: 93~96; A-: 90~92; B+: 87~89; B: 83~86; B-: 80~82; C+: 77~79; C:
73~76; C-: 70~72; D: 60~69; F: under 60
Note: The final exam covers material from the entire semester. The grades are nonnegotiable unless the TA makes mistakes.
Class Attendance:
Attendance of all class lectures is required to assure maximum course performance. You
are responsible for all business conducted within a class.
Cheating:
Cheating will not be allowed or tolerated for HW and exams. Anyone caught cheating
will be dealt with according to applicable University policy. Any HW copied from
textbook solutions or other students (both students) will get 0 credits for that HW.
Tentative Course Schedule
Date
Lecture
#
Topics
Reading
08/31
Course Introduction and Outline
Lecture 1 Number Systems
Chapter 1
1.1
1.2
09/02
Combinational Systems
Lecture 2 Truth Tables
Chapter 2
2.1
09/09
09/10
Switching Algebra,
AND, OR, NOT Gates,
Lecture 3 Algebraic Expressions,
Chapter 2
2.2
Implementation AND, OR,
Lecture 4 NOT Gates, Compliment and
Product of Sums
Chapter 2
2.3
2.4
2.5
Chapter 2
2.6
2.7
09/16
09/21
NAND, NOR and Exclusive OR
Lecture 5 Simplification of Algebraic
Expressions
09/30
Manipulation of Algebraic
Lecture 6 functions and NAND gate
Boolean Algebra
Karnaugh Maps
Karnaugh Maps
Lecture 7 Don’t Cares
10/05
Five and Six Variable Maps
Lecture 8 Multiple Output Problems
10/07
Lecture 9 Review for midterm
09/28
10/14
10/19
Chapter 2
2.8
2.9
3.1
Chapter 3
3.2
3.3
3.4
Chapter 3
3.5
3.6
Lecture
10
HW1
HW2
(HW1 Due)
HW3
(HW2 Due)
HW4
(HW3 Due)
HW4 Due
MIDTERM EXAM
Delay in Combinational Logic
Circuits
Adders, Subtractors,
Comparators
HW
Chapter 5
5.1
10/21
Lecture
11
10/26
Lecture
12
10/28
Lecture
13
Binary Decoders
Chapter 5
5.2
Designing System using Binary
Decoders
Chapter 5
5.2
Encoders and Priority Encoders
Multiplexers and Demultiplexer
Three-State Gates
Gate Arrays, State Tables and
Diagrams
Chapter 5
5.3
5.4
5.5
Chapter 6
6.1
Continue State Tables and
Diagrams, Latches, Introduction
to Flip Flops
Chapter 6
6.1
6.2
Chapter 6
6.3
6.4
11/02
Lecture
14
11/04
Lecture
15
11/09
Lecture
16
Analysis of Sequential Systems
11/11
Lecture
17
11/12
Lecture
18
Designing Sequential Systems
using Flip Flops
Continue Designing Flip Flops,
Synchronous Counters and
Asynchronous Counters
11/16
Lecture
19
Designing Counters using Flip
Flops
11/18
Lecture
20
11/23
Lecture
21
Shift Registers,
ASM Diagrams
Lecture
22
Design Systems Using Counters
11/25
State Table and State Diagrams,
PLDs with Flip Flops
Chapter 6
7.1
HW5
HW5 Due
HW6
HW7
HW6 Due
Chapter 7
7.2
Chapter 7
7.3
HW8
HW7 due
Chapter 7
7.4
8.3
Chapter 8
8.1
8.4
Chapter 8
8.2
HW8 Due
11/30
12/02,
12/07,
12/09
12/15
To
12/23
Lecture
23
No class
Review for final exam
Self-study
FINAL EXAM