5. CMOS Operational Amplifiers
Analog Design for CMOS VLSI Systems
Franco Maloberti
Basic op-amp
The ideal operational amplifier is a voltage controlled
voltage source with infinite gain, infinite input impedance
and zero output impedance.
The op-amp is always used in feedback configuration.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
1
Typical feedback configuration
Z4 Z1 + Z2
Z2
V0 = V2
V1
Z3 + Z4 Z1
Z1
Finite gain effect:
Z4 Z1 + Z2
Z2 Z1 + Z2 V0 = V2
V1 1+
Z1 A0Z1 Z3 + Z4 Z1
The error due to the finite gain is proportional to 1 / A0. This
error must be smaller than the error due to impedance
mismatch.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
2
OTA
If impedances are implemented with capacitors and
switches, after a transient, the load of the op-amp is made
of pure capacitors. The behavior of the circuit does not
depend on the output resistance of the op-amp and stages
with high output resistance (operational transconductance
amplifiers) can be used.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
3
Transient
C1
Vi (0 ) = Vin
C1 + C // C0
+
C
Vo (0 ) = Vi (0 )
C0 + C
+
+
C1 + C
Vi () = Vin
C1 + C(1+ gm r0 )
Vo () = Vi () gm r0
C0
gm
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
4
Performance characteristics
Actual op-amps deviate from the ideal behavior. The
differences are described by the performance
characteristics.
DC differential gain:
It is the open-loop voltage gain measured at DC with a
small differential input signal. Typically Ad = 80 ÷ 100 dB.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
5
Common mode gain:
It is the open-loop voltage gain with a small signal applied
to both the input terminals. Acm = 20 ÷ 40 dB.
Common mode rejection ratio:
It is defined as the ratio between the differential gain and
the common mode gain. Typically CMRR = 40 ÷ 80 dB.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
6
Power supply rejection ratio:
If a small signal is applied in series with the positive (or
negative) power supply, it is transferred to the output with a
given gain Aps+ (or Aps-).
The ratios between differential gain and power supply gains
furnish the two PSRRs.
Typically:
PSRR = 90 dB (DC)
PSRR = 60 dB (1 kHz)
PSRR = 30 dB (100 kHz)
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
7
Input offset voltage:
In real circuits if the two input terminals are set at the same
voltage the output saturates close to VDD or to VSS.
Typically |Vos| = 4 ÷ 6 mV.
Input common mode range:
It is the maximum range of the common-mode input voltage
which do not produce a significant variation of the
differential gain.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
8
Output voltage swing:
It is the swing of the output node without generating a
defined amount of harmonic distortion.
Equivalent input noise:
The noise performances can be described in terms of an
equivalent voltage source at the input of the op-amp.
Typically vn = 40 ÷ 50 nV/Hz at 1 kHz,
in a wide band (1 MHz) it results 10 ÷ 50 V RMS.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
9
Unity gain frequency:
It is the frequency where the open-loop gain is zero. It is
also the -3 dB bandwidth in unity-gain closed loop
conditions. Typically fT = 200 MHz.
Phase margin:
It is the phase shift of the small-signal differential gain
measured at the unity gain frequency. A phase margin
smaller than 60° causes ringing in the output response.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
10
Slew rate:
It is the maximum slope of the output voltage. Usually it is
measured in the buffer configuration. The positive slew rate
can be different from the negative slew rate. Typically SR =
50 ÷ 200 V/s (lower values for micropower operation).
Settling time:
The settling time is the time required to settle the output
within a given range (usually ± 0.1%) of the final value.
Power dissipation:
It depends on speed and bandwidth requirements.
Typically, for 3.3 V supply, it is around 1 mW.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
11
Typical parameters of a 0.25 m OTA
Feature
DC gain
CMRR
Offset
Bandwidth
Slew-rate
Settling time: 1 V, CL = 4 pF
PSRR @ DC
PSRR @ 1 kHz
PSRR @ 100 kHz
Input referred noise (white)
Corner frequency
Supply voltage
Input common mode voltage
Output dynamic range
Power consumption
Silicon area
Analog Design for CMOS VLSI Systems
Franco Maloberti
Value
80
40
4-6
100
3
300
90
60
30
100
1
3.3
1.5
2.2
1
2000
Unit
dB
dB
mV
MHz
V/s
ns
dB
dB
dB
nV/Hz
kHz
V
V
Vpp
mW
m2
5. CMOS Operational Amplifiers
12
Basic architecture
1st gain stage
differential to single-ended converter
2nd gain stage
output stage (to reduce the output impedance)
Key requirements:
absolute stability in unity gain closed-loop conditions
when driving maximum load.
minimum number of gain stages.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
13
Two-stage op-amp
Key design issues:
open-loop differential gain
dc offset
power supply rejection (PSRR)
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
14
Open-loop differential gain:
The gain is obtained by multiplying the gains of the two
stages.
gm1
gm5
Av = A1A2 =
=
(gds2 + gds 4 ) (gds5 + gds6 )
=
2 2µn µp Cox
( n + p )2
W W W L 1 L 5 L B 1
IBias
W W L 6 L 7
At low frequency the gain is inversely proportional to the
bias current.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
15
Common mode dc gain:
Applying the same signal to both inputs the circuit becomes
symmetrical and can be studied considering half circuit.
ACM = ACM1ACM2
g g
ds7
m5
=
2gm1 gds5 + gds6 Av
2gm1gm3
CMRR =
=
ACM gds7 (gds2 + gds 4 )
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
16
Offset:
The offset is composed of two terms:
systematic offset
random offset
The systematic offset can be reduced to zero with a
careful design. A necessary condition to have zero
systematic offset, is that the currents of M5 and M6 are
equal, when the inputs are connected to the same voltage.
Assuming all the transistors in saturation this condition is:
W L)
W L) (W L)
(
(
=I
I
(W L)
(W L) (W L)
1
(W L) (W L) = 2 (W L) (W L)
6
Bias
Bias
B
3
Analog Design for CMOS VLSI Systems
Franco Maloberti
6
7
5
B
3
7
5
5. CMOS Operational Amplifiers
17
The random offset is due to the geometrical mismatching
and process dependent inaccuracies.
When we refer the offset of the second stage at the input
terminal we have to divide it by the gain of the first stage.
Since the two offsets are uncorrelated we have:
2
Vos2
2
Vos = Vos1 + A1 The total offset is dominated by the offset of the input
stage.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
18
We study the effect of a mismatch between M3 and M4:
mirror factor (1 + ) instead of 1.
I
I
Vos1 Vos1 Bias
Bias
gm1
+ gm2
1+ = 2 2 2
2
(
)
Analog Design for CMOS VLSI Systems
Franco Maloberti
Vos1
I1
gm1
5. CMOS Operational Amplifiers
19
MOS:
VGS1 VTh
I1
=
= 150 ÷ 300 mV
gm1
2
(in saturation)
I1
nkT
= nVT =
q
gm1
(in sub-threshold)
BJT:
I1
26 mV
gm1
Assuming = 0.01:
Vos,BJT = 0.26 mV
Vos,MOS = 1.5 ÷ 3 mV
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
20
Power supply rejection:
A signal on the positive bias line determines a modulation
in the reference current, which, in turn, gives an equal
modulation of the currents in M5 and M6, if the condition of
the zero systematic offset is fulfilled.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
21
The spur signal v+n affects the currents of M5 and M6.
in,7
in,6
=
= µCox VGS,MB VTh vn+
W /L
W /L
(
) (
)
6
(
)
7
a) low+ frequency:
W /L
W
/
L
W
/
L
1
1
6
5
7
vo,n,1 = in,tot 2 W / L W / L gds6 + gds7
W / L
B
4
B
(
(
)
)
(
(
)(
)(
)
)
b) high frequency:
vo,n,1 = in,Ref
(W / L)
(W / L)
6
B
Analog Design for CMOS VLSI Systems
Franco Maloberti
1
gm5
5. CMOS Operational Amplifiers
22
Power supply rejection at low frequency
(v )
o,tot
2
gm5 (1 k+ ) gds6 2gm3 rds3 +
vn
=
gds5 + gds6
Analog Design for CMOS VLSI Systems
Franco Maloberti
( )
gm5k gds6 2
2gm3 rds3 vn
+
gds5 + gds6 ( )
2
5. CMOS Operational Amplifiers
23
Effect of external components on PSRR
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
24
Frequency response and
compensation
A two-stage scheme with poles in the same frequency
range needs compensation.
A single pole system is always stable.
Strategy: Approach the single pole performance by
splitting the two poles apart.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
25
Miller capacitance moves p1 at lower frequency.
Shunt feedback moves p2 at higher frequency.
Small signal equivalent circuit for two-stage op-amp.
v1(g1 + sC1) + (v1 v0 )sCc + gm1vin = 0
v0 (g2 + sC2 ) + (v0 v1)sCc + gm2v1 = 0
v0
gm2 sCc
= gm1R1R2
vin
1+ sR1R2gm2Cc + s 2R1R2 C1C2 + (C1 + C2 )Cc
[
Analog Design for CMOS VLSI Systems
Franco Maloberti
]
5. CMOS Operational Amplifiers
26
The circuit has two poles and a zero in the right half plane.
1
p1 R1R2gm2Cc
gm2Cc
p2 C1C2 + (C1 + C2 )Cc
gm2
z=
Cc
since in practice Cc > C1, Cc C2, gm1 > 1/R1, gm2 > 1/R2 it
results:
1
p1 <<
R1C1
gm2
1
p2 >>
R2C2
C2
Assuming p1 as dominant, the unity gain angular frequency
is:
1
gm1
T = p1 A0 gm1gm2R1R2 =
R1R2gm2Cc
Cc
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
27
The locations of the second pole p2 and of the zero with
respect to T are derived by considering:
p2
gm2Cc
=
T
gm1C2
z
gm2
=
T
gm1
Analog Design for CMOS VLSI Systems
Franco Maloberti
for stability > 2 to 4
The phase shift given by the
zero is also negative and
can worsen the phase
margin. It must be located
far from the unity gain
frequency.
5. CMOS Operational Amplifiers
28
if Cc > C2 and gm2 > gm1
The right half-plane worsen the phase margin.
In bipolar technology gm2 >> gm1 because the current in
the second stage is normally higher than the one in the
first stage.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
29
In CMOS technology gm2 gm1 because they are
proportional to the square root of I and W/L; moreover,
the transconductance of the input pair must be high in
order to reduce their thermal noise contribution.
In real situations the obtainable phase margin does not
guarantee stability.
Eliminating the right half-plane zero:
unity gain buffer
zero nulling resistor
unity gain current amplifier
The zero is due to a signal feedforward
to a point that is 180° out of phase.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
30
Solution 1: Eliminate feedforward with source follower
Disadvantages:
Area
Power dissipation
Actually it creates a doublet in the feedback path.
Potentially not stable.
Alternative, a substrate emitter follower may be used.
(The bipolar transistor is smaller and has higher gm.)
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
31
Solution 2: Zero nulling resistor
The zero position is pushed away with a resistance in
series with Cc.
(
)
1+ s Rz 1/ gm2 Cc
v0
A0
vin
s s
1+ 1+ p1 p2 Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
32
The pole locations are close to the original.
The zero is moved depending on Rz.
1
z=
1/ gm2 Rz Cc
(
)
If Rz = 1 / gm2 the zero is moved at infinity
If Rz > 1 / gm2 the zero is located in the left half-plane
Implementation:
1
1
1
=
+
Rz Rn Rp
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
33
W 1
= kn VDD V1 VTh,n
Rn
L n
(
)
W 1
= kp V1 VSS VTh,p
Rp
L p
(
)
Choose (W/L)n and (W/L)p such that:
W W kn = kp L n
L p
and:
W 1
= kn VDD Vss VTh,n VTh,p
Rz
L n
Problem: Supply sensitivity.
Since the swing of the node 1 is A2 less than the output
swing, only one transistor with supply independent bias can
be used.
(
Analog Design for CMOS VLSI Systems
Franco Maloberti
)
5. CMOS Operational Amplifiers
34
Solution 3: Unity gain current amplifier
v1(g1 + sC1) + gm1vin v0sCc = 0
v0 (g2 + sC2 ) + gm2v1 + v0sCc = 0
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
35
Slew rate
For large input signal:
M1, M4 are off so the current IM7 discharges Cc through
M2. Assuming M5 able to drive the current request by Cc,
CL and IM6.
V
IM7
SR =
=
t max
Cc
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
36
M2, M5 are off so the current IM7 mirrored by M4 charges
Cc; CL and Cc are charged by IM6. The smaller of these
two limits will hold:
V+
IM7
V+
IM6
SR+ =
=
SR+ =
=
t max Cc
t
C +C
max
c
L
To have SR+ = SR-, a condition can be:
IM6
IM7
=
Cc Cc + CL
Since T = gm1 / Cc, the SR is
IM7
SR =
T = VGS1 VTh T
gm1
For T = 2 · 40 · 106 rad/s, (VGS1 - VTh) = 300 mV, SR 75.4 V/s.
(
Analog Design for CMOS VLSI Systems
Franco Maloberti
)
5. CMOS Operational Amplifiers
37
Single stage schemes
High gain is get with a cascode scheme.
Telescopic cascode
Mirrored cascode
Folded cascode
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
38
Telescopic cascode
DC gain A0 (gmrds)2
low power consumption
only one high impedance
node: compensated with a
capacitance load (if
necessary)
low output swing
reference of the input close
to the negative supply
two bias lines (VB1, VB2)
5 transistors in series
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
39
Mirrored cascode
optimum input common
mode range
only 4 transistors in series
improved output swing
speed of the mirror
higher power consumption
Voutmax = VB1max + VGS4 - Vsat
VB1max = VDD - Vsat - VGS4
Voutmax = VDD - 2Vsat
Voutmax = VGS7 + Vsat
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
40
Conventional folded cascode
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
41
Modified folded cascode
(improved output swing)
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
42
Two stage amplifier vs. single stage amplifier
Two stages:
Voltage gain less affected by resistive loading
Maximum signal swing
Less bussing of bias lines
Requires an additional capacitor for frequency
compensation
More power consumption
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
43
Single stage:
No need for additional compensation capacitor
Lower power consumption
Better CMRR
Lower signal swing
More bussing of bias lines
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
44
Class AB op-amps
Class AB: a circuit which can have an output current which
is larger than its DC quiescent current.
Two stages amplifier with class AB second stage
M6 and M7 act as a
level shifter
M8 and M9 act as a
class AB push-pull
amplifier
gm8 + gm9
A2 =
gds8 + gds9
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
45
The quiescent current in the output stage is bias voltage
and technological variation dependent.
VDD = VGS8 + VGS6 + VGS9
neglecting the body effect:
VDD = VTh,p + 2VTh,n
2L
2L
2L
+
I6 +
I8 +
I9
kn W 6
kn W 8
kn W 9
VDD VTh,p 2VTh,n
I9 =
2L
I6
kn W 6
2L
2L
+
kn W 9
kn W 8
Typically with VDD = 5 V the numerator is around 1.6 V; if it
is assumed VDD = (5 ± 0.5) V and VTh = ± 200 mV, it
results that the numerator can change from 0.7 V to 2.5 V;
hence, Imin = 0.3 Inom; Imax = 2.5 Inom
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
46
Single stage class AB amplifier (only inverting)
In the input pair M1 and M2
operate as source followers
and drive the common gate
stage M3 and M4.
VB = VTh,n + VTh,p + Vov,n + Vov,p
for Vin = 0
I1 = I2 = IBias
for Vin > 0
Iout = K8,9 I1 - K5,6 I2
K8,9 and K5,6 mirror factors
(assumed equal)
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
47
VB + Vin = VGS2 + VGS 4 = VTh,n + VTh,p
2 W
2 W I2
+
+
kn L L
k
p
2
4
VB Vin = VGS1 + VGS3 = VTh,n + VTh,p
2 W
2 W +
+
I1
kn L L
k
p
3
1
It results:
Iout = K8,9 (I1 - I2) = K8,9 VB Vin
Until I1 or I2 goes to zero, for a
larger Vin, Iout increases
quadratically with Vin.
Small signal gain:
Av = 2 Gm rout
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
48
Gm is the transconductance of the cross coupled input
stage
(
)
gm2 Vin VA = gm4VA
gm2Vin
VA =
gm2 + gm4
Iout
gm2gm4
= gm4VA =
Vin = GmVin
gm2 + gm4
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
49
Fully differential op-amps
The use of fully differential paths in analog signal
processing gives benefits on:
PSRR
dynamic range
clock feedthrough cancellation
Consider an integrator and its fully differential version:
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
50
Noise from the power supply and clock feedthrough are
common mode signals.
The output swing is doubled (Vmax+ - Vmax- = 2 Vmax).
Since the noise is unchanged, the dynamic range
improves by 6 dB.
Single ended to differential and double ended to single
ended converters are necessary
Larger area
More bussing of bias lines
Common mode feedback is necessary
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
51
The SE/DE and DE/SE blocks increase the complexity and
introduce noise. The differential approach is convenient if
the differential processor contains more than 4 stages.
The feedback around the op-amp control the difference of
the input terminal voltages and not their mean value. In turn,
there is no control on the output common mode voltage.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
52
Fully differential two stage OTA
1st stage with gain:
1
gm1
A1 =
2 gds1 + gds 4
Analog Design for CMOS VLSI Systems
Franco Maloberti
two 2nd stages with gain:
gm5
A2 =
gds5 + gds6
5. CMOS Operational Amplifiers
53
Fully differential single stage OTA
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
54
COMMON MODE FEEDBACK
continuous time
sampled data
Continuous-time common mode feedback
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
55
VB is such that M1 and M2 are in the linear region;
(W/L)1 = (W/L)2; M1 and M2 are like the parallel of two
voltage dependent resistances.
W 1 2
I1 = µCox V+ VTh VDS VDS 2
L 1
W 1 2
I2 = µCox V VTh VDS VDS 2
L 2 W 2
1
Iout = I1 + I2 = µCox VB VDS VTh
2
L 3
(
)
(
)
(
)
With a differential signal Iout = cost
With a common mode signal: if positive, Iout increases
if negative, Iout decreases
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
56
Fully differential folded cascode with CMFB
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
57
Fully differential folded cascode with CMFB (2)
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
58
Problems:
dynamic range
linearity
Compensation of the non-linearities of the n-channel and pchannel CMFB cell.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
59
Sampled-data common mode feedback
The common mode feedback operates on slowly variable
signal. It can be implemented at discrete time intervals.
The sampled data feedback is essential for low bias
voltage and low power.
linearity (mean value with
capacitors)
low power consumption
no limitation to the dynamic
range
clock signal necessary
clock feedthrough effect
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
60
Micro-power op-amps
Required in battery operated systems
(portable/wearable equipment: pocket calculators, PDA's, digital
cameras, …; medical equipment: pace makers, hearing aids, …);
Use of MOS transistors in weak inversion;
Low current (< 10 A) low slew rate.
ID
gm =
nVT
gds = ID
B gm1
B
=
Av =
gds6 + gds8 nVT n + p
(
)
high dc gain (Av 60 dB)
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
61
Dynamic biasing of the tail current
Basic idea:
Generate |I1 - I2| and increase the current in the differential
stage by k|I1 - I2|.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
62
Since
ID
gm =
nVT
i1 i2 = gm (vin + vin )
(
i1 i2 = IB + k i1 i2
ID = IB + k i1 i2
)
vin + vin
nVT
The current increase becomes significant when:
vin + vin
k
>1
nVT
Typical performance:
DC gain
95 dB
ft
130 kHz
SR
0.1 V/s
0.5 A
IB
Itot
2.5 A
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
63
Class AB single stage with dynamic biasing
For maximum output swing VBIAS-p and VBIAS-n must be as
close as possible to the supply voltages.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
64
During the slewing the current source of the output
cascodes can be pushed in the linear region, hence loosing
the advantage of the AB operation.
The problem is solved with the dynamic biasing:
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
65
Noise
The noise of an operational amplifier is described with an
input referred voltage source vn.
The spectrum of vn is made of a white term and 1/f term.
vn is due to the contributions, referred to the input, of the
noise generators associated to all the transistors of the
circuit (assumed uncorrelated).
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
66
Consider the input stage of a two stage op-amp.
The output noise voltage is given by:
2
vn,out
2
1
2
2
2
2
2
2
= gm1(vn1 + vn2 ) + gm3 (vn3 + vn 4 ) gds2 + gds 4 [
Analog Design for CMOS VLSI Systems
Franco Maloberti
]
5. CMOS Operational Amplifiers
67
We assume gm1 = gm2; gm3 = gm4 (we assume the noise
source of M5 does not contribute) moreover since usually
W1 = W2; L1 = L2; W3 = W4; L3 = L4; v2n1 = v2n2; v2n3 = v2n4;
if we refer v2n,out to the input, we get:
2
vn,out
2
1
A
2
= vn,in
=
2
vn,out
2
m1
g
(g
ds2
+ gds 4
)
2
2
g
2
m3 2
= 2vn1 + 2 vn3 gm1
The contribution of the active loads is reduced by the
square of the ratio gm3/gm1
It is worth to remember that
W
gm = 2µCox
I
L
Analog Design for CMOS VLSI Systems
Franco Maloberti
8kT
1 1
KF
v =
+
f
3gm 2µCox WL f 2
n
5. CMOS Operational Amplifiers
68
The attenuation by the factor (gm3/gm1)2 gives, for the white
term:
µ
W
/
L
3
gm3
2
2
2
3 =
2v
1+
vn,in,w = 2vn11+
n1
g
µ1 W / L m1 1 and for the 1/f term:
K L2 1
K
2
F1
vn,in,1/
1+ F 3 21 f = 2
µ1CoxW1L1 f KF1L3 (
(
)
)
Where KF1 and KF3 are the flicker noise coefficient for
transistors M1 and M3. The white contribution of the active
load is reduced by choosing (W/L)input >> (W/L)load. The 1/f
noise contribution of the active load is reduced by choosing
Linput < Lload. If the above conditions are satisfied the input
noise is dominated by the input pair.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
69
Cascode scheme:
The noise is contributed by
the input pair and the current
sources of the cascode load.
2
vn,in
2
gm4
2
2 = 2 vn1 + v
n4
gm1 Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
70
Folded cascode scheme:
The noise contributed by the same source as in the
cascode and by the current source M2.
2
2
g
g
2
2
2
2 vn,in
= 2
vn1
+ m2 vn2
+ m5 vn5
gm1 gm1 Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
71
Two stage op-amp: (feedforward + zero nulling comp.)
The noise is modeled with two input referred noise sources:
one at the input of the first stage and the other at the input
of the second stage.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
72
In the low frequency range the noise is dominated by vn1.
In the high frequency range the noise is dominated by vn2.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
73
Frequency response:
The input referred noise generator is transmitted to the
output as a conventional input signal
The feedback network around the op-amp must be taken
into account.
One stage amplifier:
The cutoff frequency is: p1 = -gm/C0
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
74
Power of noise:
We consider only the white term.
Single stage amplifier:
v
2
n0
df
8
= v
= 2 1+ kT
3
1+ s / p1
0
(
2
n
)
0
1
df
gm1 1+ 2fC / g
0
m1
(
)
2
8
kT
= 1+ 3
C0
(
)
Two stage amplifier: we consider only the white term
contributed by the noise source of the second stage
v
2
n2
8 kT
= 2 1+ 3 gm2
(
p2 =
v
)
gm2
C1 + C2
Analog Design for CMOS VLSI Systems
Franco Maloberti
2
n0
=
v
0
+
2
vn0
=
2
n2
df
1+ s / p2
kT
4
1+ C1 + C2
3
(
)
5. CMOS Operational Amplifiers
75
Layout
Rules:
Use poly connections only for voltage signals, never for
currents, because the offset RI 15 mV.
Minimize the line length, especially for lines connecting
high impedance nodes.
Use matched structure (necessary common centroid).
Respect symmetries (even respect power devices).
Only straight-line transistors.
Separate (or shield) the input from the output line, to
avoid feedback.
Shield high impedance nodes to avoid noise injection
from the power supply and the substrate.
Regular shapes and layout oriented design.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
76
Stacked layout:
Csb = Cdb = CjbW (d + 2x j )
Structure A:
1
W
Csb = Cdb = Cjb
(d + 2x j )
2
2
Structure B:
2W
Csb = Cdb = Cjb
(d + 2x j )
3
Capacitances are
further reduced if the
diffusion area is shared
between different
transistors.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
77
Key point: use of equal width transistors
Transistors with arbitrary width are not allowed.
Placement and routing:
If we divide a transistor in
an odd number of parallel
transistors the resulting
stack has the source on
one side and the drain on
the other side.
Analog Design for CMOS VLSI Systems
Franco Maloberti
If we divide a transistor in
an even number of parts
the resulting stack has
source or drain on the two
sides.
5. CMOS Operational Amplifiers
78
Example:
Routing into stacks: use of comb connections or serpentine
connections.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
79
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
80
Example: Fully differential folded cascode.
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
81
Analog Design for CMOS VLSI Systems
Franco Maloberti
5. CMOS Operational Amplifiers
82