Operational Amplifiers
On completion of this chapter you should be able to:
1 Understand the main properties of operational amplifiers.
2 Explain and apply the principles of operation for a number of operational amplifier circuit
configurations.
3 Understand the significance of the various amplifier parameters when applied to practical
circuits.
4 Appreciate the use of operational amplifiers for a number of practical applications.
1 Introduction
Operational amplifiers (more commonly referred to simply as op amps)
were originally designed to perform the mathematical operations
of addition, subtraction, multiplication, division, sign changing,
differentiation and integration in analogue computers and analogue
simulators. Although still used to perform these mathematical functions
they are also widely used in a vast range of other applications.
Op amps are produced in integrated circuit (IC) packages, the circuit
chip being embedded in a plastic case. Connections to the internal
circuitry are made via dual-in-line (DIL) connection pins. The simplest
form is an 8-pin DIL package as illustrated in Fig. 1.
For obvious reasons the internal circuitry is not accessible, so if the
device fails it is simply replaced by a new one. Since these devices
are small and cheap, this replacement technique is both fast and
economically sound.
One of the earliest, and still very widely used, op amp ICs is the
741 op amp, which is produced in an 8-pin DIL package as described.
There are also 14 pin ICs which contain two 741 amplifiers. Since all
op amps behave in a similar manner this chapter will concentrate on
the characteristics and function of the 741 package.
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82
Operational Amplifiers
Fig. 1
Before using an op amp in a practical situation a more detailed
knowledge of the various device parameters is necessary. However,
for the sake of simplicity and to avoid getting bogged down in minute
detail at this stage, these parameters and their practical implications are
dealt with at the end of the chapter.
2 Basic Features of an Op Amp
An op amp is a linear, high gain, directly coupled differential amplifier.
This sounds rather complicated but is not. The term directly coupled
means that it can amplify signals down to 0 Hz, i.e. both a.c. and
d.c. signals. The term differential refers to the fact that it effectively
amplifies the difference in the voltages applied to its two inputs.
The symbol for an op amp is shown in Fig. 2. The minus sign inside
the general triangular symbol indicates the inverting input; the noninverting input being identified by the plus sign. A positive d.c. input to
the inverting input will result in a negative d.c. output, and an a.c. input
will result in a phase inverted output. Using the non-inverting input
results in no polarity reversal for d.c. inputs and no phase inversion for
a.c. signals.
As with any other amplifier, the op amp requires a d.c. supply voltage
in order to function. This is usually a dual Vs, 0 V, Vs supply. In
Vs
V1
V2
V0
Vs
Fig. 2
Operational Amplifiers
Fig. 2 the Vs connections are shown, but in circuit diagrams they are
omitted for the sake of clarity. When using an op amp therefore, don’t
forget to make these connections, otherwise the device will not work!
As with other amplifiers, the 0 V rail forms the common reference
point for both input and output signals.
The ideal characteristics for an op amp and typical actual values for a
741 op amp are listed in Table 1.
Table 1
Characteristic
Ideal
Typical actual value (741)
open-loop voltage gain (A0 )
infinite
200 000 (106 dB)
input resistance
infinite
1 M
output resistance
zero
75 bandwidth
infinite
up to 1 MHz
common mode rejection
ratio (CMMR)
infinite
30 000 (90 dB)
slew rate
infinite
0.5 V/µS
At the moment do not concern yourself with the last three items listed
in the table. The explanation and significance of these will be dealt
with later under practical considerations. At this stage the first three
characteristics are the most important.
Open-loop gain All op amps have a very high open-loop gain. In this
respect the 741 is quite modest since some op amps have an openloop gain up to 30 106 times (150 dB). Due to this it requires a p.d.
between the two inputs of only a few microvolts to cause the amplifier
to saturate, i.e. V0 ⬇ Vs volt (the d.c. supply voltage). Now no
signal amplifier can produce an output voltage that exceeds its d.c.
supply voltage, so any significant voltage applied to the op amp in this
situation will cause the output voltage to be at its saturation value
(in practice this will be slightly lower than Vs). This effect is
illustrated in Fig. 3.
From Fig. 3 it may be seen that the amplifier output will be directly
proportional to the input over only the very small range of inputs
between points X and Y—note that this axis is marked in microvolt.
Any input outside this range will cause saturation and the output voltage
will be meaningless in relation to the actual value of the input. For
this reason, unless the device is to be used for switching purposes, an
op amp is always used as a negative feedback amplifier. This means that
a proportion (or even all) of the input is fed back in opposition to the
input. The effect of negative feedback is that the closed-loop gain (Av)
is greatly reduced and is stabilised, thus allowing a larger range of input
voltages to be applied. In addition, the use of negative feedback has
the benefits of modifying both input and output resistances, increasing
83
84
Operational Amplifiers
V0 (V)
Saturation
Vs
X
(V2 V1) [µV]
O
Y
Vs
Saturation
Fig. 3
the available bandwidth and reducing noise and distortion in the output
signal. The reduction in closed-loop gain is easily compensated for by
using more than one stage of amplification if necessary.
3 The Inverting Amplifier
The circuit diagram of an inverting amplifier is shown in Fig. 4. In this
application the non-inverting input is connected to the 0 V rail, so point
B in the circuit is at 0 V. Now, due to the inherent very high open-loop
gain we have seen that an input of only a few microvolt would cause
saturation. Thus the p.d. between points A and B is virtually zero,
which means that point A is a virtual earth point.
Rf
2
1
R1
A
V1
B
V0
Fig. 4
Using the virtual earth concept we can say that the input voltage V1 is
applied across resistor R1. Due to the very high input resistance of the
amplifier (ideally infinite) negligible current will flow into it, so I1 I2.
Operational Amplifiers
Resistor Rf is the feedback resistor connecting the output back to
the input. Again, since point A is a virtual earth, then V0 is connected
across Rf. The relationship between V0 and V1, and hence the closedloop voltage gain Av of the circuit, can be determined as follows.
I1 V0
V1
amp, and I 2 amp where the minus sign
R1
Rf
indictess inversion
but I1 I 2 , so and
V0
V
1
Rf
R1
Rf
V0
Av V1
R1
(1)
From this equation it may be seen that the closed-loop gain is
dependent only on the ratio of Rf to R1. This means that not only is
the gain figure accurately defined but can also be varied simply by
choosing different values for the two resistors. In practice there are
limitations on the values chosen for the resistors. Since R1 effectively
forms the input resistance of the circuit, too low a value is to be
avoided. The usual minimum value for this is 10 k. Similarly, Rf
should not be too large, otherwise a significant current will flow into
the op amp and then I1 I2. On the other hand Rf should not be too
small either, otherwise it will shunt the load. Typically Rf will be
100 k to 1 M. Using these figures, the normal maximum voltage
gain available will be 100.
Worked Example 1
Q
For the circuit of Fig. 4, the following combinations of resistors and input voltages are applied. For
each case calculate the resulting output.
(a)
(b)
(c)
(d)
(e)
R1 100 k; R1 1 M; V1 0.5 V
R1 100 k; Rf 100 k; V1 6.0 V
R1 100 k; Rf 10 k; V1 12.0 V
R1 10 k; Rf 1 M; V1 0.04 sin t volt
R1 Rf 100 k; V1 2.5 V
A
In each case, V0 V1
(a) V0 0.5 106
5.0 V Ans
1 05
(b) V0 ( 6 ) (c) V0 12 Rf
volt
R1
1 05
6.0 V Ans
1 05
10 4
1.2 V Ans
1 05
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Operational Amplifiers
(d) V0 0.04 sin t (e) V0 2.5 106
4 sin t volt Ans
10 4
1 05
2.5 V Ans
1 05
From this example it can be seen that this configuration performs the
functions of sign changing together with multiplication and division.
It is worth noting at this stage that the inverting mode is used for all
mathematical functions.
4 The Summing Amplifier
Consider the circuit in Fig. 5.
I1 V
V0
V
V1
; I 2 2 ; I 3 3 ; and I f R1
R2
R3
Rf
Summing
Junction
Rf
R1
1
R2
2
3
V1
f
R3
V0
V2
V3
Fig. 5
and from Kirchhoff ’s curent law, If I1 I2 I3
so, V0
V
V
V
1 2 3
Rf
R1 R2
R3
⎛ Rf
⎞
Rf
Rf
V0 ⎜⎜⎜
V1 V2 V3 ⎟⎟⎟
⎜⎝ R1
R2
R3 ⎟⎠
(2)
and if Rf R1 R2 R3 then
V0 (V1 V2 V3 )
i.e. the output is the inverted sum of the input voltages.
(3)
Operational Amplifiers
Worked Example 2
Q
For the summing amplifier of Fig. 5, the following combination of resistors and input voltages is
applied. In each case calculate the resulting output voltage.
(a) R1 R2 R3 Rf 100 k V1 0.25 V; V2 3.0 V; V3 6.0 V
(b) R1 R2 100 k ; R3 Rf 1 M
V1 1.2 V; V2 0.35 V; V3 6.0 V
A
(a) Since all the resistors are of the same value then equation (3) will apply
V0 (V1 V2 V3 ) volt (1.5 (3.0 ) 6.0 )
(7.5 3.0 )
V0 4.5 V An
ns
(b) Using equation (2):
⎛R
⎞
R
R
V0 ⎜⎜⎜ f V1 f V2 f V3 ⎟⎟⎟ volt
⎜⎝ R1
R2
R3 ⎟⎠
⎛ 106
⎞
106
106
⎜⎜ 5 1.2 5 0.35 6 ( 6.0 )⎟⎟⎟
⎟⎠
⎜⎝ 10
10
10
(12 3.5 6 )
V0 9.5 V Ans
From the last example it may be seen that as well as summation, the
circuit can also multiply or divide each input by a specified amount.
5 The Non-inverting Amplifier
The input voltage is now applied to the non-inverting input but the
input resistor R1 and the feedback resistor Rf are connected to the
inverting input as shown in Fig. 6.
V1
Rf
R1
Fig. 6
V0
87
88
Operational Amplifiers
Since zero current is assumed to flow into the op amp itself, and
internally the two input terminals are connected by the internal
resistance of the device, then no p.d. will be developed across this
resistance and so the input voltage V1 will be effectively developed
across R1.
Resistors Rf and R1 form a potential divider between the output
terminal and the 0 V rail, so the p.d. developed across R1 will be the
appropriate proportion of V0, thus
p.d. across R1 R1
V0 V1
R f R1
R1 R f
V0
Av V1
R1
Av 1 Rf
R1
(4)
The main advantage of the non-inverting amplifier is that due to the
feedback arrangement the input impedance of the circuit is very high,
and not just R1 as in the previous cases.
Worked Example 3
Q
The circuit of Fig. 6 has the following combination of inputs and resistors applied. In each case
calculate the resulting output voltage.
(a) Rf 1 M; R1 100 k; V1 0.6 V
(b) Rf 100 k; R1 1 M; V1 1.5 V
(c) Rf 100 k; R1 1 M; V1 5 sin t volt
A
In each case, from equation (4)
⎛
R ⎞
V0 V1 ⎜⎜⎜1 f ⎟⎟⎟
⎜⎝
R1 ⎟⎠
⎛
106 ⎞⎟
⎟ 0.6 11
(a) V0 0.6 ⎜⎜1 ⎜⎝
105 ⎟⎟⎠
V0 6.6 V Ans
⎛
105 ⎞⎟
⎟ 1.5 1.1
(b) V0 1.5 ⎜⎜1 ⎜⎝
106 ⎟⎟⎠
V0 1.65 V Ans
⎛
105 ⎞⎟
⎟ 5 sin t 1.1
(c) V0 5 sin t ⎜⎜1 ⎜⎝
106 ⎟⎟⎠
V0 5.5 sin t volt Ans
Operational Amplifiers
6 The Differential Amplifier
In this mode both of the input terminals have voltages applied to them,
as shown in Fig. 7.
Note that two resistors are marked as R1 and the other pair as R2. This
means that each set needs to be a carefully matched pair (i.e. each pair
having the same value).
R2
2
R1
1
A
B
V1
R1
R2
V2
V0
Fig. 7
The potential at point B, VB Also, I1 I2 where, I1 R2
V2 VA ……………[1]
R1 R2
V V0
V1 VA
and I 2 A
R1
R2
V V0
V1 VA
A
R1
R2
VA V0
V1 VA
0
or,
R1
R2
so,
V
V1
V
V
0 A A 0
R1
R2
R1
R2
⎛1
V
V1
1 ⎞⎟
⎟⎟ 0
0 VA ⎜⎜⎜ ⎜⎝ R1
R1
R2
R2 ⎟⎠
⎛ R R ⎞⎟
V
V1
2⎟
0 VA ⎜⎜⎜ 1
0
⎜⎝ R1 R2 ⎟⎟⎠
R2
R1
and substituting equation [1] for VA we have:
V
V2 R2
R R2
V1
0 1
0
R2
R1 R2
R1 R2
R1
V
V1
V
0 2 0
R1
R2
R1
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Operational Amplifiers
hence,
V0
V
V
V V1
2 1 2
R2
R1 R1
R1
and V0 R2
(V2 V1 ) volt
R1
and if R1 R2 , then V0 V2 V1 volt
i.e. the difference between the two inputs.
Worked Example 4
Q
For the circuit of Fig. 7 the following combination of input voltages and resistors is applied. For each
case calculate the resulting output voltage.
(a) R1 R2 100 k; V1 6.4 V; V2 10.5 V
(b) R1 R2 1 M; V1 2.6 V; V2 4 V
(c) R1 100 k; R2 1 M; V1 4.9 V; V2 3.8 V
A
(a) Since R1 R2, then using equation (6)
V0 (V2 V1 ) volt 10.5 6.4
V0 4.1 V Ans
(b) Again using equation (6)
V0 ((4 ) 2.6 )
V0 6.2 V Ans
(c) Since R1 R2 then equation (5) applies
V0 R2
(V2 V1 ) volt
R1
106
(3.8 4.9 ) 10 (1. 1)
1 05
V0 11 V Ans
Note that if the supply voltage VS 10 V, then the last circuit with those
values would give an invalid result since the amplifier would saturate at an
output voltage just less than 10 V.
7 The Integrator
The circuit arrangement for an op amp integrator is shown in Fig. 8,
where the feedback resistor is replaced by a capacitor.
The value of I1 at any instant, i1 V1
amp....................... [1]
R
(5)
(6)
Operational Amplifiers
i1
i1
C
R
V1
V0
Fig. 8
and this current charges the capacitor
the p.d. across the capacitor V0 volt
the instantaneous charge on the capacitor, q Cv0 coulomb
and since current is rate of change of charge
then i1 dv
dq
d
(Cv0 ) C 0 amp................. [2]
dt
dt
dt
and equating [1] and [2] yields
V
dv0
1
R
dt
dv0
1
V1
dt
CR
1
and, V0 ∫
V1 dt volt
CR
C
(7)
Normally a capacitor will charge exponentially with time, but because
of the virtual earth point at the inverting input, as long as V1 is constant
then I1 will be constant, because it is limited only by R, and is not
dependent on the capacitor p.d. For this reason the capacitor will
charge linearly with time, and if V1 remains connected to the input the
output voltage will eventually saturate. This is illustrated in Fig. 9.
The steepness of the ramp output voltage (i.e. the rate of change
O
t (s)
Saturation
Vs
V0 (V)
Fig. 9
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Operational Amplifiers
of output) depends upon the time constant. Apart from the purely
mathematical function of integration, this production of a linear ramp
voltage is a very useful function that is utilised in a number of practical
applications, as was mentioned in the book Further Electrical and
Electronics Principles, Chapter 8. The principal advantage of using
an op amp as an integrator is that the severe attenuation required for
‘good’ integration produced by a simple CR network can be overcome
by the closed-loop gain of the amplifier. This is achieved by having
CR 1 second, e.g. C 1 µF and R 1 M.
Worked Example 5
Q
The integrator circuit of Fig. 8 has R 100 k; C 4 µF; and Vs 10 V. If the input voltage is
maintained at 0.5 V then
(a) sketch (to scale) the resulting output voltage, and
(b) calculate the time taken for the output voltage to reach 6 V.
A
1
V1 dt volt
CR ∫
1
0.5t 2.5 0.5t
4 106 105
(a) V0 V0 1.25t
and the slope of the ramp V0
t
1.25 V/s, and will be a straight line.
The sketch graph is shown in Fig. 10.
(b) V0 1.25t , so when V0 6 V
6
s
1.25
t 4.8 s Ans
t
2
4
6
0
8
10
t (s)
2
4
Slope 1.25 V/s
6
8
10
V0
Fig. 10
Operational Amplifiers
Worked Example 6
Q
An integrator circuit is shown in Fig. 11. For this circuit determine the output voltage when V1 25
sin (314t) volt.
C
10 µF
R
100 kΩ
V1
V0
Fig. 11
A
V0 6
Vi dt volt
CR ∫
1
105 105
1
( 25 cos 314t )
314
∫ 25 sin (314t )dt
V0 79.6 cos (314t ) mV Ans
8 The Differentiator
For this application the resistor and capacitor of the previous circuit are
transposed as shown in Fig. 12.
i1
i1
C
R
V1
V0
Fig. 12
V
dv
dq
C 1 and i2 0
dt
dt
R
dv1
C
dt
dv
CR 1
dt
dV1
CR
volt
dt
i1 so,
V0
R
V0
or, V0
(8)
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Operational Amplifiers
Thus, provided that V1 is a varying input of some kind then the
resulting output voltage will be the differential of the input. For
example, if v1 Vm sin t volt then,
d
(Vm sin t )
dt
CR Vm cos t
V0 CR
V0 CRVm cos t or CRVm sin (t / 2) volt
Note that the angular frequency, , now becomes a multiplying factor
in the output voltage. This can be a serious disadvantage, and mainly
for this reason the differentiator circuit is very seldom used. The
problem is illustrated in the following example.
Worked Example 7
Q The differentiator circuit of Fig. 12 uses C 1 µF and R 1 M. In addition to the required input
voltage, a noise signal due to mains ‘hum’ also appears at the input. If the input noise signal vn 5 sin
314t mV, determine the resulting noise signal at the output.
A
CR 106 106 1 s
output noise, Von CR
d
(5 sin 314t ) mV
dt
5 314 cos 314t mV
Von 1.57 cos 314t V Ans
Now, this level of noise at the output could have a serious effect on the desired
output signal. Notice that the integrator circuit would in fact reduce the noise
by the factor of 314.
9 The Buffer Amplifier
This configuration is shown in Fig. 13, from which it may be seen that
100% negative feedback is employed. The gain is almost unity, and as
the non-inverting input is used, the output voltage will be the same as
V1
V0 V1
Fig. 13
Operational Amplifiers
the input. If the input voltage varies then the output will follow exactly
the same variations, so this arrangement is also known as a voltage
follower. Due to the feedback employed the input impedance of this
amplifier is extremely high and its output impedance is very low. Its
main usage is therefore as a buffer between a high impedance source
and a low impedance load. These features are shared by the BJT and
FET equivalents, namely the emitter follower and source follower
respectively.
10 Voltage Comparator
As the name suggests this device compares the relative values of the
two voltages applied to its inputs. In this mode the op amp utilises both
inputs, and as there is no feedback from output to input it operates in
its open-loop mode. As was seen in section 2, when in open-loop mode
the gain is extremely large and the output will be at its saturation level
of either Vs or Vs volt, depending upon which input is the greater.
Consider a simple example where a warning light is required to
illuminate when the temperature of a device rises to some critical
value. A possible solution is shown in Fig. 14.
Vs
t°C
RT
VA
R2
Vref
V0
Vs
Warning
lamp
0V
Fig. 14
The resistor RT would be a thermistor. This is a temperature dependent
resistor made from semiconductor material, and as such has a fairly
large negative temperature coefficient of resistance. The thermistor
together with R2 forms a potential divider circuit connected between
the amplifier’s Vs supply rails. At low (safe) temperatures RT R2
so more voltage is dropped across R2 and the potential VA Vref 0 V.
Since Vref is connected to the inverting input, then V0 ⬇ Vs, which is
the reverse bias condition for the diode. As the temperature increases
so the value of RT will decrease and potential VA will increase, and
when the critical temperature is reached VA will just exceed Vref. The
non-inverting input will now be the larger of the two, and the output of
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96
Operational Amplifiers
the amplifier will switch from VS to VS volt. The diode will now
be forward biased and the lamp will light.
11
Digital to Analogue (D/A) and Analogue to
Digital (A/D) Conversion
The ‘real’ world is an analogue one whereby changes take place in
a continuous manner, e.g. linear variations or sinusoidal variations.
Digital systems on the other hand vary only in discrete steps, following
a binary law, whereby variables can take on values of either logic 1
or logic 0 (typically 5 V or 0 V). In addition, humans are used to
dealing with numbers on the denary (decimal) scale, and cannot readily
appreciate values expressed in binary. For these reasons some means
of communicating information between analogue and digital systems
is required. The circuits that achieve this are known as D/A and A/D
converters.
12
D/A Converter
This device utilises the summing op amp as its main component, with
the values of its input resistors being binary weighted, i.e. they increase
in powers of 2. A typical example is illustrated in Fig. 15, where a 4-bit
digital input (a binary number) is converted into an analogue output
(a denary number). For simplicity the switches are shown as mechanical
5 V
V1 (lsb)
8R
Rf (8 k)
(80 k)
1 MΩ
S1
V2
4-bit
binary
input
4R
(40 k)
500 kΩ
S2
V3
2R
(20 k)
S3
V′
V4
(msb)
R
(10 k)
S4
0V
Fig. 15
V0
Operational Amplifiers
devices, but in practice they would take the form of electronic
switches. Thus each of the inputs V1 to V4 may be set to either 0 V or
5 V which represent the digital states of logic 0 (LOW) or logic 1
(HIGH) respectively.
The output of the summing amplifier, V Rf
R
)
(
Rf
8R
V1 Rf
4R
V2 Rf
2R
V3 V4 volt and using the actual values shown in brackets in Fig. 15
V (0.1V1 0.2V2 0.4V3 0.8V4 ) volt
Now, if switches S1 and S4 are moved to the other position, then
V1 V4 5 V and the other two inputs will remain at 0 V. The
digital input therefore represents the value 1001, which is equivalent to
the denary number 9.
V (0.1 5 0 0 0.8 5) volt 4.5V
Now, V
forms the input to an inverting amplifier with a closed-loop
gain of 2, so
V0 (2) ( 4.5) 9 V
It is left to the reader to verify that for any combination of inputs from
0000 to 1111 will result in output voltages from 0 V to 15 V.
13
A/D Converter
This circuit utilises two op amps: one as a voltage comparator and the
other as a D/A converter. Also shown in a logic AND gate, a clock
generator and a binary counter. A brief description of these additional
elements is given, and the complete block diagram of the arrangement
is shown in Fig. l6.
Clock generator This provides a continuous train of rectangular pulses
at a carefully controlled frequency.
AND gate This gate provides a logic 1 (HIGH) output only when both
of its inputs are also in the HIGH state. If either one or both of its
inputs is LOW, then the output will be LOW.
clock
generator
V1
analogue
input
V2
AND
D/A
converter
Fig. 16
binary
counter
4-bit
binary
output
97
Operational Amplifiers
Binary counter This provides a 4-bit digital output which is
incremented by one each time it receives a logic 1 signal from the
clock generator via the AND gate.
The operation of the circuit is as follows. Initially V2 will be 0 V, and
the analogue input voltage V1 will be some constant positive value.
Under these conditions the output of the comparator will be ⬇VS
(HIGH). Each time a positive pulse is produced by the clock generator
the AND gate will be enabled and an output pulse will cause the binary
counter to increment by one. This binary output is fed back to the D/A
converter, which in turn converts this to an analogue voltage V2. This
process continues until V2 equals V1, at which time the comparator
output switches to VS (LOW). The AND gate will now be inhibited
and the binary count will be frozen at a value corresponding to the input
analogue signal. At the end of the counting period provision would be
made to zero the counter. The various waveforms are shown in Fig. 17.
V1
analogue
signals
t
0
Vs
comparator
output
t
0
Vs
AND
gate
output
‘1’
t
‘0’
‘1’
clock
generator
output
t
Fig. 17
0110
0101
0100
0011
0010
binary
output
0001
‘0’
0000
98
Operational Amplifiers
14
Practical Considerations
In the foregoing descriptions of the various op amp configurations it
has been assumed that the amplifier was ideal. However, when using
these devices in practice there are a number of non-ideal parameters
that need to be considered. Where typical values are quoted in the
following descriptions they refer to the 741 op amp.
Input bias current This is the average of the currents flowing into
the input terminals, the typical value being 80 nA.These (very small)
currents will cause corresponding p.d.s across any resistors connected
to the input terminals.
Input offset current This is the difference between the two input
currents when the output voltage is zero, and will typically be 20 nA.
Thus, not only is the practical amplifier non-ideal from the standpoint
that it requires input currents, but it is also non-ideal in that these
currents are unequal, i.e. the two halves of the amplifier internal
circuitry are not exactly symmetrical.
Input offset voltage Ideally, when both inputs are zero (or equal) the
output will be zero. In practice this is not always the case, again due to
asymmetry within the internal circuitry. This effect is nulled by the use
of an external potentiometer. The two ends of this potentiometer are
connected to terminals on the IC package marked ‘offset null’ (pins 1 and
5), and the wiper is connected to the Vs supply (pin 4). With both input
terminals grounded the potentiometer is adjusted until the output is zero.
Slew rate This is a measure of the maximum rate of change of output
voltage that can be attained, a typical value being 0.5 V/µs. The result
is that the output waveform cannot have vertical leading and trailing
edges. The effect is illustrated in Fig. 18, where the ideal output is a
10 V pk-pk, 2 kHz rectangular waveform.
V0
10 V
ideal
actual
0
t (µs)
10 V
40 250
Fig. 18
99
Operational Amplifiers
From this figure it may be appreciated that the higher the frequency
of the signal the more significant will be the distortion of the output
waveform.
Bandwidth From 0 Hz (d.c.) to 10 Hz the open-loop gain remains
constant. At frequencies above this the capacitive effects within the
amplifier cause the gain to fall off at a constant rate of 20 dB/decade
(6 dB/octave), until unity gain occurs at a frequency of 1 MHz.This is
known as the transition frequency, fT, and the graph is shown in Fig. 19.
106
105
104
Av
100
103
102
fT
10
1
10
102
103
104
105
106
f (Hz)
Fig. 19
fT gain bandwidth 1 MHz, and is also referred to as the
gain–bandwidth product. This is a constant for any given amplifier, so
if higher gain is required this can only be achieved at the expense of
bandwidth, and vice versa. If the maximum closed-loop gain is limited
to 100, then the available bandwidth will be given by
fT 106 100 B
so, B 10 kHz
Common-mode rejection ratio (CMMR) Ideally when the same
signal is connected to both inputs simultaneously the output should
be zero. Such an input signal is called a common mode input, and is
usually an unwanted input such as noise, which can be superimposed
on the genuine input. The ability of an amplifier to reject (attenuate) a
common mode input is called the CMMR, and is defined as
⎛ differential voltage gain ⎞⎟
⎟⎟ dB
CMMR 20 log ⎜⎜⎜
⎝ common mode gain ⎟⎠
(9)
Operational Amplifiers
A typical figure for CMMR is 90 dB. Strictly speaking this should
be written as 90 dB since it is a measure of the attenuation of the
common mode input, but in practice the minus sign is omitted.
Summary of Equations
V0 Inverting amplifier:
Rf
R1
V1 volt
⎛ Rf
⎞
Rf
Rf
V0 ⎜⎜⎜
V1 V2 ... Vn ⎟⎟⎟ volt
⎜⎝ R1
R2
Rn ⎟⎠
and if R f R1 R 2 ... Rn , then
V0 (V1 V2 ... Vn ) volt
Summing amplifier:
⎛
R f ⎞⎟
⎟⎟ volt
V0 ⎜⎜⎜1 ⎜⎝
R 1 ⎟⎠
Non-inverting amplifier:
R2
(V2 V1 ) volt
R1
and if R1 R2 , then
V0 Differential amplifier:
V0 (V2 V1 ) volt
Integrator:
V0 Differentiator:
∫ V1 dt volt
V0 CR
Input bias current:
Input offset current:
CMMR:
1
CR
IB dV1
volt
dt
I B1 I B 2
nanoampere
2
IOB I B1 I B 2 nanoampere
⎛ differential voltage gain ⎞⎟
⎟ dB
CMMR 20 log ⎜⎜
⎜⎝ common mode gain ⎟⎟⎠
101
102
Operational Amplifiers
Assignment Questions
1
For the circuit of Fig. 20 the d.c. supply voltage
is 10 V. Determine the output voltage when
the input voltage is (a) 1.5 mV, (b) 30 mV, and
(c) 200 mV.
4
Design and sketch an op amp circuit that will
provide an output of 5 V when an input of
0.25 V is applied to its input.
5
Design an amplifier circuit that will produce
an output that represents the equation
V0 2.5 a 0.5b 10c volt, where a, b, and c
are voltages.
6
For the circuit shown in Fig. 23, the output
voltage is 5.25 V and input V1 6.8 V.
Determine the value of V2.
1 MΩ
10 kΩ
V1
V0
470 kΩ
Fig. 20
15 kΩ
To what value must V1 be set in order to
produce an output of 3.5 V for the circuit
of Fig. 21?
2
15 kΩ
V1
V2
V0
470 kΩ
V1
V0
1 MΩ
Fig. 23
47 kΩ
7
An op amp connected as an inverting
amplifier has an input resistor of 12 k and a
voltage gain of 4.6. Calculate, to the nearest
kilohm, the value of the feedback resistor.
8
The input bias currents of an op amp are
IB1 16 nA and IB2 14 nA. Calculate (a) the
input bias current, and (b) the input offset
current.
9
An op amp integrator is supplied with a
constant input voltage of 0.75 V. The input
and feedback components are R 100 k
and C 10 µF respectively. Calculate (a)
the output voltage 5 s after the input is
connected, and (b) the time taken for the
output to reach 8 V. You may assume that at
the instant of connection the output was zero.
10
An op amp has a common mode gain of 5 and
a CMMR of 100 dB.
Fig. 21
Considering Fig. 22, if V1 9 V; V2 0.2 V;
and V3 1.5 V, then
3
(a) determine the value of V0, and
(b) which of the following values of d.c.
supply voltage would be suitable
(i) 9 V, (ii) 5 V, (iii) 12 V, (iv) 15 V
and justify your answer to part (b)?
200 kΩ
100 kΩ
8.2 kΩ
100 kΩ
V1
V2
V3
Fig. 22
V0
(a) Calculate the differential voltage gain.
(b) If the common mode gain was 4.5 and
the differential voltage gain was 2 105,
calculate the CMMR.
Operational Amplifiers
Suggested Practical Assignments
Note: The connections for the VS d.c. supply to the op amp, and those for the
offset null adjustment have not been shown in the following circuit diagrams.
Do not forget to make these connections according to the data sheet pin-out
diagram for the 741 op amp.
Assignment 1
To investigate the operation of an inverting op amp.
Apparatus:
1 741 op amp
1 dual d.c. power supply
2 voltmeter
1 10 k potentiometer
Method:
1 MΩ
VS
100 kΩ
RV1
10 k
VS
V1
V0
0V
Fig. 24
1
2
3
4
Connect the circuit shown in Fig. 24.
By means of RV1, vary the input V1, in steps, from Vs to Vs volt, and record
the corresponding values of output V0.
Plot a graph of V0 versus Vi over the range of voltages obtained in 2.
For the range of input voltages between 0.5 V, determine the amplifier
closed-loop gain.
Assignment 2
To investigate the operation of a non-inverting op amp.
Apparatus:
1 741 op amp
1 dual d.c. power supply
2 voltmeter
1 10 k potentiometer
Method:
1
2
3
Connect the circuit shown in Fig. 25.
By means of RV1, vary the input voltage, in 0.2 V steps, from 0.8 V to 0.8 V
and tabulate the corresponding values for the output voltage.
From your results determine the amplifier gain.
103
104
Operational Amplifiers
100 kΩ
VS
RV1
10 kΩ
10 kΩ
V1
VS
V0
10 kΩ
0V
Fig. 25
Assignment 3
To investigate the operation of a differential amplifier.
Apparatus:
1 741 op amp
1 dual d.c. power supply
3 voltmeter
2 10 k potentiometer
4 matched 10 k, resistors
Method:
VS
10 kΩ
10 kΩ
RV1
10 k
10 kΩ
RV2
10 k
V0
V1
V2
VS
10 kΩ
0V
Fig. 26
1
2
3
Connect the circuit of Fig. 26.
By means of RV1 and RV2, apply a variety of inputs to the amplifier and
record the corresponding outputs.
Determine whether your results verify that V0 (V2 V1) volt.
Assignment 4
To plot the frequency response curve for a 741 op amp.
Apparatus:
1 741 op amp
1 variable frequency signal generator
1 double-beam oscilloscope
1 100 k resistor
1 10 k resistor
Method:
1
Connect the circuit shown in Fig. 27, and monitor the input and output
terminals with the oscilloscope.
Operational Amplifiers
1 MΩ
R1 1 MΩ
Signal
generator
V1
V0
Fig. 27
2
3
4
5
6
7
Set the output of the signal generator to 5 mV at the lowest possible
frequency.
Keeping the voltage output of the signal generator constant, increase the
frequency in decade steps up to 1 MHz, and tabulate the corresponding
value of output voltage.
From your results, calculate and tabulate the amplifier gain figures.
Replace R1 with a 100 k resistor and repeat 2 to 4.
Replace R1 with a 10 k resistor and repeat 2 to 4.
From the tabulated results plot the three response curves on the same axes.
Assignment 5
To investigate the operation of a D/A converter.
Apparatus:
1 741 op amp
1 voltmeter
1 5 V d.c. supply
resistors to make up values of 20 k, 40 k, 80 k, and 160 k
Method:
1
2
Connect the circuit of Fig. 28.
Connect all four digital inputs to 0 V and using the null offset control adjust
the output to zero.
(msb)
A
10 kΩ
20 kΩ
40 kΩ
B
digital
data
80 kΩ
C
V0
160 kΩ
D
(lsb)
0V
Fig. 28
105
106
Operational Amplifiers
3
Apply the combination of digital data to inputs A to D as specified in
Table 2, and for each combination measure the output.
Table 2
Digital input
4
A
B
C
D
1
0
1
0
Decimal
equivalent
Ideal V0
(V)
10
3.125
1
0
0
0
8
2.500
0
1
0
1
5
1.563
0
1
0
0
4
1.250
0
0
1
0
2
0.625
Actual V0
(V)
Compare the measured output values with the ideal values in Table 2, and
comment on any discrepancies found.
Operational Amplifiers
Answers to Assignment Questions
150 mV
3V
⬇10 V (saturation)
1
(a)
(b)
(c)
2
157 mV
3
(a)
(b)
4
Inverter with gain 20; say Rf 1 M and R1 50 k
5
Summer; if Rf 1 M then use 400 k, 2 M, 100 k for input resistors
6
6.97 V
7
55 k
8
(a)
(b)
15 nA
2 nA
9
(a)
b)
3.75 V
10.67 s
10
(a)
(b)
5 10 5
93 dB
8.516 V
(i), (iii) and (iv)
107