14-Bit, 125 MSPS
Dual TxDAC+® Digital-to-Analog Converter
AD9767
FEATURES
FUNCTIONAL BLOCK DIAGRAM
14-bit dual transmit DAC
125 MSPS update rate
SFDR and IMD: 82 dBc
Gain and offset matching: 0.1%
Fully independent or single resistor gain control
Dual-port or interleaved data
On-chip 1.2 V reference
5 V or 3.3 V operation
Power dissipation: 380 mW @ 5 V
Power-down mode: 50 mW @ 5 V
48-lead LQFP
DVDD
WRT2
ACOM
1
LATCH
PORT1
WRT1
AVDD
DIGITAL
INTERFACE
1
DAC
IOUTA1
IOUTB1
REFERENCE
REFIO
FSADJ1
FSADJ2
GAINCTRL
BIAS
GENERATOR
SLEEP
AD9767
2
LATCH
PORT2
CLK1
MODE
2
DAC
IOUTA2
IOUTB2
CLK2
00620-001
DCOM
Figure 1.
APPLICATIONS
Communications
Base stations
Digital synthesis
Quadrature modulation
GENERAL DESCRIPTION
The AD9767 is a dual-port, high speed, 2-channel, 14-bit
CMOS DAC. It integrates two high quality, 14-bit TxDAC+
cores, a voltage reference and digital interface circuitry into
a small, 48-lead LQFP. The AD9767 offers exceptional ac and
dc performance while supporting update rates up to 125 MSPS.
The AD9767 has been optimized for processing I and Q data in
communications applications. The digital interface consists of
two double-buffered latches as well as control logic. Separate
write inputs allow data to be written to the two DAC ports
independent of one another. Separate clocks control the update
rate of the DACs.
A mode control pin allows the AD9767 to interface to two
separate data ports, or to a single interleaved high speed data
port. In interleaving mode, the input data stream is demuxed
into its original I and Q data and then latched. The I and Q data
is then converted by the two DACs and updated at half the
input data rate.
The GAINCTRL pin allows two modes for setting the full-scale
current (IOUTFS) of the two DACs. IOUTFS for each DAC can be set
independently using two external resistors, or IOUTFS for both DACs
can be set by using a single external resistor. See the Gain Control
Mode section for important date code information on this feature.
The DACs utilize a segmented current source architecture
combined with a proprietary switching technique to reduce glitch
energy and maximize dynamic accuracy. Each DAC provides
differential current output, thus supporting single-ended or
differential applications. Both DACs can be simultaneously updated
and can provide a nominal full-scale current of 20 mA. The full-scale
currents between each DAC are matched to within 0.1%.
The AD9767 is manufactured on an advanced, low cost
CMOS process. It operates from a single supply of 3.3 V to
5.0 V and consumes 380 mW of power.
PRODUCT HIGHLIGHTS
1.
The AD9767 is a member of a pin-compatible family of
dual TxDACs providing 8-bit, 10-bit, 12-bit, and 14-bit
resolution.
2.
Dual 14-Bit, 125 MSPS DACs. A pair of high performance
DACs optimized for low distortion performance provide for
flexible transmission of I and Q information.
3.
Matching. Gain matching is typically 0.1% of full scale, and
offset error is better than 0.02%.
4.
Low Power. Complete CMOS dual DAC function operates
on 380 mW from a 3.3 V to 5.0 V single supply. The DAC
full-scale current can be reduced for lower power
operation, and a sleep mode is provided for low power idle
periods.
5.
On-Chip Voltage Reference. The AD9767 includes a 1.20 V
temperature-compensated band gap voltage reference.
6.
Dual 14-Bit Inputs. The AD9767 features a flexible dual-port
interface, allowing dual or interleaved input data.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD9767
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog Outputs .......................................................................... 14
Applications....................................................................................... 1
Digital Inputs .............................................................................. 14
General Description ......................................................................... 1
DAC Timing................................................................................ 15
Functional Block Diagram .............................................................. 1
Input Clock and Data Timing Relationship ........................... 16
Product Highlights ........................................................................... 1
Sleep Mode Operation............................................................... 17
Revision History ............................................................................... 2
Power Dissipation....................................................................... 17
Specifications..................................................................................... 3
Applying the AD9767 .................................................................... 18
DC Specifications ......................................................................... 3
Output Configurations .............................................................. 18
Dynamic Specifications ............................................................... 4
Differential Coupling Using a Transformer............................ 18
Digital Specifications ................................................................... 5
Differential Coupling Using an Op Amp................................ 18
Absolute Maximum Ratings............................................................ 6
Single-Ended, Unbuffered Voltage Output............................. 19
Thermal Resistance ...................................................................... 6
Single-Ended, Buffered Voltage Output Configuration........ 19
ESD Caution.................................................................................. 6
Power and Grounding Considerations, Power-Supply
Rejection...................................................................................... 19
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 11
Theory of Operation ...................................................................... 12
Functional Description.............................................................. 12
Reference Operation .................................................................. 13
Gain Control Mode .................................................................... 13
Reference Control Amplifier .................................................... 13
Applications..................................................................................... 21
VDSL Applications Using the AD9767 ................................... 21
CDMA ......................................................................................... 21
Evaluation Board ............................................................................ 22
General Description................................................................... 22
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
DAC Transfer Function ............................................................. 13
REVISION HISTORY
10/06—Rev. B to Rev. C
Updated Format..................................................................Universal
Changes to Figure 2.......................................................................... 5
Changes to Figure 3.......................................................................... 7
Changes to Functional Description Section ............................... 12
Changes to Figure 25 and Figure 26............................................. 15
Changes to Figure 28 and Figure 29............................................. 16
Changes to Power Dissipation Section ........................................ 18
Changes to Figure 39...................................................................... 19
Changes to Power and Grounding Considerations Section ..... 19
Changes to Figure 45...................................................................... 22
Changes to Figure 47...................................................................... 24
Updated Outline Dimensions....................................................... 28
Changes to Ordering Guide .......................................................... 28
2/00—Rev. A to Rev. B
12/99—Rev. 0 to Rev. A
8/99—Revision 0: Initial Version
Rev. C | Page 2 of 28
AD9767
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD = 3.3 V or 5 V, IOUTFS = 20 mA, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
DC ACCURACY 1
Integral Linearity Error (INL)
TA = 25°C
TMIN to TMAX
Differential Nonlinearity (DNL)
TA = 25°C
TMIN to TMAX
ANALOG OUTPUT
Offset Error
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Gain Match
Full-Scale Output Current 2
Output Compliance Range
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current 3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
Small Signal Bandwidth
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
POWER SUPPLY
Supply Voltages
AVDD
DVDD
Analog Supply Current (IAVDD)
Digital Supply Current (IDVDD) 4
Digital Supply Current (IDVDD) 5
Supply Current Sleep Mode (IAVDD)
Power Dissipation4 (5 V, IOUTFS = 20 mA)
Power Dissipation5 (5 V, IOUTFS = 20 mA)
Power Dissipation 6 (5 V, IOUTFS = 20 mA)
Power Supply Rejection Ratio 7 —AVDD
Power Supply Rejection Ratio7—DVDD
OPERATING RANGE
Min
14
Typ
Max
Unit
Bits
−3.5
−4.0
±1.5
+3.5
+4.0
LSB
LSB
−2.5
−3.0
±1.0
+2.5
+3.0
LSB
LSB
+0.02
+2
+5
+1.6
+0.14
20.0
+1.25
% of FSR
% of FSR
% of FSR
% of FSR
dB
mA
V
kΩ
pF
1.26
V
nA
1.25
1
0.5
V
MΩ
MHz
0
±50
± 100
±50
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
−0.02
−2
−5
−1.6
−0.14
2.0
–1.0
±0.25
±1
±0.1
100
5
1.14
1.20
100
0.1
3
2.7
5
5
71
5
8
380
5.5
5.5
75
7
15
12
410
420
450
mW
−0.4
−0.025
+0.4
+0.025
mW
% of FSR/V
% of FSR/V
−40
+85
°C
450
1
Measured at IOUTA, driving a virtual ground.
Nominal full-scale current, IOUTFS, is 32 times the IREF current.
3
An external buffer amplifier with input bias current use of <100 nA should drive any external load.
4
Measured at fCLK = 25 MSPS and fOUT = 1.0 MHz.
5
Measured at fCLK = 100 MSPS and fOUT = 1 MHz.
6
Measured as unbuffered voltage output with IOUTFS = 20 mA and 50 Ω RLOAD at IOUTA and IOUTB, fCLK = 100 MSPS and fOUT = 40 MHz.
7
±10% power-supply variation.
2
B
Rev. C | Page 3 of 28
V
V
mA
mA
mA
mA
mW
AD9767
DYNAMIC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD = 3.3 V or 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly
terminated, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fCLK)
Output Settling Time (tST) (to 0.1%) 1
Output Propagation Delay (tPD)
Glitch Impulse
Output Rise Time (10% to 90%)1
Output Fall Time (90% to 10%)1
Output Noise (IOUTFS = 20 mA)
Output Noise (IOUTFS = 2 mA)
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
fCLK = 100 MSPS; fOUT = 1.00 MHz
0 dBFS Output
−6 dBFS Output
−12 dBFS Output
−18 dBFS Output
fCLK = 65 MSPS; fOUT = 1.00 MHz
fCLK = 65 MSPS; fOUT = 2.51 MHz
fCLK = 65 MSPS; fOUT = 5.02 MHz
fCLK = 65 MSPS; fOUT = 14.02 MHz
fCLK = 65 MSPS; fOUT = 25 MHz
fCLK = 125 MSPS; fOUT = 25 MHz
fCLK = 125 MSPS; fOUT = 40 MHz
Spurious-Free Dynamic Range Within a Window
fCLK = 100 MSPS; fOUT = 1.00 MHz; 2 MHz Span
fCLK = 50 MSPS; fOUT = 5.02 MHz; 10 MHz Span
fCLK = 65 MSPS; fOUT = 5.03 MHz; 10 MHz Span
fCLK = 125 MSPS; fOUT = 5.04 MHz; 10 MHz Span
Total Harmonic Distortion
fCLK = 100 MSPS; fOUT = 1.00 MHz
fCLK = 50 MSPS; fOUT = 2.00 MHz
fCLK = 125 MSPS; fOUT = 4.00 MHz
fCLK = 125 MSPS; fOUT = 10.00 MHz
Multitone Power Ratio (Eight Tones at 110 kHz Spacing)
fCLK = 65 MSPS; fOUT = 2.00 MHz to 2.99 MHz
0 dBFS Output
–6 dBFS Output
–12 dBFS Output
–18 dBFS Output
Channel Isolation
fCLK = 125 MSPS; fOUT = 10 MHz
fCLK = 125 MSPS; fOUT = 40 MHz
1
Min
Typ
Max
125
35
1
5
2.5
2.5
50
30
MSPS
ns
ns
pV-s
ns
ns
pA/√Hz
pA/√Hz
71
82
77
73
70
82
80
79
70
55
67
70
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
82
91
88
88
88
dBc
dBc
dBc
dBc
−81
−79
−83
−80
Measured single-ended into 50 Ω load.
Rev. C | Page 4 of 28
Unit
−71
dBc
dBc
dBc
dBc
80
79
78
76
dBc
dBc
dBc
dBc
85
77
dBc
dBc
AD9767
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD = 3.3 V or 5 V, IOUTFS = 20 mA, unless otherwise noted.
Table 3.
Parameter
DIGITAL INPUTS
Logic 1 Voltage @ DVDD = 5 V
Logic 1 @ DVDD = 3.3 V
Logic 0 Voltage @ DVDD = 5 V
Logic 0 @ DVDD = 3.3 V
Logic 1 Current
Logic 0 Current
Input Capacitance
Input Setup Time (tS)
Input Hold Time (tH)
Latch Pulse Width (tLPW, tCPW)
Min
Typ
3.5
2.1
5
3
0
Max
1.3
0.9
+10
+10
0
−10
−10
5
2.0
1.5
3.5
Timing Diagram
tS
tH
DATA IN
(WRT2) (WRT1/IQWRT)
tLPW
(CLK2) (CLK1/IQCLK)
IOUTA
OR
IOUTB
tPD
Figure 2. Timing Diagram for Dual and Interleaved Modes
Rev. C | Page 5 of 28
00620-002
tCPW
Unit
V
V
V
V
μA
μA
pF
ns
ns
ns
AD9767
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
AVDD
DVDD
ACOM
AVDD
MODE, CLK1, CLK2,
WRT1, WRT2
Digital Inputs
IOUTA1/IOUTA2, IOUTB1/IOUTB2
REFIO, FSADJ1,
FSADJ2
GAINCTRL, SLEEP
Junction Temperature
Storage Temperature
Range
Lead Temperature
(10 sec)
With
Respect
to
ACOM
DCOM
DCOM
DVDD
DCOM
Rating
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +3 V
−6.5 V to +6.5 V
−0.3 V to DVDD + 0.3 V
DCOM
ACOM
ACOM
−0.3 V to DVDD + 0.3 V
−1.0 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
ACOM
−0.3 V to AVDD + 0.3 V
150°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5. Thermal Resistance
Package Type
48-lead LQFP
300°C
ESD CAUTION
Rev. C | Page 6 of 28
θJA
91
Unit
°C/W
AD9767
48 47 46 45 44 43 42
SLEEP
ACOM
IOUTA2
IOUTB2
FSADJ2
GAINCTRL
REFIO
FSADJ1
IOUTB1
IOUTA1
AVDD
MODE
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
41 40 39 38 37
DB13P1 (MSB) 1
36
DB0P2 (LSB)
35
DB1P2
DB11P1 3
34
DB2P2
DB10P1
4
33
DB3P2
DB9P1
5
32
DB4P2
DB8P1
6
31
DB5P2
DB7P1
7
30
DB6P2
DB6P1
8
29
DB7P2
DB5P1 9
28
DB8P2
DB4P1 10
27
DB9P2
DB3P1 11
26
DB10P2
DB2P1 12
25
DB11P2
DB12P1
PIN 1
2
AD9767
TOP VIEW
(Not to Scale)
00620-003
DB12P2
DB13P2 (MSB)
DVDD2
DCOM2
WRT2/IQSEL
CLK2/IQRESET
CLK1/IQCLK
WRT1/IQWRT
DVDD1
DCOM1
DB1P1
DB0P1 (LSB)
13 14 15 16 17 18 19 20 21 22 23 24
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1 to 14
15, 21
16, 22
17
18
19
20
23 to 36
37
38
39, 40
41
42
43
44
45, 46
47
48
Name
PORT1
DCOM1, DCOM2
DVDD1, DVDD2
WRT1/IQWRT
CLK1/IQCLK
CLK2/IQRESET
WRT2/IQSEL
PORT2
SLEEP
ACOM
IOUTA2, IOUTB2
FSADJ2
GAINCTRL
REFIO
FSADJ1
IOUTB1, IOUTA1
AVDD
MODE
Description
Data Bit DB13P1 to Data Bit DB0P1.
Digital Common.
Digital Supply Voltage.
Input Write Signal for PORT 1. IQWRT in interleaving mode.
Clock Input for DAC1. IQCLK in interleaving mode.
Clock Input for DAC2. IQRESET in interleaving mode.
Input Write Signal for PORT 2. IQSEL in Interleaving Mode.
Data Bit DB13P2 to Data Bit DB0P2.
Power-Down Control Input.
Analog Common.
PORT 2 Differential DAC Current Outputs.
Full-Scale Current Output Adjust for DAC2.
Gain Control Mode. 0 = 2 resistor, 1 = 1 resistor.
Reference Input/Output.
Full-Scale Current Output Adjust for DAC1.
PORT 1 Differential DAC Current Outputs.
Analog Supply Voltage.
Mode Select. 1 = dual port, 0 = interleaved.
Rev. C | Page 7 of 28
AD9767
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 3.3 V or 5 V, DVDD = 3.3 V or 5 V, IOUTFS = 20 mA, 50 Ω doubly terminated load, differential output, TA = 25°C, SFDR up to
Nyquist, unless otherwise noted.
90
85
5MSPS
80
25MSPS
125MSPS
70
–6dBFS
70
–12dBFS
65
60
60
fOUT (MHz)
50
0
5
10
15
20
25
30
35
60
70
30
35
fOUT (MHz)
Figure 4. SFDR vs. fOUT @ 0 dBFS
00620-008
100
00620-009
10
00620-005
1
00620-010
55
65MSPS
50
0dBFS
75
SFDR (dBc)
SFDR (dBc)
80
Figure 7. SFDR vs. fOUT @ 65 MSPS
90
85
80
0dBFS
0dBFS
75
SFDR (dBc)
SFDR (dBc)
85
–6dBFS
–12dBFS
70
–6dBFS
–12dBFS
65
80
60
55
0
0.5
1.0
1.5
2.0
2.5
fOUT (MHz)
50
00620-006
75
0
10
20
30
40
50
fOUT (MHz)
Figure 5. SFDR vs. fOUT @ 5 MSPS
Figure 8. SFDR vs. fOUT @ 125 MSPS
90
90
0dBFS
85
85
IOUTFS = 5mA
80
–12dBFS
SFDR (dBc)
75
70
–6dBFS
60
75
IOUTFS = 10mA
70
65
60
IOUTFS = 20mA
65
55
0
2
4
6
8
fOUT (MHz)
10
12
00620-007
SFDR (dBc)
80
Figure 6. SFDR vs. fOUT @ 25 MSPS
50
0
5
10
15
20
25
fOUT (MHz)
Figure 9. SFDR vs. fOUT and IOUTFS @ 65 MSPS and 0 dBFS
Rev. C | Page 8 of 28
AD9767
90
75
910kHz/10MSPS
85
2.27MHz/25MSPS
70
IOUTFS = 20mA
SINAD (dBc)
SFDR (dBc)
80
75
IOUTFS = 10mA
65
IOUTFS = 5mA
70
60
11.37MHz/125MSPS
65
–15
–10
–5
0
AOUT (dBFS)
55
20
00620-011
60
–20
40
60
80
100
120
140
fCLK (MSPS)
Figure 10. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/11
00620-014
5.91MHz/65MSPS
Figure 13. SINAD vs. fCLK and IOUTFS @ fOUT = 5 MHz and 0 dBFS
90
2.5
1MHz/5MSPS
85
2.0
2MHz/10MSPS
1.5
75
1.0
INL (LSB)
SFDR (dBc)
80
5MHz/25MSPS
70
65
0.5
0
13MHz/65MSPS
60
–0.5
25MHz/125MSPS
55
–15
–10
–5
0
AOUT (dBFS)
–1.5
00620-012
50
–20
0
4000
12000
16000
CODE
Figure 14. Typical INL
Figure 11. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/5
0.4
85
0.965MHz/1.035MHz@7MSPS
80
8000
00620-015
–1.0
0.2
3.38MHz/3.63MHz@25MSPS
0
75
DNL (LSB)
65
16.9MHz/18.1MHz@125MSPS
–0.4
–0.6
–0.8
60
6.75MHz/7.25MHz@65MSPS
–1.0
55
–1.2
–20
–15
–10
–5
AOUT (dBFS)
0
–1.4
0
200
400
600
CODE
Figure 15. Typical DNL
Figure 12. Dual-Tone SFDR vs. AOUT @ fOUT = fCLK/7
Rev. C | Page 9 of 28
800
1000
00620-016
50
–25
00620-013
SFDR (dBc)
–0.2
70
AD9767
85
0
fOUT = 1MHz
–10
80
fOUT = 10MHz
–20
–30
70
SFDR (dBm)
fOUT = 25MHz
65
fOUT = 40MHz
60
–40
–50
–60
55
–70
fOUT = 60MHz
50
–80
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
–90
00620-017
45
–60
0
10
20
30
40
FREQUENCY (MHz)
Figure 16. SFDR vs. Temperature @ 125 MSPS, 0 dBFS
00620-020
SFDR (dBc)
75
Figure 19. Dual-Tone SFDR @ fCLK = 125 MSPS
0.05
0
1.0
0.03
–20
0.5
GAIN ERROR
0
0
–0.03
–30
SFDR (dBm)
OFFSET ERROR
GAIN ERROR (%FS)
OFFSET ERROR (%FS)
–10
–40
–50
–60
–0.5
–70
–20
0
20
40
60
80
–1.0
TEMPERATURE (°C)
Figure 17. Reference Voltage Drift vs. Temperature
0
–10
–30
–40
–50
–60
–70
–80
10
20
30
FREQUENCY (MHz)
40
00620-019
SFDR (dBm)
–20
0
0
10
20
30
FREQUENCY (MHz)
Figure 20. Four-Tone SFDR @ fCLK = 125 MSPS
10
–90
–90
Figure 18. Single-Tone SFDR @ fCLK = 125 MSPS
Rev. C | Page 10 of 28
40
00620-021
–0.05
–40
00620-018
–80
AD9767
TERMINOLOGY
Linearity Error or Integral Nonlinearity (INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by
a straight line drawn from zero to full scale.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized to
full scale, and associated with a 1 LSB change in digital input code.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all 0. For IOUTB, 0 mA output is expected when all
inputs are set to 1.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per °C. For reference drift, the drift is reported in
ppm per °C (ppm/°C).
Power Supply Rejection (PSR)
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling Time
The time required for the output to reach and remain within
a specified error band about its final value, measured from the
start of the output transition.
B
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1 minus the output when all inputs are set to 0.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits can
cause either output stage saturation or breakdown resulting in
nonlinear performance.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse, which
is specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the output signal and the peak spurious signal over the specified
bandwidth.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).
Rev. C | Page 11 of 28
AD9767
THEORY OF OPERATION
5V
CLK1/IQCLK CLK2/IQRESET
AVDD
RSET1
2kΩ
REFIO
0.1µF
FSADJ2
RSET 2
2kΩ
PMOS
CURRENT
SOURCE
ARRAY
AD9767
GAINCTRL
WRT1/
IQWRT
DVDD
DCOM
RETIMED CLOCK OUTPUT*
IOUTA1
SEGMENTED
LSB
IOUTB1
SWITCHES FOR SWITCH
DAC1
DAC 1
LATCH
PMOS
CURRENT
SOURCE
ARRAY
1.2V REF
MINI
CIRCUITS
T1-1T
CLK
DIVIDER
50Ω
IOUTA2
SEGMENTED
LSB
SWITCHES FOR
SWITCH IOUTB2
DAC2
DAC 2
LATCH
TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
50Ω
MODE
MULTIPLEXING LOGIC
CHANNEL 1 LATCH
CHANNEL 2 LATCH
DB0 TO DB13
DB0 TO DB13
50Ω
5V
DVDD
ACOM DCOM
WRT2/
IQSEL
DIGITAL
DATA
LECROY 9210
PULSE
GENERATOR
*AWG2021 CLOCK RETIMED SUCH THAT
DIGITAL DATA TRANSITIONS ON FALLING
EDGE OF 50% DUTY CYCLE CLOCK.
TEKTRONIX
AWG-2021
w/OPTION 4
00620-004
FSADJ1
SLEEP
Figure 21. Basic AC Characterization Test Setup for AD9767, Testing Port 1 in Dual-Port Mode, Using Independent GAINCTRL Resistors on FSADJ1 and FSADJ2
5V
CLK1/IQCLK
CLK2/IQRESET
AVDD
IREF 1
0.1µF
RSET 2
2kΩ
FSADJ1
REFIO
FSADJ2
IREF 2
1.2V REF
PMOS
CURRENT
SOURCE
ARRAY
PMOS
CURRENT
SOURCE
ARRAY
AD9767
SLEEP
ACOM
CLK
DIVIDER
WRT1/
IQWRT
VOUT1A
IOUTA1
SEGMENTED
LSB
SWITCHES FOR
I
SWITCH OUTB1
DAC1
DAC 1
LATCH
DAC 2
LATCH
IOUTA2
SEGMENTED
LSB
SWITCHES FOR
I
SWITCH OUTB2
DAC2
VOUT1B
VOUT2A
VOUT2B
RL2B
50Ω
MODE
MULTIPLEXING LOGIC
CHANNEL 1 LATCH
GAINCTRL
VDIFF = VOUTA – VOUTB
DVDD
CHANNEL 2 LATCH
DB0 TO DB13
DB0 TO DB13
DIGITAL DATA INPUTS
RL1B
50Ω
RL1A
50Ω
RL2A
50Ω
5V
DCOM
WRT2/
IQSEL
00620-022
RSET 1
2kΩ
Figure 22. Simplified Block Diagram
FUNCTIONAL DESCRIPTION
Figure 22 shows a simplified block diagram of the AD9767.
The AD9767 consists of two DACs, each with its own independent
digital control logic and full-scale output current control. Each
DAC contains a PMOS current source array capable of providing
up to 20 mA of full-scale current (IOUTFS).
All of these current sources are switched to one or the other of
the two output nodes (IOUTA or IOUTB) via PMOS differential
current switches. The switches are based on a new architecture
that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching complementary drive signals to the inputs of the
differential current switches.
The array is divided into 31 equal currents that make up the five
most significant bits (MSBs). The next four bits, or middle bits,
consist of 15 equal current sources whose value is 1/16th of an
MSB current source. The remaining LSB is a binary weighted
fraction of the middle bit current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances the dynamic performance for multitone or low
amplitude signals and helps maintain the DAC high output
impedance (that is, >100 kΩ).
The analog and digital sections of the AD9767 have separate
power supply inputs (AVDD and DVDD) that can operate
independently at 3.3 V or 5.0 V. The digital section, capable of
operating up to a 125 MSPS clock rate and consists of edge
triggered latches and segment decoding logic circuitry. The
analog section includes the PMOS current sources, the
associated differential switches, a 1.20 V band gap voltage
reference, and two reference control amplifiers.
B
Rev. C | Page 12 of 28
AD9767
The full-scale output current of each DAC is regulated by
separate reference control amplifiers and can be set from 2 mA
to 20 mA via an external resistor (RSET), connected to the full
scale adjust (FSADJ) pin. The external resistor, in combination
with both the reference control amplifier and voltage reference
(VREFIO), sets the reference current (IREF), which is replicated to
the segmented current sources with the proper scaling factor.
The full-scale current (IOUTFS) is 32 × IREF.
When GAINCTRL is low (that is, connected to AGND), the
independent channel gain control mode, using two resistors, is
enabled. In this mode, individual RSET resistors are connected to
FSADJ1 and FSADJ2. When GAINCTRL is high (that is,
connected to AVDD), the master/slave channel gain control
mode, using one resistor, is enabled. In this mode, a single RSET
resistor is connected to FSADJ1, and the resistor on FSADJ2
must be removed.
REFERENCE OPERATION
Note that only parts with a date code of 9930 or later have the
master/slave gain control function. For parts with a date code
before 9930, Pin 42 is connected to AGND, and the part
operates in the two-resistor, independent gain control mode.
The AD9767 contains an internal 1.20 V band gap reference.
This can easily be overridden by an external reference with no
effect on performance. REFIO serves as either an input or
output, depending on whether an internal or external reference is
used. To use the internal reference, simply decouple the REFIO pin
to ACOM with a 0.1 μF capacitor. The internal reference voltage is
present at REFIO. If the voltage at REFIO is used elsewhere in the
circuit, an external buffer amplifier with an input bias current of
less than 100 nA is used. An example of the use of the internal
reference is shown in Figure 23.
OPTIONAL
EXTERNAL
REFERENCE
BUFFER
GAINCTRL
1.2V
REF
AVDD
AD9767
REFERENCE
SECTION
REFIO
ADDITIONAL
EXTERNAL
LOAD
0.1µF
CURRENT
SOURCE
ARRAY
FSADJ
ACOM
2kΩ
00620-023
IREF
Figure 23. Internal Reference Configuration
An external reference can be applied to REFIO as shown in
Figure 24. The external reference can provide either a fixed
reference voltage to enhance accuracy and drift performance or
a varying reference voltage for gain control. The 0.1 μF
compensation capacitor is not required because the internal
reference is overridden, and the relatively high input impedance
of REFIO minimizes any loading of the external reference.
REFERENCE CONTROL AMPLIFIER
Both of the DACs in the AD9767 contain a control amplifier
that is used to regulate the full-scale output current (IOUTFS).
The control amplifier is configured as a V-I converter as shown
in Figure 23, so that its current output (IREF) is determined by
the ratio of the VREFIO and an external resistor, RSET, as stated in
Equation 4. IREF is copied to the segmented current sources with
the proper scale factor to set IOUTFS as stated in Equation 3.
The control amplifier allows a wide (10:1) adjustment span of
IOUTFS from 2 mA to 20 mA by setting IREF between 62.5 μA and
625 μA. The wide adjustment range of IOUTFS provides several
benefits. The first relates directly to the power dissipation of the
AD9767, which is proportional to IOUTFS (see the Power
Dissipation section). The second relates to the 20 dB adjustment, which is useful for system gain control purposes.
The small signal bandwidth of the reference control amplifier is
approximately 500 kHz and can be used for low frequency,
small signal multiplying applications.
DAC TRANSFER FUNCTION
Both DACs in the AD9767 provide complementary current outputs,
IOUTA and IOUTB. IOUTA provides a near full-scale current output (IOUTFS)
when all bits are high (for example, DAC CODE = 16383), while
IOUTB, the complementary output, provides no current. The
current output appearing at IOUTA and IOUTB is a function of both
the input code and IOUTFS and can be expressed as
B
GAINCTRL
1.2V
REF
REFIO
EXTERNAL
REFERENCE
FSADJ
IREF
AD9767
REFERENCE
SECTION
CURRENT
SOURCE
ARRAY
2kΩ
ACOM
00620-024
AVDD
AVDD
Figure 24. External Reference Configuration
GAIN CONTROL MODE
The AD9767 allows the gain of each channel to be independently
set by connecting one RSET resistor to FSADJ1 and another RSET
resistor to FSADJ2. To add flexibility and reduce system cost, a
single RSET resistor can be used to set the gain of both channels
simultaneously.
IOUTA = (DAC CODE/16384) × IOUTFS
(1)
IOUTB = (16383 – DAC CODE)/16384) × IOUTFS
(2)
where DAC CODE = 0 to 16383 (decimal representation).
IOUTFS is a function of the reference current (IREF). This is
nominally set by a reference voltage (VREFIO)and external resistor
(RSET). It can be expressed as
IOUTFS = 32 × IREF
(3)
where
Rev. C | Page 13 of 28
IREF = VREFIO/RSET
(4)
AD9767
The two current outputs typically drive a resistive load directly
or via a transformer. If dc coupling is required, IOUTA and IOUTB
are directly connected to matching resistive loads (RLOAD) that
are tied to analog common (ACOM). Note that RLOAD can represent
the equivalent load resistance seen by IOUTA or IOUTB, as is the case in
a doubly terminated 50 Ω or 75 Ω cable. The single-ended voltage
output appearing at the IOUTA and IOUTB nodes is simply
B
VOUTA = IOUTA × RLOAD
(5)
VOUTB = IOUTB × RLOAD
(6)
significant as the frequency content of the reconstructed
waveform increases. This is due to the first order cancellation of
various dynamic common-mode distortion mechanisms, digital
feedthrough, and noise.
Performing a differential-to-single-ended conversion via
a transformer also provides the ability to deliver twice the
reconstructed signal power to the load, assuming no source
termination. Because the output currents of IOUTA and IOUTB are
complementary, they become additive when processed
differentially. A properly selected transformer allows the
AD9767 to provide the required power and voltage levels to
different loads.
B
Note that the full-scale value of VOUTA and VOUTB must not
exceed the specified output compliance range to maintain
specified distortion and linearity performance:
VDIFF = (IOUTA − IOUTB) × RLOAD
(7)
Substituting the values of IOUTA, IOUTB and IREF, VDIFF can be
expressed as
B
VDIFF = {(2 × DAC CODE − 16383)/16384} ×
(8)
The output impedance of IOUTA and IOUTB is determined by the
equivalent parallel combination of the PMOS switches
associated with the current sources and is typically 100 kΩ in
parallel with 5 pF. It is also slightly dependent on the output
voltage (VOUTA and VOUTB) due to the nature of a PMOS device.
As a result, maintaining IOUTA and/or IOUTB at a virtual ground via an
I-V op amp configuration results in the optimum dc linearity. Note
the INL/DNL specifications for the AD9767 are measured with
IOUTA maintained at a virtual ground via an op amp.
B
B
B
(32 × RLOAD/RSET) × VREFIO
Equation 7 and Equation 8 highlight some of the advantages of
operating the AD9767 differentially. First, the differential operation
helps cancel common-mode error sources associated with IOUTA
and IOUTB such as noise, distortion, and dc offsets. Second, the
differential code dependent current and subsequent voltage, VDIFF,
is twice the value of the single-ended voltage output (VOUTA or
VOUTB), thus providing twice the signal power to the load.
B
The gain drift temperature performance for a single-ended
(VOUTA and VOUTB) or differential output (VDIFF) of the AD9767
can be enhanced by selecting temperature tracking resistors for
RLOAD and RSET due to their ratiometric relationship, as shown in
Equation 8.
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of –1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit can result in a breakdown
of the output stage and affect the reliability of the AD9767.
B
ANALOG OUTPUTS
The complementary current outputs in each DAC, IOUTA, and
IOUTB, can be configured for single-ended or differential operation.
IOUTA and IOUTB can be converted into complementary single-ended
voltage outputs, VOUTA and VOUTB, via a load resistor (RLOAD), as
described by Equation 5 through Equation 8. The differential
voltage, VDIFF, existing between VOUTA and VOUTB, can also be
converted to a single-ended voltage via a transformer or
differential amplifier configuration. The ac performance of the
AD9767 is optimum and specified using a differential
transformer coupled output in which the voltage swing at IOUTA
and IOUTB is limited to ±0.5 V. If a single-ended unipolar output is
desired, select IOUTA.
B
The distortion and noise performance of the AD9767 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both IOUTA and IOUTB can be
significantly reduced by the common-mode rejection of
a transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.
The enhancement in distortion performance becomes more
B
The positive output compliance range is slightly dependent on the
full-scale output current, IOUTFS. It degrades slightly from its
nominal 1.25 V for an IOUTFS = 20 mA to 1.00 V for an IOUTFS = 2 mA.
The optimum distortion performance for a single-ended or
differential output is achieved when the maximum full-scale
signal at IOUTA and IOUTB does not exceed 0.5 V. Applications
requiring the AD9767 output (VOUTA and/or VOUTB) to extend its
output compliance range must size RLOAD accordingly.
Operation beyond this compliance range adversely affects the
AD9767 linearity performance and subsequently degrades its
distortion performance.
B
B
DIGITAL INPUTS
The AD9767 digital inputs consist of two channels. For the
dual-port mode, each DAC has its own dedicated 14-bit data
port, WRT line, and CLK line. In the interleaved timing mode,
the function of the digital control pins changes as described in
the Interleaved Mode Timing section. The 14-bit parallel data
inputs follow straight binary coding, where DB13 is the most
significant bit (MSB) and DB0 is the least significant bit (LSB).
IOUTA produces a full-scale output current when all data bits are
at Logic 1. IOUTB produces a complementary output with the
full-scale current split between the two outputs as a function of
the input code.
Rev. C | Page 14 of 28
AD9767
DAC TIMING
The AD9767 can operate in two timing modes, dual and
interleaved, which are described in the following section.
The block diagram in Figure 27 represents the latch architecture
in the interleaved timing mode.
Dual-Port Mode Timing
When the MODE pin is at Logic 1, the AD9767 operates in
dual-port mode. The AD9767 functions as two distinct DACs.
Each DAC has its own completely independent digital input
and control lines.
The AD9767 features a double-buffered data path. Data enters
the device through the channel input latches (see Figure 21). This
data is then transferred to the DAC latch in each signal path.
Once the data is loaded into the DAC latch, the analog output
settles to its new value. For general consideration, the WRT
lines control the channel input latches and the CLK lines
control the DAC latches. Both sets of latches are updated on the
rising edge of their respective control signals.
The rising edge of CLK occurs before or simultaneously with
the rising edge of WRT. If the rising edge of CLK occurs after
the rising edge of WRT, a 2 ns minimum delay must be maintained
from the rising edge of WRT to the rising edge of CLK.
Timing specifications for dual-port mode are shown in Figure 25
and Figure 26.
tS
DATA IN
D2
D3
D4
D5
WRT1/WRT2
IOUTA
OR
IOUTB
xx
D1
D3
D2
Figure 26. Dual Mode Timing
Interleaved Mode Timing
When the MODE pin is at Logic 0, the AD9767 operates in
interleaved mode (see Figure 27). WRT1 now functions as
IQWRT and CLK1 functions as IQCLK. WRT2 functions as
IQSEL and CLK2 functions as IQRESET.
Data enters the device on the rising edge of IQWRT. The logic level
of IQSEL steers the data to either Channel Latch 1 (IQSEL = 1) or
to Channel Latch 2 (IQSEL = 0).
When IQRESET is high, IQCLK is disabled. When IQRESET
goes low, the following rising edge on IQCLK updates both
DAC latches with the data present at their inputs. In the interleaved mode, IQCLK is divided by 2 internally. Following this
first rising edge, the DAC latches are updated only on every
other rising edge of IQCLK. In this way, IQRESET is used to
synchronize the routing of the data to the DACs.
As with the dual-port mode, IQCLK occurs before or
simultaneously with IQWRT.
The digital inputs are CMOS-compatible with logic thresholds,
VTHRESHOLD, set to approximately half the digital positive supply
(DVDD), or
VTHRESHOLD = DVDD/2 (±20%)
INTERLEAVED
DATA IN, PORT 1
PORT 1
INPUT
LATCH
DAC1
LATCH
DAC1
PORT 2
INPUT
LATCH
IQWRT
IQSEL
tH
IQCLK
IQRESET
÷2
DEINTERLEAVED
DATA OUT
DAC2
LATCH
DAC2
Figure 27. Latch Structure Interleaved Mode
WRT1/WRT2
tLPW
CLK1/CLK2
00620-025
tCPW
tPD
D4
00620-026
CLK1/CLK2
DATA IN
IOUTA
OR
IOUTB
D1
Figure 25. Dual Mode Timing
Rev. C | Page 15 of 28
00620-027
The digital interface is implemented using an edge triggered
master/slave latch. The DAC outputs are updated following
either the rising edge or every other rising edge of the clock,
depending on whether dual or interleaved mode is being used.
The DAC outputs are designed to support a clock rate as high as
125 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulse width. The setup and hold times
can be varied within the clock cycle as long as the specified
minimum times are met, although the location of these
transition edges can affect digital feedthrough and distortion
performance. Best performance is typically achieved when the
input data transitions on the falling edge of a 50% duty cycle clock.
AD9767
Timing specifications for interleaved mode are shown in Figure 28
and Figure 29.
tS
tH
Digital signal paths are kept short and run lengths matched to
avoid propagation delay mismatch. The insertion of a low value
(20 Ω to 100 Ω) resistor network between the AD9767 digital
inputs and driver outputs can be helpful in reducing any
overshooting and ringing at the digital inputs that contribute to
digital feedthrough. For longer board traces and high data
update rates, stripline techniques with proper impedance and
termination resistors should be considered in order to maintain
clean digital inputs.
DATA IN
IQSEL
IQWRT
tH*
tLPW
The external clock driver circuitry provides the AD9767 with
a low jitter clock input meeting the minimum/maximum logic
levels while providing fast edges. Fast clock edges help
minimize any jitter that manifests itself as phase noise on
a reconstructed waveform. Thus, the clock input is driven by the
fastest logic family suitable for the application.
IQCLK
*APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY.
00620-028
tPD
IOUTA
OR
IOUTB
interface circuitry are specified to meet the minimum setup and
hold times of the AD9767 as well as its required minimum/
maximum input logic level thresholds.
Figure 28. Interleaved Mode Timing
INTERLEAVED
DATA
xx
D1
D2
D3
D4
Note that the clock input can also be driven via a sine wave,
which is centered around the digital threshold (DVDD/2) and
meets the minimum/maximum logic threshold. This typically
results in a slight degradation in the phase noise, which
becomes more noticeable at higher sampling rates and output
frequencies. In addition, at higher sampling rates, the 20%
tolerance of the digital logic threshold can be considered,
because it affects the effective clock duty cycle and,
subsequently, cuts into the required data setup and hold times.
D5
IQSEL
IQWRT
IQCLK
DVDD
IQRESET
D1
D3
xx
D2
D4
DIGITAL
INPUT
00620-030
DAC OUTPUT
PORT 2
xx
00620-029
DAC OUTPUT
PORT 1
Figure 29. Interleaved Mode Timing
Figure 30. Equivalent Digital Input
The internal digital circuitry of the AD9767 is capable of
operating over a digital supply range of 3.3 V to 5.0 V. As
a result, the digital inputs can also accommodate TTL levels
when DVDD is set to accommodate the maximum high level
voltage of the TTL drivers VOH (max). A DVDD of 3 V to 3.3 V
typically ensures proper compatibility with most TTL logic
families. Figure 30 shows the equivalent digital input circuit for
the data and clock inputs. The sleep mode input is similar, with
the exception that it contains an active pull-down circuit, thus
ensuring that the AD9767 remains enabled if this input is left
disconnected.
Because the AD9767 is capable of being updated up to 125
MSPS, the quality of the clock and data input signals are
important in achieving the optimum performance. Operating
the AD9767 with reduced logic swings and a corresponding
digital supply (DVDD) results in the lowest data feedthrough
and on-chip digital noise. The drivers of the digital data
INPUT CLOCK AND DATA TIMING RELATIONSHIP
SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9767 is rising edge triggered and so
exhibits SNR sensitivity when the data transition is close to this
edge. The goal when applying the AD9767 is to make the data
transition close to the falling clock edge. This becomes more
important as the sample rate increases. Figure 31 shows the
relationship of SNR to clock placement with different sample
rates. Note that at the lower sample rates, much more tolerance
is allowed in clock placement, while much more care must be
taken at higher rates.
Rev. C | Page 16 of 28
AD9767
80
80
70
70
90
50
IAVDD
40
50
40
30
30
20
–2
–1
0
1
2
TIME OF DATA CHANGE RELATIVE TO
RISING CLOCK EDGE (ns)
3
4
10
0
5
POWER DISSIPATION
The power dissipation (PD) of the AD9767 is dependent on
several factors, including
20
25
Figure 32. IAVDD vs. IOUTFS
Conversely, IDVDD is dependent on both the digital input waveform,
fCLK, and digital supply DVDD. Figure 33 and Figure 34 show IDVDD
as a function of full-scale sine wave output ratios (fOUT/fCLK) for
various update rates with DVDD = 5 V and DVDD = 3.3 V,
respectively. Note that IDVDD is reduced by more than a factor of 2
when DVDD is reduced from 5 V to 3.3 V.
35
30
125MSPS
25
100MSPS
IDVDD (mA)
The AD9767 has a power-down function that turns off the
output current and reduces the supply current to less than
8.5 mA over the supply range of 3.3 V to 5.0 V and over the full
temperature range. This mode can be activated by applying
a Logic Level 1 to the SLEEP pin. The SLEEP pin logic
threshold is equal to 0.5 × AVDD. This digital input also
contains an active pull-down circuit that ensures the AD9767
remains enabled if this input is left disconnected. The AD9767
takes less than 50 ns to power down and approximately 5 μs to
power back up.
15
IOUTFS
Figure 31. SNR vs. Clock Placement @ fOUT = 20 MHz and fCLK = 125 MSPS
SLEEP MODE OPERATION
10
20
65MSPS
15
10
•
The power supply voltages (AVDD and DVDD)
5
•
The full-scale current output (IOUTFS)
0
•
The update rate (fCLK)
•
The reconstructed digital input waveform
25MSPS
5MSPS
0
0.1
0.2
0.3
0.4
0.5
00620-033
–3
00620-031
0
–4
00620-032
20
10
0.5
00620-034
SNR (dBc)
60
RATIO (fOUT/fCLK)
Figure 33. IDVDD vs. Ratio @ DVDD = 5 V
18
The power dissipation is directly proportional to the analog
supply current (IAVDD) and the digital supply current (IDVDD).
IAVDD is directly proportional to IOUTFS, as shown in Figure 32,
and is insensitive to fCLK.
125MSPS
16
14
100MSPS
IDVDD (mA)
12
10
65MSPS
8
6
25MSPS
4
5MSPS
2
0
0
0.1
0.2
0.3
0.4
RATIO (fOUT/fCLK)
Figure 34. IDVDD vs. Ratio @ DVDD = 3.3 V
Rev. C | Page 17 of 28
AD9767
AD9767
APPLYING THE AD9767
OUTPUT CONFIGURATIONS
RLOAD
B
DIFFERENTIAL COUPLING USING A
TRANSFORMER
An RF transformer can be used to perform a differential-to
single-ended signal conversion, as shown in Figure 35.
A differentially coupled transformer output provides the
optimum distortion performance for output signals whose
spectral content lies within the transformer pass band. An RF
transformer such as the Mini-Circuits® T1-1T provides excellent
rejection of common-mode distortion (that is, even-order
harmonics) and noise over a wide frequency range. It also
provides electrical isolation and the ability to deliver twice the
power to the load. Transformers with different impedance ratios
can also be used for impedance matching purposes. Note that
the transformer provides ac coupling only.
The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both IOUTA and IOUTB. The complementary voltages appearing
at IOUTA and IOUTB (VOUTA and VOUTB) swing symmetrically
around ACOM and are maintained with the specified output
compliance range of the AD9767. A differential resistor (RDIFF)
can be inserted in applications where the output of the
transformer is connected to the load (RLOAD) via a passive
reconstruction filter or cable. RDIFF is determined by the
transformer impedance ratio and provides the proper source
termination, resulting in a low VSWR. Approximately half the
signal power is dissipated across RDIFF.
Figure 35. Differential Output Using a Transformer
DIFFERENTIAL COUPLING USING AN OP AMP
An op amp can also be used to perform a differential-to-singleended conversion, as shown in Figure 36. The AD9767 is
configured with two equal load resistors (RLOAD) of 25 Ω.
The differential voltage developed across IOUTA and IOUTB is
converted to a single-ended signal via the differential op amp
configuration. An optional capacitor can be installed across
IOUTA and IOUTB, forming a real pole in a low-pass filter.
The addition of this capacitor also enhances the op amp
distortion performance by preventing the DAC high slewing
output from overloading the op amp input.
B
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differential
op amp circuit using the AD8047 is configured to provide some
additional signal gain. The op amp must operate from a dual
supply, because its output is approximately ±1.0 V. Select a high
speed amplifier capable of preserving the differential performance
of the AD9767 while meeting other system level objectives (cost or
power). Consider the op amp differential gain, its gain setting
resistor values, and full-scale output swing capabilities when
optimizing this circuit.
500Ω
AD9767
225Ω
IOUTA
AD8047
225Ω
IOUTB
COPT
500Ω
25Ω
00620-036
B
OPTIONAL
RDIFF
25Ω
Figure 36. DC Differential Coupling Using an Op Amp
The differential circuit shown in Figure 37 provides the
necessary level-shifting required in a single supply system.
In this case, AVDD, which is the positive analog supply for both
the AD9767 and the op amp, is also used to level-shift the
differential output of the AD9767 to midsupply (that is, AVDD/2).
The AD8055 is a suitable op amp for this application.
Rev. C | Page 18 of 28
500Ω
AD9767
225Ω
IOUTA
225Ω
IOUTB
AD8055
COPT
25Ω
1kΩ
25Ω
AVDD
500Ω
Figure 37. Single-Supply DC Differential-Coupled Circuit
00620-037
A single-ended output is suitable for applications requiring
a unipolar voltage output. A positive unipolar output voltage
results if IOUTA and/or IOUTB is connected to an appropriately
sized load resistor, RLOAD, referred to as ACOM. This configuration may be more suitable for a single-supply system
requiring a dc-coupled, ground-referred output voltage.
Alternatively, an amplifier can be configured as an I-V converter,
thus converting IOUTA or IOUTB into a negative unipolar voltage.
This configuration provides the best dc linearity, because IOUTA
or IOUTB is maintained at a virtual ground. Note that IOUTA
provides slightly better performance than IOUTB.
IOUTB
00620-035
The following sections illustrate some typical output configurations
for the AD9767. Unless otherwise noted, IOUTFS is set to a nominal
20 mA. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. A
differential output configuration can consist of either an RF
transformer or a differential op amp configuration. The transformer configuration provides the optimum high frequency
performance and is recommended for any application allowing
for ac coupling. The differential op amp configuration is
suitable for applications requiring dc coupling, a bipolar output,
signal gain and/or level shifting within the bandwidth of the
chosen op amp.
B
MINI-CIRCUITS
T1-1T
IOUTA
AD9767
SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT
Figure 38 shows the AD9767 configured to provide a unipolar
output range of approximately 0 V to 0.5 V for a doubly
terminated 50 Ω cable because the nominal full-scale current
(IOUTFS) of 20 mA flows through the equivalent RLOAD of 25 Ω. In
this case, RLOAD represents the equivalent load resistance seen by
IOUTA or IOUTB. The unused output (IOUTA or IOUTB) can be
connected to ACOM directly or via a matching RLOAD. Different
values of IOUTFS and RLOAD can be selected as long as the positive
compliance range is adhered to. One additional consideration in
this mode is the integral nonlinearity (INL), as discussed in the
Analog Outputs section. For optimum INL performance, the
single-ended, buffered voltage output configuration is suggested.
IOUTFS = 20mA
One factor that can measurably affect system performance is
the ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the power supply rejection ratio. For
dc variations of the power supply, the resulting performance of
the DAC directly corresponds to a gain error associated with
the DAC full-scale current, IOUTFS. AC noise on the dc supplies is
common in applications where the power distribution is
generated by a switching power supply. Typically, switching
power supply noise occurs over the spectrum of tens of
kilohertz to several megahertz. The PSRR vs. frequency of the
AD9767 AVDD supply over this frequency range is shown in
Figure 40.
VOUTA = 0V TO 0.5V
IOUTA
50Ω
50Ω
00620-038
IOUTB
25Ω
Figure 38. 0 V to 0.5 V Unbuffered Voltage Output
90
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
COPT
RFB
200Ω
AD9767
IOUTFS = 10mA
IOUTA
U1
200Ω
00620-039
VOUT = IOUTFS × RFB
IOUTB
Figure 39. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS,
POWER-SUPPLY REJECTION
Many applications seek high speed and high performance under
less than ideal operating conditions. In these application circuits,
the implementation and construction of the printed circuit board is
PSRR (dB)
85
Figure 39 shows a buffered single-ended output configuration in
which the Op Amp U1 performs an I-V conversion on the
AD9767 output current. U1 maintains IOUTA (or IOUTB) at a virtual
ground, thus minimizing the nonlinear output impedance effect
on the DAC INL performance, as described in the Analog
Outputs section. Although this single-ended configuration
typically provides the best dc linearity performance, its ac
distortion performance at higher DAC update rates can be
limited by U1 slewing capabilities. U1 provides a negative
unipolar output voltage and its full-scale output voltage is
simply the product of RFB and IOUTFS. Set the full-scale output
within U1 voltage output swing capabilities by scaling IOUTFS
and/or RFB. An improvement in ac distortion performance can
result with a reduced IOUTFS, because the signal current U1
required to sink is subsequently reduced.
80
75
70
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
FREQUENCY (MHz)
1.1
00620-040
AD9767
as important as the circuit design. Proper RF techniques must be
used for device selection, placement, and routing, as well as
power supply bypassing and grounding, to ensure optimum
performance. Figure 45 to Figure 53 illustrate the recommended
printed circuit board ground, power, and signal plane layouts
that are implemented on the AD9767 evaluation board.
Figure 40. Power Supply Rejection Ratio vs. Frequency
Note that the units in Figure 40 are given in units of amps out/volts
in. Noise on the analog power supply has the effect of modulating
the internal current sources, and therefore the output current.
The voltage noise on AVDD, therefore, is added in a nonlinear
manner to the desired IOUT. PSRR is very code-dependent, thus
producing mixing effects that can modulate low frequency power
supply noise to higher frequencies. Worst-case PSRR for either one
of the differential DAC outputs occurs when the full-scale current
is directed towards that output. As a result, the PSRR measurement
in Figure 40 represents a worst-case condition in which the digital
inputs remain static and the full-scale output current of 20 mA is
directed to the DAC output being measured.
Suppose a switching regulator with a switching frequency of
250 kHz produces 10 mV of noise and, for simplicity’s sake
(to ignore harmonics), all of this noise is concentrated at 250 kHz.
To calculate how much of this undesired noise appears as
current noise superimposed on the DAC full-scale current,
IOUTFS, one must determine the PSRR in decibels using Figure 40
Rev. C | Page 19 of 28
AD9767
Proper grounding and decoupling are primary objectives in any
high speed, high resolution system. The AD9767 features
separate analog and digital supply and ground pins to optimize
the management of analog and digital ground currents in
a system. In general, decouple the analog supply (AVDD) to the
analog common (ACOM), as close to the chip as physically
possible. Similarly, decouple the digital supply (DVDD) to the
digital common (DCOM) as close to the chip as possible.
For those applications that require a single 5 V or 3.3 V supply
for both the analog and digital supplies, a clean analog supply
can be generated using the circuit shown in Figure 41. The circuit
consists of a differential LC filter with separate power supply
and return lines. Lower noise can be attained by using low ESRtype electrolytic and tantalum capacitors.
FERRITE
BEADS
TTL/CMOS
LOGIC
CIRCUITS
Rev. C | Page 20 of 28
ELECTROLYTIC
100µF
CERAMIC
10µF
TO
22µF
AVDD
0.1µF
ACOM
TANTALUM
5V
POWER SUPPLY
Figure 41. Differential LC Filter for Single 5 V and 3.3 V Applications
00620-041
at 250 kHz. To calculate the PSRR for a given RLOAD such that
the units of PSRR are converted from A/V to V/V, adjust the
curve in Figure 40 by the scaling factor 20 × log (RLOAD).
For instance, if RLOAD is 50 Ω, the PSRR is reduced by 34 dB
(for example, PSRR of the DAC at 250 kHz, which is 85 dB in
Figure 40, becomes 51 dB VOUT/VIN).
AD9767
–20
APPLICATIONS
VDSL APPLICATIONS USING THE AD9767
–40
–20
–30
–40
–50
–100
–120
4.85
4.95
5.00
5.05
5.10
5.15
FREQUENCY (MHz)
Figure 43. Notch in Missing Bin at 5 MHz Is Down >60 dB
(Peak Amplitude = 0 dBm)
Similar to a discrete multitone (DMT) waveform, a CDMA
waveform containing multiple subscribers can be characterized
as having a high peak to average ratio (that is, crest factor), thus
demanding highly linear components in the transmit signal
path. The bandwidth of the spectrum is defined by the CDMA
standard being used and is implemented in operation by using
a spreading code with particular characteristics.
Distortion in the transmit path can lead to power being transmitted
out of the defined band. The ratio of power transmitted in-band to
out-of-band is often referred to as adjacent channel power (ACP).
This is a regulatory issue due to the possibility of interference
with other signals being transmitted by air. Regulatory bodies
define a spectral mask outside of the transmit band, and the
ACP must fall under this mask. If distortion in the transmit
path causes the ACP to be above the spectral mask, then
filtering, or different component selection, is needed to meet
the mask requirements.
Figure 44 shows the AD9767, when used with the AD8346,
reconstructing a wideband CDMA signal at 2.4 GHz. The baseband signal is being sampled at 65 MSPS and has a chip rate of
8 M chips.
–70
–80
–90
–100
–30
–110
–40
0.685
0.705
0.725
0.745
0.765
0.785
0.805
0.825
FREQUENCY (MHz)
–50
00620-042
–120
0.665
4.90
Figure 42. Notch in Missing Bin at 750 kHz Is Down >60 dB
(Peak Amplitude = 0 dBm)
–60
==
(dB)
–70
CDMA
–80
–90
Code division multiple access (CDMA) is an air transmit/receive
scheme in which the signal in the transmit path is modulated with
a pseudorandom digital code (sometimes referred to as the
spreading code). The effect of this is to spread the transmitted
signal across a wide spectrum.
–100
–110
c11
c11
cu1
–120
cu1
C0
C0
–130
CENTER 2.4GHz
3MHz
FREQUENCY
SPAN 30MHz
00620-044
(dBm)
–60
–80
00620-043
As with other multitone applications, each VDSL tone is capable of
transmitting a given number of bits, depending on the signalto-noise ratio (SNR) in a narrow band around that tone. For a
typical VDSL application, the tones are evenly spaced over the
range of several kHz to 10 MHz. At the high frequency end of this
range, performance is generally limited by cable characteristics and
environmental factors such as external interferers. Performance at
the lower frequencies is much more dependent on the performance
of the components in the signal chain. In addition to in-band noise,
intermodulation from other tones can also potentially interfere
with the data recovery for a given tone. The two graphs in Figure 42
and Figure 43 represent a 500 tone missing bin test vector, with
frequencies evenly spaced from 400 Hz to 10 MHz. This test is very
commonly done to determine if distortion limits the number of bits
that can be transmitted in a tone. The test vector has a series of
missing tones around 750 kHz, which is represented in Figure 42,
and a series of missing tones around 5 MHz, which is represented
in Figure 43. In both cases, the spurious-free dynamic range
(SFDR) between the transmitted tones and the empty bins is
greater than 60 dB.
–60
(dBm)
Very high frequency digital subscriber line (VDSL) technology is
growing rapidly in applications requiring data transfer over relatively
short distances. By using quadrature amplitude modulation (QAM)
and transmitting the data in discrete multiple tones (DMT), high data
rates can be achieved.
Figure 44. CDMA Signal, 8 M Chips Sampled at 65 MSPS, Recreated at
2.4 GHz Adjacent Channel Power > 60 dBm
Rev. C | Page 21 of 28
AD9767
This board allows the user the flexibility to operate the AD9767
in various configurations. Possible output configurations
include transformer-coupled, resistor-terminated, and single
and differential outputs. The digital inputs can be used in
dual-port or interleaved mode and are designed to be driven
from various word generators, with the on-board option to add
a resistor network for proper load termination. When operating the
AD9767, best performance is obtained by running the DVDD at
3.3 V and the AVDD at 5 V.
EVALUATION BOARD
GENERAL DESCRIPTION
The AD9767-EB is an evaluation board for the AD9767 14-bit
dual DAC. Careful attention to layout and circuit design, combined with a prototyping area, allow the user to easily and
effectively evaluate the AD9767 in any application where a high
resolution, high speed conversion is required.
DVDDIN
B3
L1
DVDD
BEAD
BAN-JACK
AVDDIN
1
C9
10µF
2 25V
B2
BLK
TP37
BAN-JACK
BLK
TP38
BAN-JACK
BLK
TP39
TP43
BLK
DVDD
L2
AVDD
BEAD
1
C10
10µF
BLK
TP40
2 25V
B4
BAN-JACK
DGND
WHT
TP29
2
1
3
A B
JP16
JP5
A 2B
1
2
1
DVDD
WHT
TP31
JP4
A 2B
1
I
DGND; 3, 4, 5
WHT
TP32
1
DGND; 3, 4, 5
1
2
1
R1
50Ω
2
1
R2
50Ω
2
R3
50Ω
1
2
JP1
I
J
1
AGND
10
U1
Q
K
CLR
15
3
5
11
13
CLK
2
DVDD
C
JP3
A2 B
2 0.01µF
3
PRE
3
3
1 C8
2 0.1µF
A B
JP2
C
I
DGND; 3, 4, 5
WRT2IN S4
IQSEL
1 C7
4
WHT
TP30
CLK2IN S3
RESET
BLK
TP42
JP6
DCLKIN2
DGND; 3, 4, 5
CLK1IN S2
IQCLK
BLK
TP41
TP44
BLK
JP9
DCLKIN1
WRT1IN S1
IQWRT
RED
TP11
Q
6
12
PRE
J
9
Q
U2
CLK
7
Q
K
CLR
TSSOP112
14
DGND; 8
DVDD; 16
TSSOP112
DGND; 8
DVDD; 16
A B
DVDD
1
3
2
JP7
/2 CLOCK DIVIDER
3
WRT1
C
R4
50Ω
CLK1
CLK2
WHT
TP33
WRT2
SLEEP
1
2
SLEEP
R13
50Ω
RP16
R1
22Ω
RCOM
1
2
INP1
R2
22Ω
3
INP2
R3
22Ω
4
INP3
R4
22Ω
5
INP4
R5
22Ω
6
R6
22Ω
7
INP5
INP6
R7
22Ω
8
INP7
R8
22Ω
9
R9
22Ω
RP9
R1
22Ω
RCOM
10
1
INP8
2
R2
22Ω
3
R3
22Ω
4
R4
22Ω
5
R5
22Ω
6
R6
22Ω
7
R7
22Ω
8
INP9 INP10 INP11 INP12 INP13 INP14
R8
22Ω
9
R1
22Ω
1
2
R2
22Ω
3
R3
22Ω
4
R4
22Ω
5
R5
22Ω
6
R6
22Ω
7
R7
22Ω
8
R8
22Ω
9
R9
22Ω
10
10
INCK1
RP10
RCOM
R9
22Ω
RP15
R1
22Ω
RCOM
1
INP23 INP24 INP25 INP26 INP27 INP28 INP29 INP30
2
R2
22Ω
3
R3
22Ω
4
R4
22Ω
5
R5
22Ω
6
R6
22Ω
7
INP31 INP32 INP33 INP34 INP35 INP36
Figure 45. Power Decoupling and Clocks on AD9767 Evaluation Board
Rev. C | Page 22 of 28
R7
22Ω
8
R8
22Ω
9
INCK2
R9
22Ω
10
00620-045
RED
TP10
B1
AD9767
RP3
RP1
RCOM R1
R9
22Ω
P1
P1 1
4
P1
P1 3
6
P1
P1 5
8
P1
P1 7
10
P1
P1 9
12
P1
P1 11
14
P1
P1 13
16
P1
P1 15
18
P1
P1 17
20
P1
P1 19
22
P1
P1 21
24
P1
P1 23
26
P1
P1 25
28
P1
P1 27
30
P1
P1 29
32
P1
P1 31
34
P1
P1 33
36
P1
P1 35
38
P1
P1 37
40
P1
P1 39
INP2
INP3
INP4
INP5
INP6
INP7
INP8
INP9
INP10
INP11
INP12
INP13
INP14
1
16
RP5, 10Ω
3
14
RP5, 10Ω
5
12
RP5, 10Ω
7
10
RP6, 10Ω
1
16
RP6, 10Ω
3
14
RP6, 10Ω
5
12
2
DUTP2
15
DUTP3
RP5, 10Ω
4
DUTP4
13
DUTP5
RP5, 10Ω
6
DUTP6
11
DUTP7
RP5, 10Ω
8
DUTP8
9
DUTP9
RP6, 10Ω
2
DUTP10
15
DUTP11
RP6, 10Ω
4
DUTP12
13
DUTP13
RP6, 10Ω
DUTP14
11
RP6, 10Ω
INCK1
8
DCLKIN1
9
RP2
R9
1
P2 1
P2
P2 3
6
P2
P2 5
8
P2
P2 7
10
P2
P2 9
12
P2
P2 11
14
P2
P2 13
16
P2
P2 15
18
P2
P2 17
20
P2
P2 19
22
P2
P2 21
24
P2
P2 23
26
P2
P2 25
28
P2
P2 27
30
P2
P2 29
32
P2
P2 31
34
P2
P2 33
36
P2
P2 35
38
P2
P2 37
40
P2
P2 39
INP24
INP25
INP26
INP27
INP28
INP29
INP30
INP31
INP32
INP33
INP34
INP35
INP36
1
16
RP7, 10Ω
3
14
RP7, 10Ω
5
12
RP7, 10Ω
7
10
RP8, 10Ω
1
16
RP8, 10Ω
3
14
RP8, 10Ω
5
12
2 3 4 5 6 7 8 9 10
1
2
2 3 4 5 6 7 8 9 10
1
2 3 4 5 6 7 8 9 10
DUTP26
13
DUTP27
DUTP28
11
DUTP29
DUTP30
9
DUTP31
DUTP32
15
DUTP33
DUTP34
13
DUTP35
RP8, 10Ω
DUTP36
11
RP8, 10Ω
8
1
DUTP25
RP8, 10Ω
4
2 3 4 5 6 7 8 9 10
DUTP24
15
RP8, 10Ω
2
R9
33Ω
DUTP23
RP7, 10Ω
8
RCOM R1
DVDD
RP7, 10Ω
6
R9
33Ω
RP7, 10Ω
4
RP12
RCOM R1
RP7, 10Ω
6
INCK2
R9
22Ω
DVDD
RP7, 10Ω
RP14
RCOM R1
22Ω
P2
2 3 4 5 6 7 8 9 10
1
DUTP1
RCOM R1
4
2 3 4 5 6 7 8 9 10
1
R9
33Ω
DVDD
RP4
2
RCOM R1
RP5, 10Ω
6
INP23
R9
33Ω
2 3 4 5 6 7 8 9 10
1
RP11
RCOM R1
DCLKIN2
9
SPARES
RP5, 10Ω
7
10
RP8, 10Ω
7
10
Figure 46. Digital Input Signal Conditioning
Rev. C | Page 23 of 28
00620-046
2
DVDD
RP5, 10Ω
R9
22Ω
2 3 4 5 6 7 8 9 10
1
INP1
RP13
RCOM R1
AD9767
BL1
TP34
WHT
C1
2 VAL
1
C2
2 0.01µF
ACOM
JP15
DVDD
C3
0.1µF
2
AVDD
1
1
2
NC = 5
3
2
R11
VAL
3
A B
1
DUTP1
1
DB13P1MSB
MODE 48
DUTP2
2
DB12P1
AVDD 47
DUTP3
3
DB11P1
IA1 46
DUTP4
4
DB10P1
IB1 45
DUTP5
5
DB9P1
DUTP6
6
DB8P1
REFIO 43
DUTP7
7
DB7P1
GAINCTRL 42
1:1
DB6P1
FSADJ2 41
DUTP9
9
DB5P1
IB2 40
DUTP10
10
DB4P1
IA2 39
6
BL2
3
A B
1
2
C4 2
10pF 1
2
R6
50Ω
C5 2
10pF 1
TP45
WHT
R9
1.92kΩ
1
1
2
C17
22nF
1
2
R10
1.92kΩ
2
DB3P1
12
DB2P1
SLEEP 37
SLEEP
DUTP13
13
DB1P1
DB0P2 36
DUTP36
DUTP14
14
DB0P1
DB1P2 35
DUTP35
15
DCOM1
DB2P2 34
DUTP34
16
DVDD1
DB3P2 33
DUTP33
17
WRT1
DB4P2 32
DUTP32
ACOM 38
C6
10pF 1
1
CLK1
18
CLK1
DB5P2 31
DUTP31
CLK2
19
CLK2
DB6P2 30
DUTP30
WRT2
20
WRT2
DB7P2 29
DUTP29
21
DCOM2
DB8P2 28
DUTP28
22
DVDD2
DB9P2 27
DUTP27
DUTP23
23
DB13P2MSB
DB10P2 26
DUTP26
DUTP24
24
DB12P2
DB11P2 25
DUTP25
1
2
C15
10pF 1
11
DUTP12
WRT1
1
R5
50Ω
C16
22nF
DUTP11
U2
S6
OUT1
T1
FSADJ1 44
8
DUTP8
2
AGND; 3, 4, 5
1
MODE
JP8
DVDD
4
2
1
R7
50Ω
2
R8
50Ω
2
R15
256Ω
1
REFIO
TP36
WHT
2
R14
256Ω
1
1
2
2
C14
0.1µF
JP10
2
WHT
TP46
BL3
TP35
WHT
3
R12
VAL
2
NC = 5
4
AGND; 3, 4, 5
1:1
1
S11
OUT2
6
T2
BL4
AVDD
1
C11
2 1µF
1
C12
2 0.01µF
1
C13
2 0.1µF
Figure 47. AD9767 and Output Signal Conditioning
Rev. C | Page 24 of 28
00620-047
1
00620-048
AD9767
00620-049
Figure 48. Assembly, Top Side
Figure 49. Assembly, Bottom Side
Rev. C | Page 25 of 28
00620-050
AD9767
00620-051
Figure 50. Layer 1, Top Side
Figure 51. Layer 2, Ground Plane
Rev. C | Page 26 of 28
00620-052
AD9767
00620-053
Figure 52. Layer3, Power Plane
Figure 53. Layer 4, Bottom Side
Rev. C | Page 27 of 28
AD9767
OUTLINE DIMENSIONS
9.20
9.00 SQ
8.80
1.60
MAX
37
48
36
1
PIN 1
7.20
7.00 SQ
6.80
TOP VIEW
1.45
1.40
1.35
0.15
0.05
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
SEATING
PLANE
VIEW A
(PINS DOWN)
25
12
13
VIEW A
0.50
BSC
LEAD PITCH
24
0.27
0.22
0.17
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
051706-A
0.75
0.60
0.45
Figure 54. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9767AST
AD9767ASTRL
AD9767ASTZ 1
AD9767ASTZRL1
AD9767-EB
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
48-Lead LQFP
48-Lead LQFP
48-Lead LQFP
48-Lead LQFP
Evaluation Board
Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00620-0-10/06(C)
Rev. C | Page 28 of 28
Package Option
ST-48
ST-48
ST-48
ST-48