ECE-343 Spring 2012, Lab 3 PMOS Differential Amplifier Due as

advertisement
ECE-343 Spring 2012, Lab 3
PMOS Differential Amplifier
Due as indicated on the time-management form
Overview
The schematic given below shows a PMOS differential amplifier. This lab involves the analysis, simulation and
construction of the amplifier. Use only ALD1106 NMOS and ALD1107 PMOS transistors. In your designs, use the
model parameters from the spice models provided on the course www site. Connect the body terminals of the chip to
the appropriate supply rail (±5 V).
Tasks
1. First, replace the current source with a single resistor. Select resistors in the design so that M1 and M2 are both
biased at a drain current of 200 µA, and Q-point drain voltages are Vo1 = Vo2 = −3 V. Assume zero-volts DC
offset for the input voltages.
(a) (Analysis) Solve for the DC bias values at all nodes. Give the drain currents for all transistors.
(b) (Analysis) Solve for the (low frequency) values for Ad , Acm , and the common-mode rejection ratio. Give
your results for both the single-ended and the differential output cases.
(c) (Simulation) Verify your solutions for parts 1a and 1b using a circuit simulation.
(d) (Hardware) Construct the amplifier, and compare the performance of the hardware implementation with
the analysis and simulation results. Also measure the “input offset voltage” for your amplifier (see section
8.4 of Sedra/Smith).
2. (Design Modification) Now use MOSFET transistors to implement the current source (you choose the design),
and replace the load resistors with an NMOS current mirror to produce a single-ended output. Use the same bias
current as that used in Task 1.
For the modified circuit (this time using the single-ended output), repeat Task 1a. Use the expressions derived in
Section 8.5 of the text to predict the values of Ad , Acm , output impedance, and CMRR (no derivation needed).
Repeat Tasks 1c and 1d. In addition, simulate and measure |Ad |, |Acm | and CMRR versus frequency, and
simulate and measure the output impedance at 1 kHz.
3. Report and Demonstration:
(a) Lab partners labeled b are each responsible for producing a written lab report. Be sure to discuss your
design process, and present your theoretical, simulated, and experimental results.
(b) Each lab partner must schedule a short demonstration and oral exam with their grader TA. Lab notebooks
should be available to the TAs during this presentation.
Time Management and Lab Notebook Documentation
ECE343, Spring 2012, Lab 3
a
Names: Group #
b
Please use this form to collect signatures from your assigned TA for each lab as you complete the tasks indicated
below. Signatures must be collected on or before the indicated date. Include this completed form with your lab
notebooks and final lab report.
In unusual circumstances, you may request a If a change in schedule is approved, have the instructor/TA change and
change of one or more of the deadlines listed initial the dates listed below, and sign in this block.
below. This request must be approved either
Monday or Tuesday of the week in which the
lab is assigned.
Mon/Tues, Feb 20/21
Attend the lab briefing and review the deadlines given below. Any modifications must
be approved by Tuesday, 4:00 p.m.
Tues, Mar 13: 4:00 p.m.
(10 pts) Circuit design and simulation results completed All designs must be entered
into lab notebooks.
TA’s: Rate from 1 (worst) to 5 (best)...
Clarity of Design Process: 1 2 3 4 5
Lab Notebook Procedures: 1 2 3 4 5
Simulations Completed: 1 2 3 4 5
Clarity of Simulation Results: 1 2 3 4 5
Successful Design Complete: 1 2 3 4 5
Early Check-off: 1 2 3 4 5
Signature:
Fri, Mar 16: 3:30 p.m.
Date:
(10 pts) Experimental measurements completed and entered into lab notebooks.
Rate from 1 (worst) to 5 (best)...
Experimental Procedures Clearly Described:
Lab Notebook Procedures:
Preliminary Analysis of Results:
Clarity of Results Presentation:
Successful Design Demonstrated:
Early Check-off:
Signature:
12345
12345
12345
12345
12345
12345
Date:
Mon, Mar 19: 4:00 p.m.
Each Lab Partner must schedule a demonstration.
Mon, Mar 19: 4:00 p.m.
(10 pts) Rough draft of report completed: (Lab Partner b only) Text should be complete, requiring editing primarily for grammar, consistency, or presentation.
Signature:
Date:
As Scheduled
(40 pts) Demonstration and Oral Exam: Each partner is required to demonstrate a lab
measurement, and show understanding of the lab content. Lab notebooks must be present
at the time of the exam.
Wed, Mar 21: 4:00 p.m.
(50 pts) Final Report Due in Room 219 (Lab Partner b only) Turn in your final report
with this form. Reports are not accepted late.
Some briefing notes about Lab 3:
1. Use only the ALD1106 NMOS and ALD1107 PMOS models from the course www site for your calculations
and simulations. Other models will not be accepted.
2. Both supply terminals of the ALD1106/7 chips should be connected to the ±5 V supplies. No other connections
are allowed.
3. Your analysis should clearly show how solutions are obtained. It’s not sufficient to set up a large number of
device equations for simultaneous solution, and let a computer/calculator solve for the solution. (You’ll use a
circuit simulation for that.)
4. For simulation of common-mode and differential signals, you might consider using a source block in microcap
similar to the one shown below. Dependent voltage sources (each with a gain of 0.5) are used to superimpose
the differential component onto the common-mode component to form the amplifier inputs vi1 and vi2. Use
the sources Vicm and Vid to set the common-mode and differential components directly.
5. You’ll have to think over how to measure differential signals. Your scope probe is NOT a differential probe:
Do not connect the ground/shield/common scope probe terminal to one of the voltages to be measured. As
always, be careful when probing any high-impedance node of your circuit. Use good technique, and record your
measurement set-up in your lab notebook.
6. Look over the deadlines, and manage your time. Calculations/Simulations are due the second day after you
return from spring break. The final report is due March 21 (The same day as Test 2!).
Download