Trends in Integrated Circuits
Technology
Prof. Krishna Saraswat
Department of Electrical Engineering
Stanford University
Stanford, CA 94305
saraswat@stanford.edu
araswat
tanford University
1
EE311/ Trends
Miniaturization => Market growth
Market Growth
Investment
Better Performance/Cost
Technology Scaling
Semiconductors have
become increasingly more
important part of world
economy
Courtesy Prof. Tsu-Jae King
(Sources: VLSI Research Inc.; United
Nation yearbook; World Bank
Database; IMF)
araswat
tanford University
2
EE311/ Trends
1
World IC Market by Technology
Ref: Chang and Sze, ULSI Technology, 1996
Silicon CMOS has become the pervasive technology
araswat
tanford University
3
EE311/ Trends
Moore’s Law
Transistors Per Die
1011
1010
Memory
Microprocessor
109
8
10
107
4M
1M
106
64K
4K 16K
105
4
10
i486™
i486™
64M
Pentium®
Pentium® 4
Pentium® III
Pentium® II
i386™
80286
8080
1K
103
256K
16M
2G 4G
512M 1G
256M
128M
Itanium®
4004
102
8086
IC Performance to Gordon Moore’s Prediction
101
100
’60
’65
’70
’75
’80
’85
’90
’95
’00
’05
’10
Source: Intel
araswat
tanford University
4
EE311/ Trends
2
Feature Size Trend
1
Generation
0.1
LGATE
micron
0.01
0.001
1980
1990
2000 2010
2020
Gate length is not true measure of transistor size
araswat
tanford University
5
EE311/ Trends
Example: Microprocessor Evolution
Generation:
1.5µ
1.0µ
0.8µ
0.6µ
0.35µ
0.25µ
Intel386™ DX
Processor
Intel486™ DX
Processor
Pentium®
Processor
Pentium® II
Processor
araswat
tanford University
6
EE311/ Trends
3
MOS Device Scaling
Constant E Field Scaling
All device parameters are scaled by
the same factor α.
• Gate oxide thickness tox ↓
• Channel length L ↓
• Source/drain junction depth Xj ↓
• Channel doping ↑
• Supply voltage VD ↓
Why do we scale MOS transistors?
1. Increase device packing density ~ α2
2.
Improve frequency response (speed) ~ a
3.
Power/ckt: ~1/α2, power density constant
4.
Improve current drive (transconductance gm)
gm =
" ID
"VG VD = const
W
µn
L
W
#
µ
L n
#
araswat
Kox
VD
for VD < VD SAT , linear region
to x
Kox
(VG $ VT ) for VD > VDSAT , saturation region
to x
tanford University
7
EE311/ Trends
Intel’s Transistor Research down to 10nm
Electronics is Nanotechnology
DNA is 15 nm wide
30nm
65nm process
2005 production
20nm
45nm process
2007 production
Source: Intel
15nm
32nm process
2009 production
10nm
22nm process
2011 production
araswat
tanford University
8
EE311/ Trends
4
Speed increases as a result of scaling
100
10
Gate
Delay 1
(ps)
0.1
Limit
0.01
0.001
0.01
0.1
LGATE (um)
1
Source: Mark Bohr, Intel
araswat
tanford University
9
EE311/ Trends
Physical Limits in Scaling Si MOSFET
Gate stack
• Tunneling current ⇒ Increased Ioff
• Gate depletion ⇒ Increased EOT
Source/Drain
• Contact resistance
• Doping level, abruptness
High E-Field
• Mobility degradation
• Reliability
Gate
Source
Drain
Substrat
e
te
Channel
•
•
•
•
Surface scattering - the “universal mobility” tyranny
DIBL ⇒ drain to source leakage
Subthreshold slope limited to 60mV/decade (kT/q) ⇒ Increased Ioff
VG - VT decrease ⇒ reduced ION
Net result: Bulk-Si CMOS device performance increase commensurate with
size scaling is unlikely beyond the 70 nm node
araswat
tanford University
10
EE311/ Trends
5
MOSFET Scaling Limit: Leakage
Total Leakage Trend
Gate Leakage
S/D Leakage
Total Power Trends
Source: Marcyk, Intel
Ability to control Ioff will limit gate-length scaling
–
–
–
To suppress D/S leakage, need to use:
–
Higher body doping to reduce DIBL
⇒ lower mobility, higher junction capacitance, increased junction leakage
– Thinner gate dielectric to improve gate control ⇒ higher gate leakage
– Ultra-shallow S/D junctions to reduce DIBL ⇒ higher Rseries
araswat
11
tanford University
EE311/ Trends
MOSFET Scaling Problem: Saturation of IDsat
Relaxed OFF current Limit
Constant
OFF current Limit
5
10
I Dsat (A/m)
4 (drive current)
800
600
NMOS
400
200
0.25
0.1 0.2
PMOS
0.3 0.4 0.6
0.8
1.0
1.2
0.8
0.4
Channel Length (µm)
log Id
Source: Intel
0
1990
Low Vt
1995
1
2005
2000
• Data from IBM, TI, Intel, AMD, Motorola and
Lucent
High Vt
IOFF,low Vt
Supply Voltage (V)

Thermionic emission over barrier
QM tunneling through barrier
Band-to-band tunneling from body to drain
Drive Current (mA/µm)

Lo et al.,IEEE EDL, May 1997.
• Low OFF current desirable
IOFF,high Vt
araswat
0
tanford University
Vg
Changhoon Choi, PhD Thesis, Stanford Univ., 2002
12
EE311/ Trends
6
Phon
on
ulo
mb
ic
Effects of Scaling Bulk MOSFET on Mobility
Co
µ
Surface
Roughness
Eeff
1
1
1
1
=
+
+
µ eff µC µ ph µ sr
E eff
S. Takagi et al., IEEE TED, 41 (1994) 2357.
q
= (N dep + # $ NChannel )
"Si
Ndep= depletion charge density
NChannel = charge induced in the channel
Increases in substrate doping ⇒ Ndep ⇑
Gate oxide thickness decrease ⇒ NChannel ⇑
!
 Eeff increases with scaling ⇒ µ ⇓
 Reduced gate oxide thickness increases remote charge scattering ⇒ µ ⇓
 High k dielectrics have higher coulombic scattering due to surface states
and phonon scattering ⇒ µ ⇓


araswat
tanford University
13
EE311/ Trends
New Structures and Materials for
Nanoscale MOSFETs
5
3
4
2
Top Gate
G
S
C
D
1
High µ
channel
Si
BULK
Source
Si
SiO2
Drain
Bottom Gate
High-K
Double gate
SOI
1. Electrostatics - Double Gate
- Retain gate control over channel
- Minimize OFF-state drain-source leakage
2. Transport - High Mobility Channel
- High mobility/injection velocity
- High drive current for low intrinsic delay
3. Parasitics - Schottky S/D
- Reduced extrinsic resistance
4. Gate leakage - High-K dielectrics
- Reduced power consumption
5. Gate depletion - Metal gate
araswat
tanford University
14
EE311/ Trends
7
Combining New Device Structures with
New Materials
We will be here with
these innovations
We are
here today
• With better injection and transport we may be able to
improve MOSFET ION
• With better electrostatics we may be able to minimize Ioff
araswat
tanford University
15
EE311/ Trends
Nanotechnology Eras
0.1
100
65 nm
Generation
45 nm
32 nm
LGATE
22 nm
16 nm
11 nm
micron 0.01
8 nm
Evolutionary
CMOS
0.001
2000
Revolutionary
Exotic
CMOS
2010
Reasonably
Familiar
Nanotubes
Nanowires
1
2020
Really
Different
Source: Mark Bohr, Intel
araswat
tanford University
10 nm
16
EE311/ Trends
8
Scaling of MOS Gate Dielectric
K
ID ! gm !
thickness
(Ref: S. Asai,
Microelectronics Engg., Sept. 1996)
Gate SiO2 thickness is approaching < 10 Å to improve device performance
• How far can we push MOS gate dielectric thickness?
• How will we grow such a thin layer uniformly?
• How long will such a thin dielectric live under electrical stress?
• How can we improve the endurance of the dielectric?
araswat
tanford University
17
EE311/ Trends
Problems in Scaling of Gate Oxide
Polysilicon gate electrode
Dopant
penetration
Leakage current
gate oxide
Reliability due to
charge injection
Defects and
nonuniformity of film
Dielectric breakdown
Si substrate
•Below 20 Å problems with SiO2
– Gate leakage => circuit instability, power dissipation
– Degradation and breakdown
– Dopant penetration through gate oxide
– Defects
araswat
tanford University
18
EE311/ Trends
9
Dielectric Degradation
• Degradation during device operation due to high E field causing current injection
• Degradation during fabrication due to charging in plasma processing
Eox
e
E
cathode
N(E)
oxide
Anode
What are the mechanisms for damage and breakdown?
How can we engineer the gate dielectric to minimize the damage?
araswat
tanford University
19
EE311/ Trends
Gate Oxide Scaling Issues: Leakage
Current (µA/µm)
1000
Ion
10
0.1
Ioff
0.001
Source G. Bersuker, et al. Sematech
Igate
0.00001
50
70
100
130
180
Technology Generation (nm)
• Ion is not increasing with scaling
• Igate ⇑, power dissipation ⇑
• Circuit instability
araswat
tanford University
20
EE311/ Trends
10
High-k MOS Gate Dielectrics
Ichannel ∝ charge x source injection velocity
∝ (gate oxide cap x gate overdrive) vinj
∝ Cox (VGS - VT) Esource µinj
Historically Cox has been increased by decreasing gate oxide
thickness. It can also be increased by using a higher K dielectric
ID " Cox "
Today
20!
Å SiO2 K ≈ 4
K
thickness
Long term
Near future
100 Å high K
40 Å
K ≈ 20
Si3N4 K ≈ 8
Si
Higher thickness -> reduced gate leakage
araswat
tanford University
21
EE311/ Trends
Capacitance and Leakage for High-k Gate
Dielectric Films Grown Using ALCVD
Gate Leakage (A/cm2)
m
1
c
/
V
±
AB
(F
@
2
)e
g
a
k
a
e
L
10
10
-2
10
-4
10
-6
10
-8
10
Germanium
Silicon
0
Gate Current@ VFB+1V (A/cm2)
V
SiO2
2.5 nm
ALCVD
ZrO2
4 nm
-10
0
0.05
0.1
1/C
'
ox
0.15
0.2
2
(µm /fF)
Equivalent SiO2 Thickness (nm)
Perkins, Saraswat and McIntyre,
Stanford Univ.
Univ. 2002
Chui, Kim, Saraswat and McIntyre,
Stanford Univ.
Univ. 2004
araswat
tanford University
22
EE311/ Trends
11
Subthreshold Behavior
OFF
VDD - VT
ID
(log scale)
ON
VT
Fermi Dirac
distribution
VDD
S=
ILEAK or
IOFF
ION
source
!VG
! (ln I D )
• Diffusion of carriers over the
barriers to the channel.
• Fermi-dirac distribution of
carriers: e-E/kT
• Gate reduces the barrier to
current flow.
VG
QI " eq# s / kT
!s = f (VG )
=
1
V
" G
I D " QI " eq VG / # kT
Where
araswat
" = 1+
1
#
2Cox
draine
VG
60 mV/decade
q$ s N a
|%p |
tanford University
23
EE311/ Trends
Effect of Reducing Channel Length
 In devices with long channel lengths, the gate is completely responsible for
depleting the semiconductor (QB). In very short channel devices, part of the
depletion is accomplished by the drain and source bias
 Since less gate voltage is required to deplete QB, VT↓ as L↓. Similarly, as VD
↑, more QB is depleted by the drain bias, and hence VT↓. These effects are
particularly pronounced in lightly doped substrates.
VT
poly gate
n+
n+
p-substrate
depleted by
gate charge
junction
depletion
region
poly gate
n+
Drawn Channel Length, L
VT
n+
p-substrate
Supply Voltage, VD
araswat
tanford University
24
EE311/ Trends
12
Drain-Induced Barrier Lowering (DIBL)
• Exacerbates subthreshold leakage in short-channel devices
• Soft punchthrough induced by drain-to-substrate depletion region
• |VT | ↓ as VD ↑ [drain-induced short channel effects (SCE)]
• VD ↑  drain-to-substrate depletion region grows with more reverse bias
• Lateral electric fields in drain-induced depletion region lowers source-tochannel barrier, allowing more carriers to diffuse from source to channel
VDD
poly gate
poly gate
n+
n+
n+
p-well
CB
n+
p-well
source
drain
reduction of electron barrier
height in conduction band (CB)
at edge of source
VDD
araswat
tanford University
25
EE311/ Trends
Why do we need to scale junction depth?
Gate
N+ source
L
Depletion
region
L!
N+ drain
rj
P-Si
QB depleted
by source
QB depleted
by drain
Q * $
2 " W ' rj VT = VFB ! 2 " # F ! B " ,1 ! & 1+
! 1) " /
Cox + %
rj
( L.
• Roll-off in threshold voltage as the channel length is reduced
• VT roll-off is reduced as junction depth(rj) is decreased
• Sheet resistance increases as junction depth is reduced
L. Yau, Solid-State Electronics, vol. 17, pp. 1059, 1974
araswat
tanford University
26
EE311/ Trends
13
Series Resistance (ohms)
Source/Drain Resistance
y=0
SiO2
Gate
Metal
Rc
Rext Rov
Rdp
Nov(y)
x
Next(x)
140
120 NMOS
100
Scaled by ITRS Roadmap
80
Rext
60
Rdp
Rc
40
20
0
Rov
30 nm 50 nm 70 nm 100 nm
Physical Gate Length
Source: Jasonn Woo, UCLA
Problem in junction scaling:
• Sheet resistance of a junction is a strong function of doping density
• Maximum doping density is limited by solid solubility and it does not scale
• Silicidation can minimize the impact of junction sheet resistance (Rs,Rd)
• Contact resistance Rc is one of the dominant components for future technology
araswat
tanford University
27
EE311/ Trends
Contact Resistance
Specific contact resistivity
$ 2"
!c = ! co exp && B
% qh
#sm* '
)
N )(
ohm * cm 2
Doping density
PROBLEMS
• Contact resistance is a strong function of
doping density at the metal/silicon interface
• Solid sulubility of dopants does not scale !
(Ref: S. Swirhun, PhD Thesis, Stanford Univ. 1987)
araswat
tanford University
28
EE311/ Trends
14
Solutions to Shallow Junction
Resistance Problem
Extension implants
Elevated source/ drain
Schottky Source/Drain
Silicidation
araswat
tanford University
29
EE311/ Trends
Problems with Poly-Si Gate.
This occurs because of high E - field due to a combination of higher
supply voltage and thinner gate oxide.
Poly-Si gate
Gate depletion
Oxide
tox(electrical)
tox(physical)
Substrate
• Effect of depletion is to increase effective t ox and thus reduce Cox
• A reduced Cox implies reduction in gm and thus ID(on)
• Ionized impurities in the gate electrode cause “remote charge scattering”
⇒ Reduced mobility
araswat
Need metal gate electrode with proper workfunction
tanford University
30
EE311/ Trends
15
Evolution of MOSFET Structures
Ultra-Thin Body Single Gate SOI
BULK
Gate
Source
SOI
Si
Drain
SiO2
TBOX
Silicon Substrate
Advantages of Ultra-Thin Body SOI
• Depleted channel ⇒ no conduction path
is far from the gate
• Short channel effects controlled by
geometry
• Steeper subthreshold slope
• Lower or no channel doping
• Higher mobility
• Reduced dopant fluctuation
Ultra-Thin Body Double
Gate SOI
Source
Tox
Gate 1
Vg
SOI
Drain
Si
Gate 2
Ref: Philip Wong, IEDM Short Course, 1999
araswat
tanford University
31
EE311/ Trends
Non Planar MOSFETs
Vertical FET
Tri Gate FET
Double Gate FinFET
Gate
Channel
Drain
Source
SiO2
Gate
Source
Stanford, AT&T
UC Berkeley
Drain
Intel
araswat
tanford University
32
EE311/ Trends
16
Transport: Effects of Biaxial Tensile Strain on Si Energy Bands
Hoyt, 2002
Strained Si grown on Relaxed Si1-xGex
[001]
biaxial tension Δ2
Conduction Band
Additional splitting:
Band repopulation
Bulk Si
[010]
Ec
Strained Si
Δ4
Δ6
Δ Es ~ 67 meV/
10% Ge
Δ2
Δ4
[100]
- reduced intervalley
scattering
- smaller in-plane effective
transport mass
µ=q
!
m*c
mt
mt
Bulk Si E
Valence Band
Γ
HH/LH degeneracy lifted at Γ
mt < ml
Strained Si E
k
in-plane
Δ Es ~ 40
meV/10% Ge
HH
- reduced interband scattering
- smaller in-plane transport
mass due to band deformation
Single ellipsoid
ml
out-ofplane
k
LH
Spin-Orbit
araswat
tanford University
33
EE311/ Trends
Mobility Enhancements in Strained-Si MOSFETs
o
i
t
a
r
gate oxide
PMOS
LTO
spacer
Strained Si
t
n
e
m
e
c
n
a 2.0
h
n 1.8
e
Mobility Enhancement Factor
n+ poly
NMOS
Relaxed Si1-xGex n+
n+
Si1-xGex Graded layer
Si Substrate
V
DS
= 10 mV
300 K
1.6
y
t 1.4
i
l
i 1.2
b
o 1.0
M
0.80
0.0
Measured, J. Welser, et al.,
IEDM 1994.
Calculated for strained Si
MOS inversion layer
S. Takagi, et al., J. Appl. Phys. 80, 1996.
0.10
0.20
0.30
0.40
Substrate Ge fraction, x
Gibbons Group, Stanford
Intel
araswat
tanford University
34
EE311/ Trends
17
Nanowire and Nanotube FETs
Ge NW Growth
ALD HfO2 Coated of Ge NW FET
Ge
Containing
Vapor
metal
Channel
dielectric ~20nm
semiconductor
Au
Nanoparticle
~10nm
Ge
Nanowire
drain
gate
source
Carbob Nanotube MOSFET
Carbob Nanotube Growth
Gate
D
HfO2
S
10 nm SiO2
CnHm
Fe
p++ Si
CnHm
Catalyst Support
Key Challenge: Controlled growth
araswat
tanford University
35
EE311/ Trends
Seemingly Useful Devices
Limited Current Drive
Cryogenic operation
Limited Fan-Out
Critical dimension control
Challenging fabrication
and process integration
B
+
=
~ 2 nm
Spintronics
Need high spin injection
and long spin coherence time
araswat
tanford University
Limited thermal stability
New architectures needed
36
Carbon
Nanotubes
Controlled growth
EE311/ Trends
18
• In general this device scaling methodology
does not take into account many other chip
performance and reliability issues, e.g.,
interconnects, contacts, isolation, etc.
• These factors are now becoming an obstacle
in the evolution of integrated circuits.
araswat
tanford University
37
EE311/ Trends
Active Area pitch (µm)
Device Isolation pitch as a function of
minimum dimension
2.5
2.0
64M
1.5
1G
1.0
0.5
0.0
araswat
16M
P. Fazan, Micron, IEDM-93
0.0
0.2
0.4
0.6
Minimum dimension [µm]
0.8
1.0
With decreasing feature size the requirement on
allowed isolation area becomes stringent.
tanford University
38
EE311/ Trends
19
Scaling of Device Isolation
Semi-recessed LOCOS
Nitride
Nitride
Pad oxide
Field oxide
After field oxidation
Fully recessed LOCOS
LOCOS
based isolation technologies have serious problems
Nitride of area due to bird’s beak.
in loss
Pad oxide
Shallow trench isolation
After field oxidation
P-substrate
N-well
Deep trench isolation
Trench isolation can minimize area loss
araswat
tanford University
39
EE311/ Trends
Scaling of interconnections
New (scaled)
Old
• Bigger chip => longer interconnects
• Scaling to smaller dimensions => reduced cross section
• Larger R, L and C
araswat
tanford University
40
EE311/ Trends
20
Interconnect Delay Is Increasing
• Chip size is continually
increasing due to
increasing complexity
– Increase in R, L and C
• Device performance is
improving but interconnect
delay is increasing
Delay Time (ns)
scaling
101
Longest Interconnect Delay
100
10-1
Typical Gate Delay
• Need better materials
10-2
– Metal with lower resistivity
– Dielectrics with lower K
– Other solutions, e.g., 3D,
optical interconnects
araswat
tanford University
60
80
100
120 140 160 180
Technology Node (nm)
41
EE311/ Trends
Advances in Backend Technology
1970’s
1980’s
1990’s
Poly-Si gate
Aluminum
Aluminum alloys
Silicide contacts
Polycide gates
Local planarization
Layerd aluminum/titanium
Salicides
CVD tungsten plugs
Shallow trench isolation
Global planarization
araswat
tanford University
42
EE311/ Trends
21
Current Interconnect Technologies
Copper 6
Copper 5
Copper 4
Copper 3
Copper 2
Copper 1
Tungsten
Local Interconnect
Current Cu technology
Current Al technology
(Courtesy of Motorola)
(Courtesy of IBM)
araswat
tanford University
43
EE311/ Trends
Why Cu and Low-k Dielectrics?
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Al & SiO2 (! = 4)
Cu & SiO2 (! = 4)
global
semiglobal
Al & low-! (! = 2)
local
Cu & lo w- ! ( ! = 2)
0.09 0.13 0.18 0.25 0.35 µm
2007 2004 2001 1998 1995 Year
Tec hnology Generation
Source: Y.Nishi
Reduced resistivity and dielectric constant results in reduction in number of
metal layers as more wires can by placed in lower levels of metal layers.
araswat
tanford University
44
EE311/ Trends
22
Cu Resistivity: Effect of Line Width Scaling
• Effect of Cu diffusion Barrier
• Barriers have higher resistivity
• Barriers can’t be scaled below a minimum thickness
• Effect of Electron Scattering
• Reduced mobility as dimensions decrease
• Effect of Higher Frequencies
• Carriers confined to outer skin increasing resistivity
Problem is worse than anticipated in the ITRS 1999 roadmap
araswat
tanford University
45
EE311/ Trends
Problems in Scaling of Interconnections
Surrounded Interconnect
AS λ DECREASES
Cu
Barrier
• Resistivity increases as
grain size decreases
ρav
Layered Interconnect
Al
• Resistivity increases as
main conductor size
Barrier
Al
decreases but not the
Pure Metal
Interconnect
surroundingbarrier size
Cu
Minimum Feature Size (λ)
araswat
tanford University
46
EE311/ Trends
23
3-D Integration: Motivation
2D Area = A
Very Long Wire
3D
A/2
A/2
Number of Interconnects
(Log-Log Plot)
2-D IC
3-D IC
Wire-length
araswat
tanford University
3-D System
2-D System
Shorter Wire
• Integration of heterogeneous technologies
possible, e.g., memory & logic, optical I/O
• Reduce Chip footprint
• Replace long horizontal wires by short
vertical wires
• Interconnect length ⇓ and therefore R, L, C ⇓
– Power reduction
– Delay reduction
47
EE311/ Trends
No. Transistors/chip //
Perf/Functionality
Source: D. Radack, DARPA
3D batch
Repeaters or
optical I/O devices
Gate
n+/p+
n+/p+
M4
M3
M2
M1
Gate
n+/p+
n+/p+
3-D Packaging
Memory
or
Analog
M’1
Logic
Gate
n+/p+
2-D Batch
12-15 years
Time
T2
M’2
n+/p+
T1
No. Transistors per cm3 in system
3-D Motivation: Integration Density
End-of-Moore’s
Law!
The Best Integrators of Electronic Devices Will Own the
Heart of Every System – We have <15 Years to Figure it out
araswat
tanford University
48
EE311/ Trends
24
Can Optical Interconnects help?
On-Chip
Optical
Interconnects
40Tb/s
Optical I/O1024
x OC-768100Tb/s
On-ChipBisection BWPMM64 Tiles64b Processor+ 4MB DRAM
Chip-to-chip Optical Interconnects
Can potentially address many problems of
Cu/low-k wires

On-Chip Links

Clocking and Synchronization

High Bandwidth off-chip Links
Reduce power
Reduce delay
Reduce jitter and skew
araswat
tanford University

49
EE311/ Trends
Result: scaling of power components
Chandra, Kapur and Saraswat,
IEEE IITC, June 2002
ITRS projections for total
power dissipation on chip
• Dynamic Power: CV2f
• Leakage power: devices
• Short circuit power during switching
• Static power, e.g., analog components (sense amps etc.)
Power increasingly becoming the performance bottleneck for high-end
microprocessors
araswat
tanford University
50
EE311/ Trends
25
2
1
0
35 50 70 100 130
180
Power Density [ W / cm2 ]
3
1.2
1
0.8
0.6
0.4
0.2
0
30
25
20
15
10
5
0
5
Jmax [ MA / cm2 ]
4
Thermal Conductivity [
W / mK ]
Dielectric Constant
Thermal Behavior in ICs
4
3
2
1
0
35 50 70 100 130
180
Technology Node [nm]
Technology Node [nm]
• Thermal conductivity of low-k insulators is poor
• Thermal impedance increases
• Energy dissipated (CV2f) is increasing as performance improves
• Average chip temperature is rising
Source: ITRS
araswat
tanford University
51
EE311/ Trends
The problems Caused by Increased Power
RELIABILITY
Electromigration induced hillocks and voids
Void
Hillock
Metal
Dielectric
Metal
Mean time to failure
>100A will flow on these wires
MTF =
"E %
A
exp$ a '
n
# kT &
r J
m
10°C ⇑ , MTF ⇓ 50%
PERFORMANCE
!
As T ⇑ R ⇑, RC delay ⇑
10°C ⇑ , Speed ⇓ 5%
araswat
tanford University
52
EE311/ Trends
26
Conclusion: Technology Progression
Bulk CMOS
Strained Si
Si
(tensile)
Cu interconnect
Si0.8Ge0.2
Si1-xGex
Feature Size
3D ICs
FD SOI CMOS
Wafer bonding
Crystallization
Nanowires
Optical interconnect
Si
Low-k ILD
Double-Gate CMOS
Gate
Metal gate
High k gate dielectric
Source
Drain
Detectors, lasers,
modulators, waveguides
Ge/Si Heterostrcture
Single e
transistor
Ge on Si hetroepitaxy
Ge on Insulator
Molecular device
Nanowire
B
Nanotube
+ =
Spin device
Time
2 nm
araswat
tanford University
53
EE311/ Trends
Summary
MOS Transistor in 2010
A Circuit in 2010
A Factory in 2010
Gate oxide thickness < 1nm
Approaching $10 billion
Channel Length < 2nm
1010 components
Junction depth < 1-2nm
Integrated digital, analog, sensors
Size of an atom ~ 5 Å
Questions we are trying to answer
• How can we continue the Moore’s law
• What will be new materials, devices, circuits, sensors,
equipment, simulators, etc.
• How will we design them?
araswat
• How will we manufacture them?
tanford University
54
EE311/ Trends
27