June 7-10, 2009
San Diego, CA
Issues in Power Delivery System
Performance Verification
Gert Hohenwarter
GateWave Northern, Inc.
Objective
• Review power and ground path integrity
• Examine model and measurement
approaches
• Show some limitations and workarounds
June
June 77 to
to 10,
10, 2009
2009
IEEE
IEEE SW
SW Test
Test Workshop
Workshop
22
Approach
• Examine power path in a probe card
• Illuminate power delivery system integrity
requirements (aka power delivery network)
• Use models and measurements to evaluate
performance
• Provide a workable verification approach
June
June 77 to
to 10,
10, 2009
2009
IEEE
IEEE SW
SW Test
Test Workshop
Workshop
33
Physical environment
Typical test system
Power travels from
tester to DUT over a
considerable
distances compared
to switching times of
the devices under
test, thus…….
June
June 77 to
to 10,
10, 2009
2009
IEEE
IEEE SW
SW Test
Test Workshop
Workshop
44
… when
…current
draw
changes…
…
transients result.
June
June 77 to
to 10,
10, 2009
2009
IEEE
IEEE SW
SW Test
Test Workshop
Workshop
55
Noise and impedance example
• Sudden current draw
results in a voltage
according to V=L*di/dt
• Impedance at a particular
frequency is an alternate
way of expressing noise
voltage: V=Z*i
Z PDS = R + jX
June
June 77 to
to 10,
10, 2009
2009
IEEE
IEEE SW
SW Test
Test Workshop
Workshop
66
Remedy: Additional energy
storage
Bypass capacitors (C) provide additional energy
during times of sudden high demand
June
June 77 to
to 10,
10, 2009
2009
IEEE
IEEE SW
SW Test
Test Workshop
Workshop
77
Tester to die path model
Components of the power delivery system (PDS)
{ P/G planes act as low Z transmission lines ‘T’ }
June
June 77 to
to 10,
10, 2009
2009
IEEE
IEEE SW
SW Test
Test Workshop
Workshop
88
Power distribution inside DUT ?
• Problem – probe card
manufacturer often
doesn’t know precisely
what’s in the DUT
June
June 77 to
to 10,
10, 2009
2009
IEEE
IEEE SW
SW Test
Test Workshop
Workshop
99
Design
•
PDS impedance specification provided by IC
manufacturer
• Z PDS = R + jX
• Power delivery system performance depends on path
and position
• Both delivery and return paths are important
• Disruptions/detours add inductance
• FEA and CAE tools must be set up to take paths into
account
• Verification
June
June 77 to
to 10,
10, 2009
2009
IEEE
IEEE SW
SW Test
Test Workshop
Workshop
10
10
Typical model setup
Planes are established at the DUT level - the
impedance Z(f) is then determined from the DUT side
June
June 77 to
to 10,
10, 2009
2009
IEEE
IEEE SW
SW Test
Test Workshop
Workshop
11
11
Modeled impedance
Resonances are due to multiple transmission line
sections between bypass capacitors
June
June 77 to
to 10,
10, 2009
2009
IEEE
IEEE SW
SW Test
Test Workshop
Workshop
12
12
But does the PDS really work ?
• Instruments
– DMM / Impedance meter
– Time Domain Reflectometer (TDR)
– Vector Network Analyzer (VNA)
• Probes
– Individual
– Whole die (surrogate DUT)
June
June 77 to
to 10,
10, 2009
2009
IEEE
IEEE SW
SW Test
Test Workshop
Workshop
13
13
Probing – surrogate DUT
Probe card site
Surrogate DUT
Develop thin film based surrogate DUT circuit, touch
down on a probe card die site and measure
impedance at relevant locations on surrogate DUT
June
June 77 to
to 10,
10, 2009
2009
IEEE
IEEE SW
SW Test
Test Workshop
Workshop
14
14
Surrogate DUT in contact with
probes
Z can be measured/modeled at various locations of die and
represents the Z experienced by a circuit under test
June
June 77 to
to 10,
10, 2009
2009
IEEE
IEEE SW
SW Test
Test Workshop
Workshop
15
15
Alternative: Discrete probe test
Measure returned signal for each accessible pad
June
June 77 to
to 10,
10, 2009
2009
IEEE
IEEE SW
SW Test
Test Workshop
Workshop
16
16
TDR measurement
Model plot for
inductance values
from 200 pH to 5 nH
TDR does allow for
extraction of some info
about PDS performance
June
June 77 to
to 10,
10, 2009
2009
IEEE
IEEE SW
SW Test
Test Workshop
Workshop
17
17
VNA measurement (Z)
Model plot for
inductance values
from 200 pH to 5 nH
VNA shows whether
there are frequencies
that are “off limits”
June
June 77 to
to 10,
10, 2009
2009
IEEE
IEEE SW
SW Test
Test Workshop
Workshop
18
18
VNA measurement (Phase)
Model plot for
inductance values
from 200 pH to 5 nH
VNA measurement of
phase allows
determination of
complex impedance
e.g. inductance
June
June 77 to
to 10,
10, 2009
2009
IEEE
IEEE SW
SW Test
Test Workshop
Workshop
19
19
Example configuration
Hypothetical die layout with bypass
capacitor placed at one end
June
June 77 to
to 10,
10, 2009
2009
IEEE
IEEE SW
SW Test
Test Workshop
Workshop
20
20
Inductance as a function of pad location
both
10
9
8
7
6
5
both
4
3
2
1
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
Inductance L (nH) along the die (capacitor location is at right)
June
June 77 to
to 10,
10, 2009
2009
IEEE
IEEE SW
SW Test
Test Workshop
Workshop
21
21
Inductance L (nH) along the die
10
9
8
7
6
same
5
across
4
(capacitor is at right)
3
2
Same side - across
1
0
1
2
3
4
5
6
7
8
Measurement taken with probe ground on the same side as signal
contact (pink) or across to opposite ground area (blue)
June
June 77 to
to 10,
10, 2009
2009
IEEE
IEEE SW
SW Test
Test Workshop
Workshop
22
22
DUT area with multiple bypass caps
7
6
5
4
1
4
3
2
1
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Impedance Z () at 250 MHz as a function of position
across die
(2 nearly identical die)
June
June 77 to
to 10,
10, 2009
2009
IEEE
IEEE SW
SW Test
Test Workshop
Workshop
23
23
Still don’t know overall Z…
• Solution: Combine measurements with simulated
results for interconnect inductance
R12
R7
L19
R6
L17
R5
L15
L18
R3
L16
L12
R2
L10
R1
L4
L13
L11
Ceramic and PCB area with
bypass caps
L6
L14
T2
L2
L7
DUT / probe area with lateral
interconnect inductance plus
inductance of contacts
June
June 77 to
to 10,
10, 2009
2009
L20
L9
R10
C2
C6
C5
C7
L1
L5
L3
L8
R8
R11
R4
R9
IEEE
IEEE SW
SW Test
Test Workshop
Workshop
24
24
Z combined
Ohms
10
1
0.1
0.01
0.001
0.01
f [GHz]
0.1
1
Individual Z measurements combined into an overall
performance assessment
June
June 77 to
to 10,
10, 2009
2009
IEEE
IEEE SW
SW Test
Test Workshop
Workshop
25
25
Summary
• Power delivery system performance depends on path
and position
• Grounding during measurement as well as model
development must be carefully planned
• The overall performance is NOT the result of assuming
that all measurements effectively form a parallel circuit
of the individual Z measurements
• A combination of measurements and models allows for
assessment of overall performance
• Local performance should be verified against
specifications
June
June 77 to
to 10,
10, 2009
2009
IEEE
IEEE SW
SW Test
Test Workshop
Workshop
26
26