A METHOD OF SEGMENTING DIGITAL-TO-ANALOG CONVERTERS
K Ola Andersson1, Niklas U Andersson1,2, Mark Vesterbacka1, and J Jacob Wikner2
1Dept.
of E.E., Linköping University, SE-581 83 Linköping, Sweden
Infineon Technologies Wireless Solutions Sweden AB, Linköping, Sweden
{olaa, niklasa, markv}@isy.liu.se, jacob.j.wikner@infineon.com
2
ABSTRACT
b1
w1
Segmented architectures are often used in digital-toanalog converters (DACs). Here we propose a DAC structure based on recursive decomposition of an N -bit binary
DAC into two ( N – 1 )-bit DACs and one 1-bit DAC. A
DAC model that includes matching errors has been simulated. The simulation results indicate that by using four
layers of decomposition it is possible to achieve similar
performance as when using seven bits of traditional segmentation.
0
0
I. INTRODUCTION
bN
wN
ref.
0
X
N–M LSBs
switches
M MSBs
binary-to-thermometer encoder
Figure 1: A common strategy for digital-to-analog
conversion.
analog weights
delay
In this work we study the digital-to-analog converter
(DAC). So called flash DACs [1] operate by switching
weighted analog sources, e.g., voltage or current sources,
to a summing node, where the output is formed, as illustrated in Fig. 1.
Segmented architectures are commonly used in design
of high-performance converters [2, 3]. The binary coded
input is divided into two or more segments, some of
which are encoded to thermometer code. An N -bit DAC
with the M most significant bits (MSBs) thermometer
coded and the N – M least significant bits (LSBs) binary
coded is shown in Fig. 2. This case is used as a reference
in this work and is referred to as M -bit segmentation.
Glitches occur in the transition between two codes, and
contribute to the distortion in the DAC output [2, 3].
These glitches are partly caused by skew between the signals controlling the switches. For example, in a binary
weighted DAC with the consecutive input codes
(1)
X (n) = [ 0, 1, 1, …, 1, 1 ]
and
(2)
X (n + 1) = [ 1, 0, 0, …, 0, 0 ] ,
we may for a short period of time in the transition
between codes have an erroneous code controlling the
switches, e.g.,
(3)
X = [ 1, 1, 1, …, 1, 1 ] ,
causing a major glitch in the output, as illustrated in
Fig. 3.
In a first order model we assume the glitch magnitude to
be proportional to the total number of switched unit
output
bj
wj
Figure 2: DAC using M -bit segmentation.
weights in the transition between the codes [3]. As a simple measure of the glitch at an input code X we use the
total number of switched unit weights between the codes
X and X – 1 , i.e.,
S( X ) =
∑ aj – bj
j
⋅ wj ,
(4)
output level
Glitch in 4−bit binary weighted DAC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
n
update instant
Figure 3: Illustration of a major glitch in a 4-bit
binary coded DAC caused by skew in the
digital signals. The desired transition is
from 7 to 8.
where the different a j and b j are the individual bits of X
and X – 1 , respectively. The factor w j is the weight of bit
j , e.g., w j = 2 j for a binary coded input and w j = 1 for
a thermometer coded input.
Commonly used measures for the static linearity of a
DAC are the differential nonlinearity (DNL) and the integral nonlinearity (INL) [4]. The DNL for an input code X
is defined as the deviation from an ideal step in the transition between the codes X – 1 and X , i.e.,
Y (X ) – Y (X – 1)
DNL(X ) = -------------------------------------- – 1 ,
(5)
K
where Y (X ) and Y (X – 1) are the settled output levels for
the input codes X and X – 1 , respectively, and K is the
gain of the converter. The INL for an input code is defined
as the deviation of the actual output, Y (X ) , from the nominal output, Y nom(X ) , i.e.,
Y (X ) – Y nom(X )
INL(X ) = ------------------------------------(6)
K
The nominal output of the DAC is given by
Y nom(X ) = K ⋅ X + m ,
(7)
where the gain K and the offset m are found by adaptation (least square method) of a best-fit straight line with
respect to the actual outputs for the different input codes.
An alternative definition sometimes used is to express the
nominal output with a straight line between the outputs
for the minimum and maximum input code. The measure
S(X ) defined in (4) is related to the DNL of the converter.
Due to matching errors in the components, there will be
errors in the analog weights. If each unit weight is
regarded as a stochastic variable with expectation value
K and variance σ 2 , then DNL(X ) is a stochastic variable
with expectation value 0 and variance S(X ) ⋅ σ 2 ⁄ K 2 .
The traditional approach to obtain good glitch properties and high static linearity is to use a segmented converter structure, as discussed earlier. The more bits that
are thermometer coded, the better performance is
obtained at the expense of an exponentially increasing
hardware cost for the thermometer encoder. In this work,
we propose an alternative method to the conventional segmentation approach. It is based on recursive decomposition of an N -bit binary DAC into two ( N – 1 )-bit DACs
and one 1-bit DAC. The hardware cost grows exponentially for each level of decomposition also for this case,
but since it has different glitch properties it is an interesting design alternative to the conventional segmented converter.
The proposed approach is presented in Sec. II, simulation results for comparisons with common segmentation
are presented in Sec. III, and the work is concluded in
Sec. V.
II. PROPOSED APPROACH
In this section we present the decomposition method.
We start by describing the digital control logic used, and
continue with a qualitative discussion on the benefits of
the method, compared with traditional segmentation.
The control logic for the simplest form of the decomposition is shown in Fig. 4, where multiplexers are used to
realize the desired function. An N -bit binary coded input,
X , is decomposed into two ( N – 1 )-bit binary coded outputs, X 1 and X 2 and one 1-bit output X 0 . X 0 is the
MSB of X and
X1 = XL ∨ X0
(8)
and
X2 = XL ∧ X0 .
(9)
X L is the N – 1 LSBs of X , and the operators ‘∨’ and
‘∧’ in (8) and (9) denote the OR and AND operations
between X 0 and the individual bits of X L , respectively. If
X 0 , X 1 , and X 2 are used as inputs to three DACs whose
outputs are summed into one combined output, the operation of an N -bit DAC is obtained. By decomposing the
signal we have reduced the glitch in the transition
between
X = [ 0, 1, 1, …, 1, 1 ] = 2 N – 1 – 1
(10)
and
N–1
X = [ 1, 0, 0, …, 0, 0 ] = 2
,
(11)
since S(2 N – 1) = 2 N – 1 in the binary coded case,
whereas S(2 N – 1) = 1 using 1-layer decomposition.
A reduction of this glitch is also obtained by using 2-bit
segmentation. However, the improvement is not as large
0
XL
2N–1–1
XL
X0
10 %. The standard deviation could, of course, be much
lower in a well designed converter.
A
X2
X1
Figure 4: Control logic for 1-layer decomposition
implemented with multiplexers.
as when 1-layer decomposition is used, since
S(2 N – 1) = 2 N – 1 – 1 using 2-bit segmentation.
The decomposition can be repeated for X 1 and X 2 ,
resulting in four ( N – 2 ) bit binary coded DACs and three
1-bit DACs. This is what we refer to as 2-layer decomposition, which further reduces the glitches. Decomposing
these four binary weighted DACs results in 3-layer
decomposition, etc. In the general case with M -layer
decomposition there are 2 M ( N – M )-bit binary coded
DACs and 2 M – 1 1-bit DACs.
In Fig. 5(a) we plot S(X ) for a 14-bit binary weighted
DAC. The values of S(X ) using 2-bit and 3-bit segmentation are plotted in Fig. 5(b) and (d), respectively, and the
values of S(X ) using 1-layer and 2-layer decomposition
are plotted in Fig. 5(c) and (e), respectively. The maximum value of S(X ) is the same for M -layer decomposition and ( M + 1 )-bit segmentation. Due to the different
hardware structure, it is not trivial to conclude what
degree of decomposition that corresponds to a given
degree of segmentation. However, there are N different
levels of segmentation and N different levels of decomposition. Moreover, 1-bit segmentation and 0-layer
decomposition both correspond to binary code, and N -bit
segmentation and ( N – 1 )-layer decomposition both correspond to thermometer code. Therefore, we use a DAC
with ( M + 1 )-bit segmentation as a reference when investigating the properties of a DAC with M -layer decomposition.
III. SIMULATION RESULTS
Pairwise comparisons between DACs with ( M + 1 )-bit
segmentation and DACs with M -layer decomposition are
presented in this section. The influence of stochastic
matching errors are considered, and to make a fair comparison we use the same stochastic outcome of the matching errors for both types of DACs. In Fig. 6 we illustrate
how the unit weights, which are represented with circles,
are assigned to the two different DAC types. The assignments of unit weights for 5-bit DACs with 2-layer decomposition and 3-bit segmentation are indicated in the left
and right parts of the figure, respectively. In the simulation we consider 14-bit converters, and the standard deviation of the Gaussian distributed unit weights is chosen to
Influence on DNL and INL
Simulated values of DNL and INL for a 2-bit segmented
DAC are shown in Fig. 7(a) and (c), respectively. The
DNL and INL for the DAC using 1-layer decomposition
having the same matching errors in the unit weights as the
2-bit segmented converter are shown in Fig. 7(b) and (d),
respectively. We note that the variation of the INL for
codes around the DC level (which is indicated with
dashed line in Fig. 7(a)-(d)) is less for the DACs utilizing
decomposition than for the segmented DACs. This is not
true for all stochastic outcomes of the matching errors,
but for most. This is an important property for inputs that
have most of their values around the DC level, such as
sinusoids with low amplitude or Gaussian distributed signals. This is further discussed in the following section.
B
Influence on SNDR
DAC specifications are often expressed in terms of the
effective number of bits (ENOB) or, equivalently, the signal-to-noise-and-distortion ratio (SNDR). The output
from a DAC at update instant n is expressed as
Y (n) = Y nom(n) + e(n) ,
(12)
where the nominal output
Y nom(n) = K ⋅ X (n) + m
(13)
and e(n) is the error caused by mismatch for the input
code X (n) . The SNDR is defined as
P signal
SNDR = --------------,
(14)
P error
where P signal is the signal power and P error is the power
of the error signal e(n) . The expression given in (14) can
be expressed in terms of the variances of Y nom(n) and
e(n) , i.e.,
Var(Y (n))
SNDR = ----------------------- ,
(15)
Var(e(n))
where Var(Y (n)) and Var(e(n)) denote the variances of
Y (n) and e(n) , respectively.
For the simulations presented in this section we have
chosen the gain K and the offset m of the DAC to yield
the nominal DAC output as a best-fit straight line with
respect to the data points given by the signal used in the
simulations. Hence, the gain and offset are different for
different input signals. This is in order to minimize the
correlation between e(n) and X (n) .
For a qualitative discussion we assume that
e(n) = INL(X (n)) (which is not completely true, since
the nominal transfer characteristics differ between the two
cases). We concluded earlier that the variations of INL for
Binary coded
16000
14000
12000
S(X)
10000
8000
6000
4000
2000
0
0
2000
4000
6000
8000 10000 12000 14000 16000
Input code
(a)
1−layer decomposition
16000
16000
14000
14000
12000
12000
10000
10000
S(X)
S(X)
2−bit segmentation
8000
8000
6000
6000
4000
4000
2000
2000
0
0
2000
4000
6000
0
0
8000 10000 12000 14000 16000
Input code
2000
4000
(b)
16000
14000
14000
12000
12000
10000
10000
S(X)
S(X)
2−layer decomposition
16000
8000
6000
6000
4000
4000
2000
2000
0
0
2000
4000
6000
8000 10000 12000 14000 16000
Input code
8000 10000 12000 14000 16000
Input code
(c)
3−bit segmentation
8000
6000
0
0
2000
4000
6000
8000 10000 12000 14000 16000
Input code
(d)
(e)
Figure 5: S(X ) for 14-bit DAC using (a) binary code, (b) 2-bit segmentation, (c) 1-layer decomposition, (d) 3-bit
segmentation, and (e) 2-layer decomposition.
input codes close to the DC level was less for the DAC
using M -layer decomposition than for the DAC using
( M + 1 )-bit segmentation. Hence, if the input has most of
its codes around the DC level, then Var(e(n)) is likely to
be smaller for the DAC using M -layer decomposition
than for the DAC using ( M + 1 )-bit segmentation.
Sinusoids are often used as test signals for data converters. However, the actual signals used in many applications
are not sinusoids. For example discrete multi-tone (DMT)
signals may be used. DMT signals have approximately
Gaussian distribution. In the simulations presented here,
we consider two different inputs, whose respective histograms are shown in Fig. 8. The histogram in Fig. 8(a) is
for a full-scale sinusoid, and the histogram in Fig. 8(b) is
for a Gaussian distributed signal with a standard deviation
σ = 2.06 ⋅ 10 3 . Both signals consist of 2 16 samples.
First we consider the sinusoidal input. The SNDR is
simulated for 1000 different outcomes of the matching
errors. For each outcome we simulate both the segmented
and the decomposed DAC with unit weights assigned as
in Fig. 6. The mean SNDR is plotted vs. the number of
layers of decomposition for both types of DACs in Fig. 9.
We observe that the mean SNDR is higher for the DACs
using decomposition than for the corresponding segmented DACs.
The same analysis is performed for the Gaussian distributed input. The mean SNDR is plotted vs. the number
of layers of decomposition for both types of DACs in
DNL for a 2−bit segmented 14−bit DAC
thermometer bit no. 7
6
binary coded DAC no. 4
4
thermometer bit no. 6
thermometer bit no. 5
2
DNL
1−bit DAC no. 3
0
−2
−4
binary coded DAC no. 3
−6
thermometer bit no. 4
−8
1−bit DAC no. 2
5000
thermometer bit no. 3
10000
Input code
15000
(a)
binary coded DAC no. 2
DNL for a 14−bit DAC with 1−layer decomposition
thermometer bit no. 2
6
1−bit DAC no. 1
4
2
binary coded DAC no. 1
binary coded LSBs
DNL
thermometer bit no. 1
0
−2
−4
Figure 6: Assignment of unit weights for the two
DAC types.
−8
5000
10000
Input code
15000
(b)
INL for a 2−bit segmented 14−bit DAC
8
6
4
2
INL
Fig. 10. Here we find that the mean SNDR is better for
the DAC using decomposition than for the corresponding
segmented DAC. We also see that the DACs with 4-layer
decomposition has roughly the same mean SNDR as the
DACs with 7-bit segmentation. Just looking at the mean
SNDR is not sufficient to conclude which type of solution
is the best, we also need to consider the statistical distribution of the values. We define the yield of the converters
as the relative number of converters having an SNDR
higher than a required SNDR. The yield is plotted as a
function of the required SNDR for DACs with 7-bit segmentation (dashed) and 4-layer decomposition (solid) in
Fig. 11. We see that the two curves practically coincides
and conclude that the same SNDR can be achieved using
4-layer decomposition as with 7-bit segmentation (for the
input used).
−6
0
−2
−4
−6
−8
0
5000
10000
Input code
15000
(c)
INL for a 14−bit DAC with 1−layer decomposition
8
6
IV. SUGGESTIONS FOR FURTHER WORK
2
INL
The simulations presented in this work only considered
static errors caused by mismatch between components.
The limiting factor for high-speed DACs is generally the
dynamic behavior of the circuit. Therefore, it is interesting to investigate, e.g., the settling behavior of the different types of DACs through modeling or circuit
implementations.
In order to make a fair comparison between the segmented and decomposed DACs, it is also necessary to
define and evaluate a proper measure of the hardware cost
(e.g., chip area or power consumption).
4
0
−2
−4
−6
−8
0
5000
10000
Input code
15000
(d)
Figure 7: DNL and INL for DACs with 2-bit
segmentation ((a) and (c)) and 1-layer
decomposition ((b) and (d)).
Histogram for sinusoidal input
SNDR vs. no. of layers of decomposition
61
6000
60
5000
59
SNDR [dB]
No. of samples
7000
4000
3000
segmented
decomposed
58
57
2000
56
1000
0
0
5000
10000
Input code
15000
1
2
3
4
5
6
M
(a)
Figure 10: Mean SNDR plotted for M -layer
decomposition
and
( M + 1 )-bit
segmentation plotted vs. M for Gaussian
distributed input.
Histogram for Gaussian distributed input
6000
No. of samples
5000
Yield vs. SNDR
4000
100
3000
80
2000
0
0
5000
10000
Input code
Yield [%]
1000
15000
(b)
Figure 8: Histograms for (a) the sinusoid and (b) the
Gaussian distributed signal used as inputs
for the SNDR simulations.
segmented
decomposed
67
20
4−layer decomposition
7−bit segmentation
0
50
55
60
SNDR requirement [dB]
65
regarding the dynamic properties are required to draw any
conclusion of the efficiency of the proposed architecture
for high-speed DACs.
66.5
SNDR [dB]
40
Figure 11: Yield as a function of SNDR for DACs
with 7-bit segmentation (dashed) and 4layer decomposition (solid).
SNDR vs. no. of layers of decomposition
67.5
60
66
65.5
65
REFERENCES
64.5
[1]
64
63.5
1
2
3
4
5
6
M
Figure 9: Mean SNDR plotted for M -layer
decomposition
and
( M + 1 )-bit
segmentation plotted vs. M for sinusoidal
input.
[2]
[3]
V. CONCLUSIONS
An alternative to the commonly used segmented DAC
architecture was proposed. Simulation results indicate
that the proposed approach has a potential of improving
the performance of the converters, since it is less sensitive
to static errors caused by mismatch. Further investigations
[4]
J.W. Bruce, “Nyquist-rate digital-to-analog converter architectures,” IEEE Potentials, vol. 20,
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C.-H. Lin and K. Bult, “A 10-b, 500-MSample/s
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