Microelectronics Reliability 47 (2007) 1790–1794
www.elsevier.com/locate/microrel
Flexible active cycle stress testing of smart power switches
Michael Glavanovics
a
a,*
, Helmut Köck
a,b
, Vladimir Košel
a,c
, Tobias Smorodin
d,e
KAI – Kompetenzzentrum Automobil- und Industrieelektronik GmbH, Europastrasse 8, Villach, Austria
b
Carinthia University of Applied Sciences, Villach/Klagenfurt, Austria
c
Slovak University of Technology in Bratislava, Faculty of Electrical Engineering, Slovakia
d
Department of Microsystems Engineering, University of Freiburg, Germany
e
Infineon Technologies AG, Munich, Germany
Received 10 July 2007
Available online 28 August 2007
Abstract
Active cycle stress testing of smart power switches is conventionally performed either with current pulses of constant amplitude or
with waveforms derived by switching inductive loads. A flexible test system is introduced that is capable of generating arbitrary current
pulse shapes, which is verified experimentally on a typical smart power switch. It is demonstrated by a test run that pulses with different
shape and amplitude but equal thermal stress derived from thermal simulation lead to comparable cycle life time.
2007 Elsevier Ltd. All rights reserved.
1. Introduction
Automotive smart power switches are frequently used
for driving inductive loads (motors, relays, actuator
coils. . .). For reasons of cost and robustness, a freewheeling path to carry the load current during turn-off (Fig. 1a
and b) is avoided as far as possible. Instead, an integrated
gate clamp (Fig. 1c) is applied to dissipate inductive energy
directly in the switch, thus minimizing part count and eliminating the need for polarity reversal protection. However,
this simple solution common to automotive applications
will cause a significant rise of junction temperature during
turn-off [1,2], posing severe thermal stress on the silicon die,
bond wires and IC package [3,4].
Device reliability under so-called ‘‘repetitive clamping’’
stress is usually investigated by active cycle life testing of
statistically relevant samples with ohmic-inductive loads
according to given device specifications [5]. This method
seems reasonably efficient for product qualification, when
only a single nominal operating points is tested to meet,
e.g. automotive quality standards [6].
*
Corresponding author. Tel.: +43 4242 34 8905.
E-mail address: michael.glavanovics@k-ai.at (M. Glavanovics).
0026-2714/$ - see front matter 2007 Elsevier Ltd. All rights reserved.
doi:10.1016/j.microrel.2007.07.065
To systematically analyze stress-related degradation
mechanisms of smart power devices as described in [4],
and to measure their time to failure, more freedom in the
definition of cycle test conditions had to be achieved:
• Shape and duration of stress pulses should be selectable
by software, to model different load conditions like
inductive switching or short circuit events.
• A high repetition rate is desirable to obtain a large number of switching cycles in reasonable testing time. Therefore it should be independent of load characteristics like
current rise time, limited only by power dissipation in
the device under test (DUT).
• Test equipment should be protected from damage by
output overload in case of a DUT that fails in a short
circuit condition.
• DUT waveforms should be continuously measured, so
that failure events may detected in real time and stored
safely over extended test duration.
For this purpose, the ‘‘ARCTIS’’ (advanced repetitive
clamping test integration system) cycle stress test system
has been developed at the KAI competence center. The
flexibility in operating point definition is based on digitally
M. Glavanovics et al. / Microelectronics Reliability 47 (2007) 1790–1794
a
The ARCTIS system provides 256 test channels that
must be driven in sequential order to minimize peak load
on the four system power supplies. All data is generated
and read back by four FPGA-based digital real time controllers hosted by an industry standard PXI system. A common lab automation programming language is used to
generate the FPGA code and the host program that runs
on a standard PC, recording data and providing a graphical user interface.
As the tested devices might fail in a short circuit condition (switch continuously on) as well as in open mode
(switch continuously high ohmic), both possible failure
modes must be detected by current and voltage measurements during test pulses. and recorded by the host system
for later statistical analysis. Stored waveforms also allow
to verify proper operation of previously tested devices,
which helps to identify eventual changes of their electrical
properties (clamp voltage, on-resistance. . .) that may be
related to physical degradation of the power switch due
to electro-thermal stress, as observed in [7,8].
The large number of test channels with individual load
conditions makes it impractical to enter test parameters
manually at the host system user interface. Pulse shapes
are therefore defined offline in a spreadsheet tool together
with all other test conditions (supply voltage, limits for failure detection, sample rates. . .). These parameter sets are
then imported by the host program and downloaded to
the FPGA subsystem to start the test sequence.
During the test, waveforms and failure status of all
devices are visualized by the user interface for supervision
by the operators. However, there is no user interaction
required until the end of the test, when the recorded failures are available for statistical evaluation.
c
b
Fig. 1. Circuits for switching inductive loads: (a) single switch with
‘‘freewheeling’’ diode, (b) full bridge for bidirectional current flow and (c)
single DMOS switch with clamped gate.
controlled, galvanically isolated, high speed current
sources. This approach allows also to protect the test
equipment in case of device failure by disabling the source’s
output driver in case of overload. End of DUT life is
detected by electrical measurements during test pulses
and recorded for further statistical evaluation.
To evaluate system performance, a typical smart power
device was tested with constant versus linearly decaying
(‘‘inductive switching’’) current pulse shapes of equal calculated junction temperature rise to compare the influence of
pulse shape on device reliability.
2. Cycle stress test system
In the following, the ARCTIS test system for the emulation of inductive switching stress is briefly described
(Fig. 2). As mentioned before, instead of using ohmicinductive loads, current pulses are defined by floating current sources with a peak current output of 10 A applying
voltages up to 90 V. Reference values for pulse shape are
fed to the high bandwidth current control loop by a
12 bit D/A converter, voltage and current measurements
for diagnosis are performed by a 12 bit A/D converter.
All data are transmitted serially via high speed magnetic
couplers that allow an update and measurement rate of
10 ls. Every current source is individually protected
against electrical and thermal overload to make sure that
the reliability of the test system far exceeds that of the
tested DUTs.
PC-Host
System
PXI-Bus
A/D
&
D/A
converters
FPGA
System
with SPI
interface
1791
3. Definition of a verification test run
One approach to perform a simplified active cycle stress
test is to replace inductive switching waveforms by pulses
of constant amplitude and calculate the equivalent thermal
stress for each operating point of the tested device based on
a thermal model. This approach has been applied and presented before [1,5], as the hardware implementation may
based on simple pulse sources.
MOSFET
Driver
+
_
Current
Controller
Device
under Test
(DUT)
Galvanic Isolation
Fig. 2. Single channel block diagram of the cycle stress test system.
Power
Supply
ID
547601
Title
Flexibleactivecyclestresstestingofsmartpowerswitches
http://fulltext.study/article/547601
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Pages
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