Single, 3 V, CMOS, LVDS
Differential Line Receiver
ADN4662
±15 kV ESD protection on input pins
400 Mbps (200 MHz) switching rates
Flow-through pinout simplifies PCB layout
2.5 ns maximum propagation delay
3.3 V power supply
High impedance outputs on power-down
Low power design: typically 3 mW (quiescent)
Interoperable with existing 5 V LVDS drivers
Accepts small swing (310 mV typical) differential signal
levels
Supports open, short, and terminated input fail-safe
0 V to −100 mV threshold region
Conforms to TIA/EIA-644 LVDS standard
Industrial operating temperature range: −40°C to +85°C
Available in surface-mount (SOIC) package
FUNCTIONAL BLOCK DIAGRAM
VCC
ADN4662
RIN+
ROUT
RIN–
NC GND NC NC
07960-001
FEATURES
Figure 1.
APPLICATIONS
Point-to-point data transmission
Multidrop buses
Clock distribution networks
Backplane receivers
GENERAL DESCRIPTION
The ADN4662 is a single, CMOS, low voltage differential
signaling (LVDS) line receiver offering data rates of over
400 Mbps (200 MHz), and ultralow power consumption.
It features a flow-through pinout for easy PCB layout and
separation of input and output signals.
The ADN4662 and its companion driver, the ADN4661, offer a
new solution to high speed, point-to-point data transmission,
and a low power alternative to emitter-coupled logic (ECL) or
positive emitter-coupled logic (PECL).
The device accepts low voltage (310 mV typical) differential
input signals and converts them to a single-ended 3 V TTL/
CMOS logic level.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
ADN4662
TABLE OF CONTENTS
Features .............................................................................................. 1 ESD Caution...................................................................................6 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions..............................7 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................8 General Description ......................................................................... 1 Theory of Operation ...................................................................... 11 Revision History ............................................................................... 2 Applications Information .......................................................... 11 Specifications..................................................................................... 3 Outline Dimensions ....................................................................... 12 AC Characteristics........................................................................ 4 Ordering Guide .......................................................................... 12 Absolute Maximum Ratings............................................................ 6 REVISION HISTORY
1/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
ADN4662
SPECIFICATIONS
VDD = 3.0 V to 3.6 V; CL = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter 1
LVDS INPUT
High Threshold at RIN+, RIN− 3
Low Threshold at RIN+, RIN−3
Input Current at RIN+, RIN−
OUTPUT
Output High Voltage
Output Low Voltage
Output Short-Circuit Current 4
Input Clamp Voltage
POWER SUPPLY
No Load Supply Current
ESD PROTECTION
RIN+, RIN− Pins
All Pins Except RIN+, RIN−
Symbol
VTH
VTL
IIN
VOH
VOL
IOS
VCL
ICC
Min
−100
−10
−10
−20
2.7
2.7
2.7
−15
−1.5
Typ 2
±1
±1
±1
3.1
3.1
3.1
0.3
−47
−0.8
5.4
±15
±4
1
Max
Unit
Conditions/Comments
+100
mV
mV
μA
μA
μA
VCM = 1.2 V, 0.05 V, 2.95 V
VCM = 1.2 V, 0.05 V, 2.95 V
VIN = 2.8 V, VCC = 3.6 V or 0 V
VIN = 0 V, VCC = 3.6 V or 0 V
VIN = 3.6 V, VCC = 0 V
V
V
V
V
mA
V
IOH = −0.4 mA, VID = +200 mV
IOH = −0.4 mA, input terminated
IOH = −0.4 mA, input shorted
IOL = 2 mA, VID = −200 mV
Enabled, VOUT = 0 V
ICL = −18 mA
mA
Inputs open
kV
kV
Human body model
Human body model
+10
+10
+20
0.5
−100
9
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground, unless otherwise specified.
All typicals are given for: VCC = +3.3 V, TA = 25°C.
VCC is always higher than RIN+ and RIN− voltage. RIN− and RIN+ are allowed to have a voltage range of −0.2 V to VCC − VID/2. However, to be compliant with ac specifications,
the common voltage range is 0.1 V to 2.3 V.
4
Output short-circuit current (IOS) is specified as magnitude only; the minus sign indicates direction only. Only one output should be shorted at a time. Do not exceed
maximum junction temperature specification.
2
3
Rev. 0 | Page 3 of 12
ADN4662
AC CHARACTERISTICS
VDD = 3.0 V to 3.6 V; CL 1 = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
Differential Pulse Skew |tPHLD − tPLHD| 4
Differential Part-to-Part Skew 5
Differential Part-to-Part Skew 6
Rise Time
Fall Time
Maximum Operating Frequency 7
Symbol
tPHLD
tPLHD
tSKD1
tSKD3
tSKD4
tTLH
tTHL
fMAX
Min
1.0
1.0
0
Typ 2
2.15
2.03
80
200
510
445
250
Max
2.5
2.5
400
1.0
1.5
800
800
1
Unit
ns
ns
ps
ns
ns
ps
ps
MHz
Conditions/Comments 3
CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)
CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)
CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)
CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)
CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)
CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)
CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)
All channels switching
CL includes probe and jig capacitance.
All typicals are given for VCC = 3.3 V, TA = 25°C.
3
Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tTLH and tTHL (0% to 100%) ≤ 3 ns for RIN+/RIN−.
4
tSKD1 is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel.
5
tSKD3, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VCC and within 5°C
of each other within the operating temperature range.
6
tSKD4, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating
temperature and voltage ranges, and across process distribution. tSKD4 is defined as |maximum − minimum| differential propagation delay.
7
fMAX generator input conditions: f = 200 MHz, tTLH = tTHL < 1 ns (0% to 100%), 50% duty cycle, differential (1.05 V to 1.35 V peak-to-peak). Output criteria: 60%/40% duty
cycle, VOL (maximum 0.4 V), VOH (minimum 2.7 V), load = 15 pF (stray plus probes).
2
Rev. 0 | Page 4 of 12
ADN4662
Test Circuits and Timing Diagrams
VCC
RIN+
SIGNAL
GENERATOR
ROUT
RIN–
50Ω
07960-002
50Ω
CL
CL = LOAD AND TEST JIG CAPACITANCE
Figure 2. Test Circuit for Receiver Propagation Delay and Transition Time
RIN–
1.3V
0V (DIFFERENTIAL)
VID = 200mV
1.2V
RIN+
1.1V
tPLHD
tPHLD
VOH
80%
1.5V
1.5V
20%
20%
tTLH
tTHL
Figure 3. Receiver Propagation Delay and Transition Time Waveforms
Rev. 0 | Page 5 of 12
VOL
07960-003
ROUT
80%
ADN4662
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VCC to GND
Input Voltage (RIN+, RIN−) to GND
Output Voltage (ROUT) to GND
Operating Temperature Range
Industrial Temperature Range
Storage Temperature Range
Junction Temperature (TJ max)
Power Dissipation
SOIC Package
θJA Thermal Impedance
Reflow Soldering Peak Temperature
Pb-Free
Rating
−0.3 V to +4 V
−0.3 V to VCC + 3.9 V
−0.3 V to VCC + 0.3 V
−40°C to +85°C
−65°C to +150°C
150°C
(TJ max − TA)/θJA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
149.5°C/W
260°C ± 5°C
Rev. 0 | Page 6 of 12
ADN4662
RIN– 1
RIN+ 2
NC 3
ADN4662
TOP VIEW
NC 4 (Not to Scale)
8
VCC
7
ROUT
6
NC
5
GND
07960-004
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC = NO CONNECT
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
Mnemonic
RIN−
2
RIN+
3
4
5
6
7
NC
NC
GND
NC
ROUT
8
VCC
Description
Receiver Channel 1 Inverting Input. When this input is more negative than RIN+, ROUT is high. When this input is
more positive than RIN+, ROUT is low.
Receiver Channel 1 Noninverting Input. When this input is more positive than RIN−, ROUT is high. When this input is
more negative than RIN−, ROUT is low.
No Connect.
No Connect.
Ground reference point for all circuitry on the part.
No Connect.
Receiver Output (3 V TTL/CMOS). If the differential input voltage between RIN+ and RIN− is positive, this output is
high. If the differential input voltage is negative, this output is low.
Power Supply Input. This part can be operated from 3.0 V to 3.6 V.
Rev. 0 | Page 7 of 12
ADN4662
TYPICAL PERFORMANCE CHARACTERISTICS
0
3.6
ILOAD = –400µA
TA = 25°C
VID = 200mV
3.4
3.3
3.2
3.1
3.0
–10
–15
–20
–25
–30
–35
–40
–45
3.1
3.2
3.3
3.4
3.5
3.6
POWER SUPPLY VOLTAGE, VCC (V)
07960-007
3.0
3.0
3.2
3.3
3.4
3.5
3.6
POWER SUPPLY VOLTAGE, VCC (V)
Figure 5. Output High Voltage vs. Power Supply Voltage
Figure 8. Threshold Voltage vs. Power Supply Voltage
33.60
50
45
POWER SUPPLY CURRENT, ICC (mA)
33.55
33.50
33.45
33.40
33.35
33.30
40
TA = 25°C
VCC = 3.3V
VID = 200mV
CL = 15pF
35
30
25
20
15
10
07960-023
ILOAD = 2mA
TA = 25°C
VID = –200mV
5
33.25
3.1
3.2
3.3
3.4
3.5
3.6
POWER SUPPLY VOLTAGE, VCC (V)
0
0.01
07960-008
3.0
0.1
1
10
FREQUENCY (MHz)
100
1000
Figure 9. Power Supply Current vs. Frequency
Figure 6. Output Low Voltage vs. Power Supply Voltage
10
VOUT = 0V
TA = 25°C
9
POWER SUPPLY CURRENT, ICC (mA)
–37
–39
–41
–43
–45
–47
–49
–51
–53
8
VCC = 3.3V
VID = 200mV
CL = 15pF
FREQUENCY = 1MHz
7
6
5
4
3
2
07960-024
–35
1
–55
3.0
3.1
3.2
3.3
3.4
3.5
3.6
POWER SUPPLY VOLTAGE, VCC (V)
0
–40
07960-009
OUTPUT SHORT-CIRCUIT CURRENT, IOS (mA)
3.1
07237-011
–50
2.9
OUTPUT LOW VOLTAGE, VOL (mV)
VOUT = 0V
TA = 25°C
–5
THRESHOLD VOLTAGE, VTH (mV)
OUTPUT HIGH VOLTAGE, VOH (V)
3.5
Figure 7. Output Short-Circuit Current vs. Power Supply Voltage
–15
10
35
AMBIENT TEMPERATURE (°C)
60
Figure 10. Power Supply Current vs. Ambient Temperature
Rev. 0 | Page 8 of 12
85
ADN4662
6.0
2.3
tPHLD
2.2
2.1
tPLHD
2.0
1.9
1.8
–40
–15
10
35
60
VCC = 3.3V
CL = 15pF
FREQUENCY = 200MHz
VCM = 1.2V
5.5
5.0
4.5
4.0
3.5
3.0
tPLHD
2.5
tPHLD
2.0
1.5
1.0
85
0
AMBIENT TEMPERATURE, TA (°C)
250
3.0
2.5
tPLHD
2.0
tPHLD
0
0.5
1.0
1.5
2.0
150
100
50
0
–50
–100
3.0
2.5
TA = 25°C
VID = 200mV
FREQUENCY = 200MHz
CL = 15pF
200
07960-018
3.5
DIFFERENTIAL SKEW, tSKEW (ps)
TA = 25°C
FREQUENCY = 200MHz
VID = 200mV
CL = 15pF
07960-015
DIFFERENTIAL PROPAGATION DELAY,
tPLHD , tPHLD (ns)
4.0
3.0
3.1
3.3
3.4
3.5
3.6
Figure 15. Differential Skew vs. Power Supply Voltage
Figure 12. Differential Propagation Delay vs. Common-Mode Voltage
160
TA = 25°C
VID = 200mV
FREQUENCY = 200MHz
CL = 15pF
2.20
2.15
tPHLD
2.10
2.05
2.00
1.95
07960-016
tPLHD
1.90
3.1
3.2
3.3
3.4
3.5
VCC = 3.3V
VID = 200mV
FREQUENCY = 200MHz
CL = 15pF
140
DIFFERENTIAL SKEW, tSKEW (ps)
2.25
3.6
120
100
80
60
40
20
0
–40
07960-019
2.30
1.85
3.0
3.2
POWER SUPPLY VOLTAGE, VCC (V)
COMMON-MODE VOLTAGE, VCM (V)
DIFFERENTIAL PROPAGATION DELAY,
tPLHD , tPHLD (ns)
3.0
Figure 14. Differential Propagation Delay vs. Differential Input Voltage
Figure 11. Differential Propagation Delay vs. Ambient Temperature
1.5
0.5
1.0
1.5
2.0
2.5
DIFFERENTIAL INPUT VOLTAGE, VID (V)
07960-025
2.4
DIFFERENTIAL PROPAGATION DELAY,
tPLHD , tPHLD (ps)
VCC = 3.3V
VID = 200mV
FREQUENCY = 200MHz
CL = 15pF
07960-014
DIFFERENTIAL PROPAGATION DELAY,
tPLHD , tPHLD (ns)
2.5
–15
10
35
60
AMBIENT TEMPERATURE, TA (°C)
POWER SUPPLY VOLTAGE, VCC (V)
Figure 16. Differential Skew vs. Ambient Temperature
Figure 13. Differential Propagation Delay vs. Power Supply Voltage
Rev. 0 | Page 9 of 12
85
ADN4662
1800
560
FREQUENCY = 25MHz
CL = 15pF
TRANSITION TIME, tTLH, tTHL (ps)
540
tTLH
520
500
480
460
tTHL
440
420
400
3.0
3.1
3.2
3.3
3.4
TA = 25°C
VCC = 3.3V
VID = 200mV
FREQUENCY = 1MHz
1600
3.5
1400
1200
1000
tTLH
800
tTHL
600
400
200
3.6
POWER SUPPLY VOLTAGE, VCC (V)
10
400
–15
10
35
60
2.5
40
45
2.3
tPLHD
2.1
1.9
10
1600
TRANSITION TIME, tTLH, tTHL (ps)
2.9
tPHLD
2.5
tPLHD
2.3
2.1
TA = 25°C
VCC = 3.3V
VID = 200mV
FREQUENCY = 1MHz
20
25
30
LOAD (pF)
35
TA = 25°C
VCC = 3.3V
VID = 200mV
FREQUENCY = 200MHz
1400
1200
tTLH
1000
800
600
tTHL
400
200
25
30
LOAD (pF)
35
40
45
07960-026
20
15
Figure 21. Differential Propagation Delay vs. Load at 200 MHz
1800
15
TA = 25°C
VCC = 3.3V
VID = 200mV
FREQUENCY = 200MHz
1.7
3.1
2.7
tPHLD
1.5
85
Figure 18. Transition Time vs. Ambient Temperature
DIFFERENTIALPROPAGATIONDELAY,
tPLHD , tPHLD (ns)
45
2.7
AMBIENT TEMPERATURE, TA (°C)
10
40
Figure 19. Differential Propagation Delay vs. Load at 1 MHz
0
10
15
20
25
30
35
40
LOAD (pF)
Figure 22. Transition Time vs. Load at 200 MHz
Rev. 0 | Page 10 of 12
45
07960-029
350
–40
1.5
35
07960-028
tTHL
DIFFERENTIALPROPAGATIONDELAY,
tPLHD , tPHLD (ns)
tTLH
07960-021
TRANSITION TIME, tTLH, tTHL (ps)
FREQUENCY = 200MHz
CL = 15pF
450
1.7
30
2.9
VCC = 3.3V
VID = 200mV
1.9
25
Figure 20. Transition Time vs. Load
600
500
20
LOAD (pF)
Figure 17. Transition Time vs. Power Supply Voltage
550
15
07960-027
580
VCC = 3.3V
VID = 200mV
07960-020
TRANSITION TIME, tTLH, tTHL (ps)
600
ADN4662
THEORY OF OPERATION
A differential current input signal, received via a transmission
medium, such as a twisted pair cable, develops a voltage across
a terminating resistor, RT. This resistor is chosen to match the
characteristic impedance of the medium, typically around
100 Ω. The differential voltage is detected by the receiver and
converted back into a single-ended logic signal.
When the noninverting receiver input, RIN+, is positive with
respect to the inverting input RIN− (current flows through RT
from RIN+ to RIN−), then ROUT is high. When the noninverting
receiver input RIN+ is negative with respect to the inverting
input RIN− (current flows through RT from RIN− to RIN+), then
ROUT is low.
The ADN4662 differential line receiver is capable of receiving
signals of 100 mV over a ±1 V common-mode range centered
around 1.2 V. This relates to the typical driver offset voltage
value of 1.2 V. The signal originating from the driver is centered
around 1.2 V and may shift ±1 V around this center point. This
±1 V shifting may be caused by a difference in the ground
potential of the driver and receiver, the common-mode effect of
coupled noise, or both.
Using the ADN4663 as a driver, the received differential current
is between 2.5 mA and 4.5 mA (typically 3.1 mA), developing
between 250 mV and 450 mV across a 100 Ω termination resis-
(1.2 V + [310 mV/2]) = 1.355 V, and the inverting receiver input
(1.2 V − [310 mV/2]) = 1.045 V for Logic 1. For Logic 0, the
inverting and noninverting input voltages are reversed. Note that
because the differential voltage reverses polarity, the peak-to-peak
voltage swing across RT is twice the differential voltage.
Current mode signalling offers considerable advantages over
voltage mode signalling, such as RS-422. The operating current
remains fairly constant with increased switching frequency,
whereas with voltage mode drivers the current increases
exponentially in most cases. This is caused by the overlap as
internal gates switch between high and low, which causes currents
to flow from VCC to ground. A current mode device simply reverses
a constant current between its two outputs, with no significant
overlap currents.
This is similar to emitter-coupled logic (ECL) and positive emittercoupled logic (PECL), but without the high quiescent current of
ECL and PECL.
APPLICATIONS INFORMATION
Figure 23 shows a typical application for point-to-point data
transmission using the ADN4663 as the driver.
+
0.1µF
3.3V
10µF
TANTALUM
ADN4661
DOUT+
RT
DOUT–
DIN
Rev. 0 | Page 11 of 12
3.3V
10µF
TANTALUM
VCC
VCC
tor. The received voltage is centered around the receiver offset of
1.2 V. In other words, the noninverting receiver input is typically
+
0.1µF
GND
RIN+
ADN4662
100Ω
RIN–
ROUT
GND
Figure 23. Typical Application Circuit
07960-119
The ADN4662 is a single line receiver for low voltage
differential signaling. It takes a differential input signal of
310 mV typically and converts it into a single-ended 3 V
TTL/CMOS logic signal.
ADN4662
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
5
1
6.20 (0.2441)
5.80 (0.2284)
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
SEATING
PLANE
0.50 (0.0196)
0.25 (0.0099)
1.75 (0.0688)
1.35 (0.0532)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-A A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
4.00 (0.1574)
3.80 (0.1497)
Figure 24. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
ADN4662BRZ1
ADN4662BRZ-REEL71
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
Z = RoHS Compliant Part.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07960-0-1/09(0)
Rev. 0 | Page 12 of 12
Package Option
R-8
R-8