Ramon Canal Q1 2014/2015

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Ramon Canal
Q1 2014/2015
Professor
• Ramon Canal
• Office: B6-2nd floor
• Email: [email protected]
• Office hours:
– Tue. 15-17, Wed. 11-13
2
Course materials
http://docencia.ac.upc.edu/master/MIRI/PD/
– Course Information
– Slides
– Lab documentation
3
High-Performance
Computing
4
Agenda
• Course structure
• Evaluation
• What will I be able to do after the
course?
• Topics covered
• Lab sessions
• Course Schedule
• Bibliography
5
Course structure
• Lectures (once a week)
– Thursday 8-10
• Lab sessions (once a week)
– Tuesday 8-10
• Assignments
– 6 Lab sessions
– 1 Final project (last 4 weeks)
6
Evaluation
• Final mark will be based on the
performance of:
– The lab sessions (Lab)
– Presentation of a research topic (T)
– The final mark will be computed as: 0,8 x Lab + 0,2 T
7
What will I be able to do
after the course? (1)
This course offers a more advanced treatment of
digital design in the context of microprocessors.
With a special emphasis on:
1.Design methodology and practice.
2.Pipeline microprocessor architecture
implementation and evaluation
8
Contents
1. Historical Perspective
2. Technology-Aware Processor Design
3. Processor Design Cycle and Fabrication
4. Memory Hierarchy
5. Modern Processor Architectures
9
What will I be able to do
after the course?
1. Understand and implement a simple pipelined
processor
2. Program skillfully in a hardware description
language
3. Understand the intricacies of advanced
microprocessor structures
a)
b)
c)
d)
Memory Hierarchy
Branch Prediction
Out-of-Order Execution
Multithreading
10
Lab sessions
1. Infrastructure setup and test
2. Module definition and especification. Workplan
(2 weeks)
3. Module implementation (3 weeks)
4. Module Review (1 week)
5. Insertion in a pipelined CPU (5 weeks)
6. CPU review (1 week)
7. Extension of original module. (due 24/1)
11
Lab sessions - Module
Each group will chose one of the following
modules to extend their baseline processor
1.
2.
3.
4.
5.
Associative cache
Branch predictor
Store forwarding queue
Error detection and correction codes in the memory
High-performance functional units (i.e. adder,
substracter, etc.)
6. Acccelerators (i.e crypthograhy, neuronal nets, etc.)
12
Bibliography
• Mike Johnson, Superscalar Microprocessor
Design, Prentice Hall ISBN:0138756341.
• Principles of CMOS VLSI Design: A Systems
Perspective with Verilog/VHDL Manual (2nd
Edition), Neil H. E. Weste, Kamran Eshraghian,
Michael John Sebastian Smith, Addison Wesley
(2000)
• Fundamentals of Digital Logic with VHDL Design
(Third Edition), Stephen Brown and Zvonko
Vranesic
14
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