a
FEATURES
FET Input Amplifier
1 pA Input Bias Current
Low Cost
High Speed
145 MHz, –3 dB Bandwidth (G = +1)
180 V/s Slew Rate (G = +2)
Low Noise
7 nV/÷Hz (f = 10 kHz)
0.6 fA/÷Hz (f = 10 kHz)
Wide Supply Voltage Range
5 V to 24 V
Single-Supply and Rail-to-Rail Output
Low Offset Voltage 1.5 mV Max
High Common-Mode Rejection Ratio
–100 dB
Excellent Distortion Specifications
SFDR –88 dB @ 1 MHz
Low Power
6.4 mA/Amplifier Typical Supply Current
No Phase Reversal
Small Packaging
SOIC-8, SOT-23-5, and MSOP
APPLICATIONS
Instrumentation
Photodiode Preamp
Filters
A/D Driver
Level Shifting
Buffering
GENERAL DESCRIPTION
High Performance, 145 MHz
Fast FET ™ Op Amps
AD8065/AD8066*
CONNECTION DIAGRAMS
SOIC-8 (R)
AD8066
(Top View)
VOUT1 1
8
AD8065
VOUT 1
+VS
–IN1 2
7
VOUT2
–VS 2
+IN1
3
6
–IN2
+IN 3
–VS
4
5
+IN2
5 +VS
4 –IN
TOP VIEW
(Not to Scale)
SOIC-8 (R) and MSOP (RM)
AD8066
VOUT1 1
(Top View)
8
+VS
–IN1 2
7
VOUT2
+IN1 3
6
–IN2
–VS 4
5
+IN2
Despite being low cost, the amplifiers provide excellent overall
performance. The differential gain and phase errors of 0.02% and
0.02∞, respectively, along with 0.1 dB flatness out to 7 MHz,
make these amplifiers ideal for video applications. Additionally,
they offer a high slew rate of 180 V/ms, excellent distortion
(SFDR –88 dB @ 1 MHz), extremely high common-mode
rejection of –100 dB, and a low input offset voltage of 1.5 mV
max under warmed up conditions. The AD8065/AD8066 operate
using only a 6.4 mA/amplifier typical supply current, while they
are capable of delivering up to 30 mA of load current.
The AD8065/AD8066 are high performance, high speed,
FET input amplifiers available in small packages: SOIC-8, MSOP,
and SOT-23-5. They are rated to work over the industrial temperature range of –40∞C to +85∞C.
The AD8065/AD8066 Fast FET amplifiers are voltage feedback amplifiers with FET inputs offering very high performance
and ease of use. The AD8065 is a single amplifier and the AD8066
is a dual amplifier. The Fast FET amplifiers in ADI’s proprietary XFCB process allow exceptionally low noise operation
(7.0 nV/÷Hz and 0.6 fA/÷Hz) as well as very high input impedance.
24
G = +10
21
VO = 200mVp-p
18
G = +5
15
GAIN – dB
With a wide supply voltage range from 5 V to 24 V, the ability to
operate on single supplies, and a bandwidth of 145 MHz, the
AD8065/AD8066 are designed to work in a variety of applications.
For added versatility, the amplifiers also contain rail-to-rail
outputs.
SOT-23-5 (RT)
12
9
G = +2
6
3
G = +1
0
–3
*Protected by U.S. Patent No. 6,262,633
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
–6
0.1
1
10
FREQUENCY – MHz
100
1000
Figure 1. Small Signal Frequency Response
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD8065/AD8066–SPECIFICATIONS (@ T = 25C, V = 5 V, R = 1 k, unless otherwise noted.)
A
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Input Overdrive Recovery Time
Output Recovery Time
Slew Rate
Settling Time to 0.1%
S
Conditions
Min
Typ
G = +1, VO = 0.2 V p-p (AD8065)
G = +1, VO = 0.2 V p-p (AD8066)
G = +2, VO = 0.2 V p-p
G = +2, VO = 2 V p-p
G = +2, VO = 0.2 V p-p
G = +1, –5.5 V to +5.5 V
G = –1, –5.5 V to +5.5 V
G = +2, VO = 4 V Step
G = +2, VO = 2 V Step
G = +2, VO = 8 V Step
100
100
145
120
50
42
7
175
170
180
55
205
MHz
MHz
MHz
MHz
MHz
ns
ns
V/ms
ns
ns
–88
–67
73
24
7
0.6
0.02
0.02
dBc
dBc
dBc
dBm
nV/÷Hz
fA/÷Hz
%
Degree
130
NOISE/HARMONIC PERFORMANCE
SFDR
fC = 1 MHz, G = +2, VO = 2 V p-p
fC = 5 MHz, G = +2, VO = 2 V p-p
fc = 1 MHz, G = +2, VO = 8 V p-p
Third Order Intercept
fC = 10 MHz, RL = 100 W
Input Voltage Noise
f = 10 kHz
Input Current Noise
f = 10 kHz
Differential Gain Error
NTSC, G = +2, RL = 150 W
Differential Phase Error
NTSC, G = +2, RL = 150 W
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
VCM = 0 V, SOIC Package
SOIC Package
TMIN to TMAX
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Common-Mode Input Impedance
Differential Input Impedance
Input Common-Mode Voltage Range
FET Input Range
Usable Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Short Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio
L
TMIN to TMAX
VO = ± 3 V, RL = 1 kW
100
5 to +1.7
See Theory of Operation section
VCM = –1 V to +1 V
VCM = –1 V to +1 V (SOT-23)
RL = 1 kW
RL = 150 W
VO = 9 V p–p,
SFDR ≥ –60 dBc, f = 500 kHz
–85
–82
0.4
1
2
25
1
1
113
10
mV
mV/oC
pA
pA
pA
pA
dB
GW储pF
GW储pF
–5.0 to +2.4
–5.0 to +5.0
–100
–91
V
V
dB
dB
V
V
35
90
20
85
Unit
1000储2.1
1000储4.5
5
–2–
1.5
17
6
–4.88 to +4.90 4.94 to +4.95
4.8 to +4.7
30% Overshoot G = +1
± PSRR
Max
6.4
–100
mA
mA
pF
24
7.2
V
mA
dB
REV. B
AD8065/AD8066
SPECIFICATIONS (@T = 25C, V = 12 V, R = 1 k, unless otherwise noted.)
A
S
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Input Overdrive Recovery
Output Overdrive Recovery
Slew Rate
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
SFDR
Third Order Intercept
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
L
Conditions
Min
Typ
G = +1, VO = 0.2 V p-p (AD8065)
G = +1, VO = 0.2 V p-p (AD8066)
G = +2, VO = 0.2 V p-p
G = +2, VO = 2 V p-p
G = +2, VO = 0.2 V p-p
G = +1, –12.5 V to +12.5 V
G = –1, –12.5 V to +12.5 V
G = +2, VO = 4 V Step
G = +2, VO = 2 V Step
G = +2, VO = 10 V Step
100
100
145
115
50
40
7
175
170
180
55
250
MHz
MHz
MHz
MHz
MHz
ns
ns
V/ms
ns
ns
fC = 1 MHz, G = +2, VO = 2 V p-p
fC = 5 MHz, G = +2, VO = 2 V p-p
fc = 1 MHz, G = +2, VO = 10 V p-p
fC = 10 MHz, RL = 100 W
f = 10 kHz
f = 10 kHz
NTSC, G = +2, RL = 150 W
NTSC, G = +2, RL = 150 W
–100
–67
–85
24
7
1
0.04
0.03
dBc
dBc
dBc
dBm
nV/÷Hz
fA/÷Hz
%
Degree
VCM = 0 V, SOIC Package
0.4
1
3
25
2
2
114
130
SOIC Package
TMIN to TMAX
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Common-Mode Input Impedance
Differential Input Impedance
Input Common-Mode Voltage Range
FET Input Range
Usable Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Short Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio
REV. B
TMIN to TMAX
VO = ± 10 V, RL = 1 kW
103
Max
1.5
17
7
10
1000储2.1
1000储4.5
See Theory of Operation section
VCM = –1 V to +1 V
VCM = –1 V to +1 V (SOT-23)
RL = 1 kW
RL = 350 W
VO = 22 V p–p,
SFDR ≥ –60 dBc, f = 500 kHz
GW储pF
GW储pF
V
V
dB
dB
11.8 to +11.811.9 to +11.9
11.25 to +11.5
V
V
30
120
25
5
84
–3–
mV
mV/oC
pA
pA
pA
pA
dB
12 to +8.5 –12.0 to +9.5
–12.0 to +12.0
85
–100
82
–91
30% Overshoot G = +1
± PSRR
Unit
6.6
–93
mA
mA
pF
24
7.4
V
mA
dB
AD8065/AD8066–SPECIFICATIONS (@ T = 25C, V = 5 V, R = 1 k to 1.5 V, unless otherwise noted.)
A
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Input Overdrive Recovery Time
Output Recovery Time
Slew Rate
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
SFDR
Third Order Intercept
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
S
L
Conditions
Min
Typ
G = +1, VO = 0.2 V p-p (AD8065) 125
G = +1, VO = 0.2 V p-p (AD8066) 110
G = +2, VO = 0.2 V p-p
G = +2, VO = 2 V p-p
G = +2, VO = 0.2 V p-p
G = +1, –0.5 V to +5.5 V
G = –1, –0.5 V to +5.5 V
G = +2, VO = 2 V Step
105
G = +2, VO = 2 V Step
155
130
50
43
6
175
170
160
60
MHz
MHz
MHz
MHz
MHz
ns
ns
V/ms
ns
fC = 1 MHz, G = +2, VO = 2 V p-p
fC = 5 MHz, G = +2, VO = 2 V p-p
fC = 10 MHz, RL = 100W
f = 10 kHz
f = 10 kHz
NTSC, G = +2, RL = 150 W
NTSC, G = +2, RL = 150 W
65
50
22
7
0.6
0.13
0.16
dBc
dBc
dBm
nV/÷Hz
fA/÷Hz
%
Degree
VCM = 1.0 V, SOIC Package
0.4
1
1
25
1
1
113
103
SOIC Package
TMIN to TMAX
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Common-Mode Input Impedance
Differential Input Impedance
Input Common-Mode Voltage Range
FET Input Range
Usable Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Short Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio
TMIN to TMAX
VO = 1 V to 4 V (AD8065)
VO = 1 V to 4 V (AD8066)
100
90
0 to 1.7
See Theory of Operation section
VCM = 1 V to 4 V
VCM = 1 V to 2 V (SOT-23)
RL = 1 kW
RL = 150 W
VO = 4 V p-p,
SFDR ≥ –60 dBc, f = 500 kHz
74
78
0.1 to 4.85
30% Overshoot G = +1
5
5.8
78
± PSRR
Max
1.5
17
5
5
Unit
mV
mV/oC
pA
pA
pA
pA
dB
dB
1000储2.1
1000储4.5
GW储pF
GW储pF
0 to 2.4
0 to 5.0
100
91
V
V
dB
dB
0.03 to 4.95
0.07 to 4.83
V
V
35
75
5
mA
mA
pF
6.4
100
24
7.0
V
mA
dB
ABSOLUTE MAXIMUM RATINGS*
MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . See Figure 2
Common-Mode Input Voltage . . VEE – 0.5 V to VCC + 0.5 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 1.8 V
Storage Temperature . . . . . . . . . . . . . . . . . . –65∞C to +125∞C
Operating Temperature Range . . . . . . . . . . . –40∞C to +85∞C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300∞C
The maximum safe power dissipation in the AD8065/AD8066
packages is limited by the associated rise in junction temperature
(TJ) on the die. The plastic encapsulating the die will locally
reach the junction temperature. At approximately 150∞C, which
is the glass transition temperature, the plastic will change its
properties. Even temporarily exceeding this temperature limit may
change the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8065/AD8066.
Exceeding a junction temperature of 175∞C for an extended
period of time can result in changes in the silicon devices,
potentially causing failure.
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
–4–
REV. B
AD8065/AD8066
The still-air thermal properties of the package and PCB (JA),
ambient temperature (TA), and the total power dissipated in the
package (PD) determine the junction temperature of the die. The
junction temperature can be calculated as follows
MAXIMUM POWER DISSIPATION – W
2.0
TJ = TA + ( PD ¥ q JA )
The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package
due to the load drive for all outputs. The quiescent power is the
voltage between the supply pins (VS) times the quiescent current
(IS). Assuming the load (RL) is referenced to midsupply, then the
total drive power is VS /2 IOUT, some of which is dissipated in
the package and some in the load (VOUT IOUT). The difference
between the total drive power and the load power is the drive
power dissipated in the package.
SOIC-8
1.0
SOT-23-5
0.5
–40
–20
0
20
40
60
AMBIENT TEMPERATURE – C
80
100
Figure 2. Maximum Power Dissipation vs.
Temperature for a Four-Layer Board
2
Airflow will increase heat dissipation effectively reducing JA.
Also, more metal directly in contact with the package leads from
metal traces, through holes, ground, and power planes, will reduce
the JA. Care must be taken to minimize parasitic capacitances
at the input leads of high speed op amps as discussed in the
board layout section.
RMS output voltages should be considered. If RL is referenced
to VS –, as in single-supply operation, then the total drive power
is VS IOUT.
If the rms signal levels are indeterminate, then consider the
worst case, when VOUT = VS /4 for RL to midsupply
PD = (VS ¥ I S ) +
MSOP-8
0
–60
PD = quiescent power + (total drive power – load power )
ÊV
ˆ V
V
PD = (VS ¥ I S ) + Á S ¥ OUT ˜ - OUT
RL ¯
RL
Ë 2
1.5
Figure 2 shows the maximum safe power dissipation in the package
versus the ambient temperature for the SOIC-8 (125∞C/W) and
SOT-23-5 (180∞C/W) packages on a JEDEC standard fourlayer board. JA values are approximations.
(VS /4)2
RL
In single-supply operation with RL referenced to VS–, worst case
is VOUT = VS /2.
OUTPUT SHORT CIRCUIT
Shorting the output to ground or drawing excessive current for
the AD8065/AD8066 will likely cause catastrophic failure.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package
Outline
AD8065AR
AD8065AR-REEL
AD8065AR-REEL7
AD8065ART-REEL
AD8065ART-REEL7
AD8066AR
AD8066AR-REEL7
AD8066AR-REEL
AD8066ARM-REEL
AD8066ARM-REEL7
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
5-Lead SOIC SOT-23
5-Lead SOIC SOT-23
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC MSOP-8
8-Lead SOIC MSOP-8
R-8
R-8
R-8
RT-5
RT-5
R-8
R-8
R-8
RM-8
RM-8
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8065/AD8066 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. B
–5–
Branding
Information
HRA
HRA
H1B
H1B
AD8065/AD8066–Typical Performance Characteristics
(Default Conditions 5 V, CL = 5 pF, RL = 1 k, VOUT = 2 V p-p, Temperature = 25C)
24
6.9
VO = 200mV p-p
G = +10
21
6.8
RL = 150
G = +2
6.7
18
VOUT = 0.2V p-p
G = +5
15
6.6
12
6.5
GAIN – dB
GAIN – dB
VOUT = 0.7V p-p
9
G = +2
6
3
6.4
VOUT = 1.4V p-p
6.3
6.2
G = +1
0
6.1
–3
6.0
–6
0.1
1
10
FREQUENCY – MHz
100
5.9
0.1
1000
4
VO = 200mV p-p
VO = 200mV p-p
G = +1
G = +2
8
VS = 5V
VS = 5V
7
GAIN – dB
2
GAIN – dB
100
9
6
VS = 5V
0
VS = 12V
VS = 12V
5
–4
4
1
10
FREQUENCY – MHz
100
3
0.1
1000
VS = 5V
6
–2
–6
0.1
1
10
FREQUENCY – MHz
1000
100
TPC 5. Small Signal Frequency Response for
Various Supplies (See Test Circuit 2)
TPC 2. Small Signal Frequency Response for
Various Supplies (See Test Circuit 1)
8
G = +1
G = +2
7
1
VS = 5V
VS = 5V
VO = 2V p-p
6
0
VS = 12V
GAIN – dB
GAIN – dB
10
FREQUENCY – MHz
TPC 4. 0.1 dB Flatness Frequency Response
(See Test Circuit 2)
TPC 1. Small Signal Frequency Response for
Various Gains
2
1
–1
VS = 12V
–2
VS = 5V
5
4
3
–3
2
–4
–5
0.1
1
1
10
FREQUENCY – MHz
100
0
0.1
1000
1
10
100
1000
FREQUENCY – MHz
TPC 6. Large Signal Frequency Response for
Various Supplies (See Test Circuit 2)
TPC 3. Large Signal Frequency Response for
Various Supplies (See Test Circuit 1)
–6–
REV. B
AD8065/AD8066
8
9
VO = 200mV p-p
CL = 25pF
6
G = +1
CL = 25pF
Rsnub = 20
CL = 55pF
6
CL = 5pF
4
CL = 20pF
0
CL = 5pF
CL = 25pF
2
GAIN – dB
GAIN – dB
3
0
–2
–3
–4
G = +2
–6
–6
VO = 200mV p-p
–8
0.1
–9
0.1
1
10
FREQUENCY – MHz
100
1000
1
10
FREQUENCY – MHz
TPC 10. Small Signal Frequency Response for
Various CLOAD (See Test Circuit 2)
TPC 7. Small Signal Frequency Response for
Various CLOAD (See Test Circuit 1)
8
8
R L = 100
VOUT = 0.2V p-p
7
6
VOUT = 2V p-p
4
6
0
GAIN – dB
2
GAIN – dB
1000
100
VOUT = 4V p-p
5
R L = 1k
4
–2
3
–4
2
–6
1
G = +2
VO = 200mV p-p
G = +2
0
1
10
FREQUENCY – MHz
100
1000
10
GAIN – dB
6
RF = RG = 1k,
RS = 500
2
RF = RG = 1k,
RS = 500,
CF = 3.3pF
0
G = +2
120
60
8
4
1000
RF = RG = 500,
RS = 250
OPEN-LOOP GAIN – dB
RF = RG = 500,
RS = 250,
CF = 2.2pF
12
60
PHASE
0
40
GAIN
20
–60
0
–120
VO = 200mV p-p
1
10
FREQUENCY – MHz
100
–20
0.01
1000
0.1
1
10
FREQUENCY – MHz
100
TPC 12. Open-Loop Response
TPC 9. Small Signal Frequency Response for
Various RF /CF (See Test Circuit 2)
REV. B
100
80
14
–4
0.1
10
FREQUENCY – MHz
TPC 11. Small Signal Frequency Response for
Various RLOAD (See Test Circuit 2)
TPC 8. Frequency Response for Various Output
Amplitude (See Test Circuit 2)
–2
1
0
–7–
–180
1k
PHASE – Degrees
–8
0.1
AD8065/AD8066
–30
–40
G = +2
–40
–50
–50
HD2 G = +2
DISTORTION – dBc
DISTORTION – dBc
–60
–60
HD2 R LOAD = 150
–70
HD2 R LOAD = 1k
–80
HD3 R LOAD = 1k
–90
HD3 R LOAD = 150
–100
HD3 G = +2
HD2 G = +1
–80
HD3 G = +1
–90
–100
–110
–120
0.1
1
10
FREQUENCY – MHz
–110
0.1
100
TPC 13. Harmonic Distortion vs. Frequency for
Various Loads (See Test Circuit 2)
1
–20
G = +2
VS = 12V
F = 1MHz
–40
–30
DISTORTION – dBc
HD3 R LOAD = 150
HD2 R LOAD = 150
–70
–80
–90
HD2 R LOAD = 300
–100
1
2
3
HD2 VO = 10V p-p
–60
–70
HD3 VO = 10V p-p
–80
–90
HD2 VO = 2V p-p
–110
–120
0
HD3 VO = 20V p-p
–50
–100
HD3 R LOAD = 300
–110
100
HD2 VO = 20V p-p
VS = 12V
G = +2
–40
–50
–60
10
FREQUENCY – MHz
TPC 16. Harmonic Distortion vs. Frequency for
Various Gains (See Test Circuits 1 and 2)
–30
DISTORTION – dBc
–70
HD3 VO = 2V p-p
–120
0.1
4 5 6 7 8 9 10 11 12 13 14 15
OUTPUT AMPLITUDE – V p-p
1
FREQUENCY – MHz
10
TPC 17. Harmonic Distortion vs. Frequency
for Various Amplitudes (See Test Circuit 2)
TPC 14. Harmonic Distortion vs. Amplitude for
Various Loads VS = ± 12 V (See Test Circuit 2)
50
100
VS = 12V
RL = 100
40
VS = 5V
NOISE – nV/ Hz
INTERCEPT POINT – dBm
45
35
30
VS = +5V
10
25
20
15
1
10
10
1
FREQUENCY – MHz
TPC 15. Third Order Intercept vs. Frequency
and Supply Voltage
100
1k
10k
100k
1M
FREQUENCY – Hz
10M
100M
1G
TPC 18. Voltage Noise
–8–
REV. B
AD8065/AD8066
CL = 5pF
G = +1
G = +1
CL = 20pF
20ns/DIV
50mV/DIV
20ns/DIV
50mV/DIV
TPC 22. Small Signal Transient Response ± 5 V
(See Test Circuit 1)
TPC 19. Small Signal Transient Response 5 V Supply
(See Test Circuit 11)
G = +1
VS = 12V
VOUT = 10V p-p
VOUT = 10V p-p
VOUT = 4V p-p
G5µs
= +2
VS = 12V
VOUT = 2V p-p
VOUT = 2V p-p
80ns/DIV
2V/DIV
TPC 23. Large Signal Transient Response
(See Test Circuit 2)
TPC 20. Large Signal Transient Response
(See Test Circuit 1)
G = 1
IN
80ns/DIV
2V/DIV
G = +1
IN
OUT
OUT
1.5V/DIV
1.5V/DIV
100ns/DIV
TPC 21. Output Overdrive Recovery
(See Test Circuit 3), VS = ± 5 V
REV. B
100ns/DIV
TPC 24. Input Overdrive Recovery
(See Test Circuit 1), VS = ± 5 V
–9–
AD8065/AD8066
VIN = 140mV/DIV
VIN = 500mV/DIV
VOUT – 2VIN
0.1%
+0.1%
0.1%
t=0
–0.1%
t=0
VOUT – 2VIN
2mV/DIV
2mV/DIV
64s/DIV
TPC 25. Long-Term Settling Time (See Test Circuit 8)
TPC 28. 0.1% Short-Term Settling Time (See Test Circuit 8)
–Ib
–10
42
36
30
24
18
12
6
0
BJT INPUT STAGE
+Ib
–Ib
FET INPUT STAGE
5
–15
–Ib
0
–5
–20
+Ib
Ib – pA
INPUT BIAS CURRENT – pA
Ib – A
0
–5
10ns/DIV
+Ib
–10
–15
–25
–20
–30
–30
–12 –10
–25
25
35
45
55
65
TEMPERATURE – C
75
85
–6 –4 –2
2
4
0
6
COMMON-MODE VOLTAGE – V
10
12
40
VS = 12V
N = 299
SD = 0.388
MEAN = –0.069
35
0.2
OFFSET VOLTAGE – mV
8
TPC 29. Input Bias Current vs. Common-Mode
Voltage Range*
TPC 26. Input Bias Current vs. Temperature
0.3
–8
30
VS = +5V
0.1
25
VS = 5V
20
0
15
–0.1
10
–0.2
–0.3
–14 –12 –10 –8
5
–6 –4 –2 0 2 4
6 8
COMMON-MODE VOLTAGE – V
10
12
0
–2.0
14
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
INPUT OFFSET VOLTAGE – mV
TPC 30. Input Offset Voltage
TPC 27. Input Offset Voltage vs. Common-Mode Voltage
*See Input and Output Overload Behavior section.
–10–
REV. B
AD8065/AD8066
–30
100
–40
OUTPUT IMPEDANCE – 10
CMRR – dB
–50
–60
VS = 12V
–70
VS = 5V
–80
1
G = +2
0.1
G = +1
0.01
–90
–100
0.1
1
10
FREQUENCY – MHz
0
100
100
OUTPUT SATURATION VOLTAGE – mV
OUTPUT SATURATION VOLTAGE – V
1M
100M
10M
80
0.25
VCC – VOH
0.20
0.15
0.10
VOL – VEE
0.05
0
10
20
I LOAD – mA
75
65
60
55
50
VOL – VEE
45
40
35
35
45
55
65
TEMPERATURE – C
85
75
TPC 35. Output Saturation Voltage vs. Temperature
0
0
–10
–10
–20
VIN = 2V p-p
G = +1
–20
CROSSTALK – dB
– PSRR
–30
+ PSRR
–40
–50
–60
–70
–30
–40
–50
B TO A
–60
–70
–80
A TO B
–80
–90
–100
0.01
VCC – VOH
70
30
25
40
30
TPC 32. Output Saturation Voltage vs. Output Load Current
PSRR – dB
100k
TPC 34. Output Impedance vs. Frequency
(See Test Circuits 4 and 6)
0.30
0.1
1
10
FREQUENCY – MHz
100
–90
0.1
1000
TPC 33. PSRR vs. Frequency (See Test Circuits 7 and 9)
REV. B
10k
FREQUENCY – Hz
TPC 31. CMRR vs. Frequency (See Test Circuit 5)
0
1k
1
10
FREQUENCY – MHz
100
TPC 36. Crosstalk vs. Frequency (See Test Circuit 10)
–11–
AD8065/AD8066
6.60
125
VS = 12V
120
VS = 5V
6.55
VS = 12V
6.50
OPEN-LOOP GAIN – dB
SUPPLY CURRENT – mA
115
6.45
VS = +5V
6.40
6.35
110
105
VS = +5V
100
95
VS = 5V
90
6.30
6.25
–40
85
80
0
20
40
TEMPERATURE – C
–20
60
80
0
10
20
ILOAD – mA
30
40
TPC 38. Open-Loop Gain vs. Load Current for
Various Supply Voltages
TPC 37. Quiescent Supply Current vs.
Temperature for Various Supply Voltages
Test Ciruits
SOIC Pinout
+VCC
+VCC
4.7F
4.7F
0.1F
0.1F
2.2pF
24.9
499
Rsnub
499
FET PROBE
Rsnub
VIN
VIN
49.9
FET PROBE
AD8065
AD8065
0.1F
1k
CLOAD
249
49.9
0.1F
1k
CLOAD
4.7F
4.7F
–VEE
–VEE
Test Circuit 1. G = +1
Test Circuit 2. G = +2
–12–
REV. B
AD8065/AD8066
+VCC
+VCC
4.7F
4.7F
0.1F
0.1F
2.2pF
499
VIN
499
499
499
49.9
VIN
FET PROBE
FET PROBE
AD8065
AD8065
49.9
249
0.1F
499
1k
499
0.1F
1k
4.7F
4.7F
–VEE
–VEE
Test Circuit 3. G = –1
Test Circuit 5. CMRR
+VCC
+VCC
4.7F
4.7F
0.1F
0.1F
24.9
499
AD8065
249
NETWORK ANALYZER S22
AD8065
NETWORK ANALYZER
S22
0.1F
0.1F
4.7F
4.7F
–VEE
–VEE
Test Circuit 4. Output Impedance G = +1
REV. B
499
Test Circuit 6. Output Impedance G = +2
–13–
AD8065/AD8066
+VCC
4.7F
VIN
1V p-p
0.1F
+VCC
49.9
24.9
24.9
FET PROBE
FET PROBE
AD8065
AD8065
1k
1k
0.1F
49.9
4.7F
VIN
1V p-p
–VEE
–VEE
Test Circuit 7. Positive PSRR
Test Circuit 9. Negative PSRR
+VCC
24.9
4.7F
FET PROBE
0.1F
24.9
1k
2.2pF
+5V
499
4.7F
499
0.1F
RECEIVE SIDE
976
VIN
249
AD8065
TO SCOPE
VIN
49.9
0.1F
0.1F
49.9
1k
49.9
4.7F
4.7F
–5V
DRIVE SIDE
–VEE
Test Circuit 8. Settling Time
Test Circuit 10. Crosstalk – AD8066
–14–
REV. B
AD8065/AD8066
2.2pF
499
499
5V
1.5V
4.7F
0.1F
FET PROBE
249
VIN
1k
49.9
1.5V
1.5V
Test Circuit 11. Single Supply
REV. B
–15–
AD8065/AD8066
THEORY OF OPERATION
Noninverting Closed-Loop Frequency Response
The AD8065/AD8066 are voltage feedback operational amplifiers
that combine a laser-trimmed JFET input stage with Analog
Devices’ eXtra Fast Complementary Bipolar process, resulting
in an outstanding combination of precision and speed. Supply
voltage range is from 5 V to 24 V. The amplifiers feature a
patented rail-to-rail output stage capable of driving within 0.5 V
of either power supply while sourcing or sinking up to 30 mA.
Also featured is a single-supply input stage that handles commonmode signals from below the negative supply to within 3 V of the
positive rail. Operation beyond the JFET input range is possible
because of an auxiliary bipolar input stage that functions with
input voltages up to the positive supply. The amplifiers operate
as if they have a rail-to-rail input and exhibit no phase reversal
behavior for common-mode voltages within the power supply.
Solving for the transfer function
With voltage noise of 7 nV/÷Hz and –88 dBc distortion for 1 MHz
2 V p-p signals, the AD8065/AD8066 are a great choice for high
resolution data acquisition systems. Its low noise, sub-pA input
current, precision offset, and high speed make it a superb preamp
for fast photodiode applications. The speed and output drive
capability of the AD8065/AD8066 also make them useful in
video applications.
VO
2p ¥ fcrossover (RG + RF )
=
VI
(RF + RG )s + 2p ¥ fcrossover ¥ RG
where fcrossover is the frequency where the amplifier’s open-loop
gain equals 0 db.
At dc
VO RF + RG
=
VI
RG
Closed-loop –3 dB frequency
f-3dB = fcrossover ¥
Inverting Closed-Loop Frequency Response
VO
-2p ¥ fcrossover ¥ RF
=
VI
s(RF + RG ) + 2p ¥ fcrossover ¥ RG
At dc
VO
R
=- F
VI
RG
Closed-Loop Frequency Response
The AD8065/AD8066 are classic voltage feedback amplifiers
with an open-loop frequency response that can be approximated
as the integrator response shown in Figure 3. Basic closed-loop
frequency response for inverting and noninverting configurations
can be derived from the shown schematics.
Closed-loop –3 dB frequency
f-3dB = fcrossover ¥
RF
VE
A
RG
VI
VO
80
OPEN-LOOP GAIN (A) – dB
RG
RF + RG
RF
RG
VI
RG
RF + RG
VE
A
VO
A = (2p fcrossover)/s
60
40
fcrossover = 65MHz
20
0
0.01
0.1
1
FREQUENCY – MHz
10
100
Figure 3. Open-Loop Gain vs. Frequency and Basic Connections
–16–
REV. B
AD8065/AD8066
The closed-loop bandwidth is inversely proportional to the
noise gain of the op amp circuit, (RF + RG)/RG. This simple
model is accurate for noise gains above 2. The actual bandwidth
of circuits with noise gains at or below 2 will be higher than
those predicted with this model due to the influence of other
poles in the frequency response of the real op amp.
RF
VI
Also see TPCs 13 to 17. The lowest distortion will be obtained with
the AD8065 used in low gain inverting applications, since this
eliminates common-mode effects. Higher closed-loop gains
result in worse distortion performance.
+VOS –
RG
Ib –
RS
A
VO
Input Protection
The inputs of the AD8065/AD8066 are protected with back-toback diodes between the input terminals as well as ESD diodes to
either power supply. This results in an input stage with picoamps
of input current that can withstand up to 1500 V ESD events
(human body model) with no degradation.
Ib+
Figure 4. Voltage Feedback Amplifier DC Errors
Figure 4 shows a voltage feedback amplifier’s dc errors. For
both inverting and noninverting configurations
Excessive power dissipation through the protection devices will
destroy or degrade the performance of the amplifier. Differential
voltages greater than 0.7 V will result in an input current of
approximately (|V+ – V–|– 0.7 V)/RI, where RI is the resistance
in series with the inputs. For input voltages beyond the positive
supply, the input current will be approximately (VI – VCC – 0.7)/RI.
Beyond the negative supply, the input current will be about
(VI – VEE + 0.7)/RI. If the inputs of the amplifier are to be
subjected to sustained differential voltages greater than 0.7 V or
to input voltages beyond the amplifier power supply, input
current should be limited to 30 mA by an appropriately sized
input resistor (RI) as shown in Figure 5.
Ê R + RF ˆ
Ê RG + RF ˆ
VO (error) = I b+ ¥ RS Á G
˜ - I b- ¥ RF + VOS Á R
˜
Ë RG ¯
Ë
¯
G
The voltage error due to Ib+ and Ib– is minimized if RS = RF储RG
(though with the AD8065 input currents at less than 20 pA
overtemperature, this is likely not a concern). To include
common-mode and power supply rejection effects, total VOS can
be modeled as
VOS = VOS
nom
+
Actual distortion performance depends on a number of variables:
∑ The closed-loop gain of the application
∑ Whether it is inverting or noninverting
∑ Amplifier loading
∑ Signal frequency and amplitude
∑ Board layout
DVS
DVCM
+
PSR
CMR
VOSnom is the offset voltage specified at nominal conditions. DVS is
the change in power supply from nominal conditions. PSR is the
power supply rejection. VCM is the change in common-mode
voltage from nominal conditions. CMR is the common-mode
rejection.
RI >
(| V+– V– | – 0.7V)
FOR LARGE | V+ – V– |
VI
RI
For the best settling times and the best distortion, the impedances
at the AD8065/AD8066 input terminals should be matched. This
minimizes nonlinear common-mode capacitive effects that can
degrade ac performance.
REV. B
RI >
AD8065
(VI – VEE – 0.7V)
30mA
(VI – VEE + 0.7V)
30mA
FOR VI BEYOND
SUPPLY VOLTAGES
VO
Wideband Operation
Test Circuits 1, 2, and 3 show the circuits used for wideband
characterization for gains of +1, +2, and –1. Source impedance at
the summing junction (RF储RG) will form a pole in the amplifier’s
loop response with the amplifier’s input capacitance of 6.6 pF.
This can cause peaking and ringing if the time constant formed is
too low. Feedback resistances of 300 W to 1 kW are recommended,
since they will not unduly load down the amplifier and the time
constant formed will not be too low. Peaking in the frequency
response can be compensated with a small capacitor (CF) in
parallel with the feedback resistor, as illustrated in TPC 9. This
shows the effect of different feedback capacitances on the peaking
and bandwidth for a noninverting G = +2 amplifier.
RI >
30mA
Figure 5. Current Limiting Resistor
Thermal Considerations
With 24 V power supplies and 6.5 mA quiescent current, the
AD8065 dissipates 156 mW with no load. The AD8065/AD8066
dissipate 312 mW. This can lead to noticeable thermal effects,
especially in the small SOT-23-5 (thermal resistance of 160CW).
VOS temperature drift is trimmed to guarantee a max drift of
17 mV∞C, so it can change up to 0.425 mV due to warm-up
effects for an AD8065/AD8066 in a SOT-23-5 package on 24 V.
Ib increases by a factor of 1.7 for every 10C rise in temperature.
Ib will be close to 5 times higher at 24 V supplies as opposed to
a single 5 V supply.
Heavy loads will increase power dissipation and raise the chip
junction temperature as described in the Maximum Power
Dissipation section. Care should be taken to not exceed the rated
power dissipation of the package.
–17–
AD8065/AD8066
Input and Output Overload Behavior
LAYOUT, GROUNDING, AND BYPASSING
CONSIDERATIONS
Power Supply Bypassing
The AD8065/AD8066 have internal circuitry to guard against
phase reversal due to overdriving the input stage. A simplified
schematic of the input stage, including the input-protection
diodes and antiphase reversal circuitry, is shown in Figure 6.
The circuit is arranged such that when the input common-mode
voltage exceeds a certain threshold, the input JFET pair’s bias
current will turn OFF, and the bias current of an auxiliary NPN
pair will turn ON, taking over control of the amplifier. When
the input common-mode voltage returns to a viable operating value,
the FET stage turns back ON, the NPN stage turns OFF, and
normal operation resumes.
The NPN pair can sustain operation with the input voltage up
to the positive supply, so this is a pseudo rail-to-rail input stage.
For operation beyond the FET stage’s common-mode limit, the
amplifier’s VOS will change to the NPN pair’s offset (mean of
160 mV, standard deviation of 820 mV), and Ib will increase to
the NPN pair’s base current up to 45 mA (see TPC 29).
Switchback, or recovery time, is about 100 ns, as shown in TPC 24.
The output transistors of the rail-to-rail output stage have circuitry
to limit the extent of their saturation when the output is overdriven.
This helps output recovery time. Output recovery from a 0.5 V
output overdrive on a ± 5 V supply is shown in TPC 21.
Power supply pins are actually inputs and care must be taken
so that a noise-free stable dc voltage is applied. The purpose of
bypass capacitors is to create low impedances from the supply to
ground at all frequencies, thereby shunting or filtering a majority
of the noise.
Decoupling schemes are designed to minimize the bypassing impedance at all frequencies with a parallel combination of capacitors.
0.1 mF (X7R or NPO) chip capacitors are critical and should be
as close as possible to the amplifier package. The 4.7 mF tantalum
capacitor is less critical for high frequency bypassing, and in most
cases, only one per board is needed at the supply inputs.
Grounding
A ground plane layer is important in densely packed PC boards to
spread the current minimizing parasitic inductances. However,
an understanding of where the current flows in a circuit is critical
to implementing effective high speed circuit design. The length
of the current path is directly proportional to the magnitude of
parasitic inductances and therefore the high frequency impedance of the path. High speed currents in an inductive ground
return will create an unwanted voltage noise.
VCC
TO REST OF AMP
VTHRESHOLD
VBIAS
VN
VP
S
S
VEE
Figure 6. Simplified Input Stage
–18–
REV. B
AD8065/AD8066
The length of the high frequency bypass capacitor leads is most
critical. A parasitic inductance in the bypass grounding will
work against the low impedance created by the bypass capacitor.
Place the ground leads of the bypass capacitors at the same
physical location. Because load currents flow from the supplies
as well, the ground for the load impedance should be at the same
physical location as the bypass capacitor grounds. For the larger
value capacitors, which are intended to be effective at lower
frequencies, the current return path distance is less critical.
Leakage Currents
Poor PC board layout, contaminants, and the board insulator
material can create leakage currents that are much larger than
the input bias current of the AD8065/AD8066. Any voltage
differential between the inputs and nearby runs will set up
leakage currents through the PC board insulator, for example,
1 V/100 GW = 10 pA. Similarly any contaminants on the board
can create significant leakage (skin oils are a common problem).
To significantly reduce leakages, put a guard ring (shield) around
the inputs and input leads that are driven to the same voltage
potential as the inputs. This way there is no voltage potential
between the inputs and surrounding area to set up any leakage
currents. For the guard ring to be completely effective it must
be driven by a relatively low impedance source and should completely surround the input leads on all sides, above and below
using a multilayer board.
Another effect that can cause leakage currents is the charge
absorption of the insulator material itself. Minimizing the amount
of material between the input leads and the guard ring will help
to reduce the absorption. Also, low absorption materials, such as
Teflon® or ceramic, may be necessary in some instances.
REV. B
Input Capacitance
Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground.
A few pF of capacitance will reduce the input impedance at high
frequencies, in turn increasing the amplifier’s gain, causing
peaking of the frequency response or even oscillations, if
severe enough. It is recommended that the external passive
components that are connected to the input pins be placed as
close as possible to the inputs to avoid parasitic capacitance. The
ground and power planes must be kept at a small distance away
from the input pins on all layers of the board.
Output Capacitance
To a lesser extent, parasitic capacitances on the output can cause
peaking and ringing of the frequency response. There are two
methods to effectively minimize their effect.
1) As shown in Figure 7, put a small value resistor (RS) in series
with the output to isolate the load capacitor from the amp’s
output stage. A good value to choose is 20 W (see TPC 7).
AD8065
VI
RS = 20
VO
CL
Figure 7. Output Isolation Resistor
2) Increase the phase margin with higher noise gains or adding
a pole with a parallel resistor and capacitor from –IN to
the output.
–19–
AD8065/AD8066
CF
RF
IPHOTO
RSH = 1011
CM
CD
CS
VO
CM
VB
CF + CS
RF
Figure 8. Wideband Photodiode Preamp
Input-to-Output Coupling
The output signal traces should not be parallel with inputs in order
to minimize capacitive coupling between the inputs and output.
Wideband Photodiode Preamp
The preamp’s output noise over frequency is shown in Figure 9.
Figure 8 shows an I/V converter with an electrical model of a
photodiode. The basic transfer function is
I PHOTO ¥ RF
1 + sCF RF
1
f1 = 2R (C + C + C + 2C )
F
F
S
M
D
1
where IPHOTO is the output current of the photodiode, and the
parallel combination of RF and CF set the signal bandwidth.
The stable bandwidth attainable with this preamp is a function
of RF, the gain bandwidth product of the amplifier, and the total
capacitance at the amplifier’s summing junction, including CS and
the amplifier input capacitance. RF and the total capacitance
produce a pole in the amplifier’s loop transmission that can result
in peaking and instability. Adding CF creates a zero in the loop
transmission that compensates for the pole’s effect and reduces
the signal bandwidth. It can be shown that the signal bandwidth
resulting in a 45∞ phase margin (f(45)) is defined by the expression
f( 45 ) =
fCR is the the amplifier crossover frequency.
RF is the the feedback resistor.
CS is the the total capacitance at the amplifier summing junction
(amplifier + photodiode + board parasitics).
The value of CF that produces f(45) can be shown to be
CF =
fCR
f3 = (C + C + 2C + C ) /C
S
M
D
F
F
RF NOISE
f2
VEN (CF + CS + CM + 2CD)/CF
f3
f1
VEN
NOISE DUE TO AMPLIFIER
FREQUENCY – Hz
fCR
2p ¥ RF ¥ CS
where:
f2 = 2R C
F F
VOLTAGE NOISE – nV/ Hz
VOUT =
The frequency response in this case will show about 2 dB of
peaking and 15% overshoot. Doubling CF and cutting the bandwidth in half will result in a flat frequency response, with about
5% transient overshoot.
Figure 9. Photodiode Voltage Noise Contributions
The pole in the loop transmission translates to a zero in the amplifier’s noise gain, leading to an amplification of the input voltage
noise over frequency. The loop transmission zero introduced by
CF limits the amplification. The noise gain’s bandwidth extends
past the preamp signal bandwidth and is eventually rolled off by
the decreasing loop gain of the amplifier. Keeping the input terminal
impedances matched is recommended to eliminate commonmode noise peaking effects, which will add to the output noise.
CS
2p ¥ RF ¥ fCR
–20–
REV. B
AD8065/AD8066
Table I. RMS Noise Contributions of Photodiode Preamp
Contributor
RMS Noise with RF = 50 kW,
CS = 15 pF, CF = 2 pF
Expression
64.5 mV
2 ¥ 4 kT ¥ R F ¥ f2 ¥ 1.57
RF (2)
2.4 mV
Amp to f1
ven ¥
f1
Amp (f2–f1)
ven ¥
(C S + C M + C F + 2 C D )
¥
CF
f2 – f1
31 mV
Amp (past f2)
ven ¥
(C S + C M + C D + 2 C F )
¥
CF
f3 ¥ 1.57
260 mV
270 mV
Total
Integrating the square of the output voltage noise spectral density
over frequency and then taking the square root allows users to
obtain the total rms output noise of the preamp. Table I summarizes
approximations for the amplifier and feedback and source resistances. Noise components for an example preamp with RF = 50 kW,
CS = 15 pF, and CF = 2 pF (bandwidth of about 1.6 MHz) are
also listed.
VCC
0.1F
4.7F
RS1
1/2
VN
2.2pF
AD8066
0.1F
4.7F
R2
500
VCC
VEE
0.1F
R1
4.7F
500
RF = 500
RG
0.1F
R3
RF = 500
VEE
500
VCC
0.1F
4.7F
R4
500
1/2
RS2
VP
2.2pF
AD8066
0.1F
4.7F
VEE
Figure 10. High Speed Instrumentation Amplifier
REV. B
VO
AD8065
–21–
4.7F
AD8065/AD8066
High Speed JFET Input Instrumentation Amplifier
Video Buffer
Figure 10 shows an example of a high speed instrumentation
amplifier with high input impedance using the AD8065/AD8066.
The output current capability and speed of the AD8065 make it
useful as a video buffer, shown in Figure 11.
The dc transfer function is
The G = +2 configuration compensates for the voltage division of
the signal due to the signal termination. This buffer maintains
0.1 dB flatness for signals up to 7 MHz, from low amplitudes
up to 2 V p-p (TPC 4). Differential gain and phase have been
measured to be 0.02% and 0.028∞ at ± 5 V supplies.
VOUT
Ê 1 + 1000 ˆ
= (VN - VP ) Á
˜
Ë RG ¯
For G = +1, it is recommended that the feedback resistors for the
two preamps be set to a low value (for instance 50 W for 50 W
source impedance). The bandwidth for G = +1 will be 50 MHz.
For higher gains, the bandwidth will be set by the preamp, equaling
Inamp-3dB = ( fCR ¥ RG ) / (2 ¥ RF )
VS
0.1F
249
VI
Common-mode rejection of the inamp will be primarily determined by the match of the resistor ratios R1:R2 to R3:R4. It can
be estimated
VO
(d1 - d2)
=
VCM (1 + d1) d2
4.7F
75
AD8065
75
0.1F
4.7F
VO
VS
2.2pF
The summing junction impedance for the preamps is equal to
RF储0.5(RG). This is the value to be used for matching purposes.
499
499
Figure 11. Video Buffer
–22–
REV. B
AD8065/AD8066
OUTLINE DIMENSIONS
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
8
5
1
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.33 (0.0130)
COPLANARITY
SEATING
0.10
PLANE
0.50 (0.0196)
45
0.25 (0.0099)
1.75 (0.0688)
1.35 (0.0532)
8
0.25 (0.0098) 0 1.27 (0.0500)
0.41 (0.0160)
0.19 (0.0075)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
5-Lead Plastic Surface Mount Package [SOT-23]
(RT-5)
8-Lead microSOIC Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Dimensions shown in millimeters
3.00
BSC
2.90 BSC
5
4
8
1
2
3
0.65 BSC
1.90
BSC
1.10 MAX
0.15
0.00
1.45 MAX
0.50
0.30
SEATING
PLANE
0.22
0.08
10
0
0.38
0.22
COPLANARITY
0.10
0.60
0.45
0.30
0.23
0.08
8
0
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
COMPLIANT TO JEDEC STANDARDS MO-178AA
REV. B
4
PIN 1
0.95 BSC
0.15 MAX
4.90
BSC
1
PIN 1
1.30
1.15
0.90
5
3.00
BSC
2.80 BSC
1.60 BSC
–23–
0.80
0.40
AD8065/AD8066
Revision History
Location
Page
2/03—Data Sheet changed from REV. A to REV. B.
Changes to Test Circuit 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Changes to Test Circuit 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Changes to Noninverting Closed-Loop Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Changes to Inverting Closed-Loop Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Updated Figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
C02916–0–2/03(B)
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to Figure 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Changes to Figures 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Changes to Figure 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Changes to High Speed JFET Instrumentation Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Changes to Video Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8/02—Data Sheet changed from REV. 0 to REV. A.
Added AD8066 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Added SOIC-8 (R) and MSOP-8 (RM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
New Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edits to TPCs 18, 25, and 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
New TPC 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Added Test Circuits 10 and 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PRINTED IN U.S.A.
MSOP (RM-8) added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
–24–
REV. B
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