EE201L_ClassNotes_Ch2.fm
Exercise for fun: Explain how the two-way stair-case light control circuit works.
2nd Floor
SPDT
110V
AC
SPDT
SPDT
1st Floor
SPDT
Now complete the three-way stair-case light control circuit below.
3rd
Floor
SPDT
110V
AC
SPDT
2nd
Floor
SPDT
DPDT
1st
Floor
DPDT
SPDT
Hint: Wire-up the DPDT so as to make
a Straight/Cross connection:
Straight
3
Cross
How many SPDTs and how many
DPDTs you think you need to
control one light-bulb common to
a 10-floor staircase. Total 11 switches.
LEDs (Light-Emitting Diodes)
1.6V
I
LED is a non-linear device (see the V-I
10mA
RED
characteristic). Since current increases steeply
LED
Cathode (-)
Anode (+)
V
once you cross the threshold voltage, we need a
current limiting resistance (example: 330 ohms resistance) wired in series with the LED.
Sinking method to drive
an LED is preferred.
Sourcing method to drive
an LED is not desirable.
A
B
74LS08
+5V
Voh (typ) = 3.4V
330 Ω
A
B
Typical VOL = 0.25V
3.4V – 1.9V
Current = ----------------------------- = 4.5mA
330Ω
4.5mA exceeds |IOHmax| of 0.4mA.
1/30/07
74LS00
330 Ω
5.0V – 1.9V – 0.25V
Current = ------------------------------------------------- = 8.6mA
330Ω
8.6mA is not too far from |IOLmax| of 8.0mA.
EE201L Class Notes - Chapter #2 Page 32 / 40
C Copyright 2007 Gandhi Puvvada
EE201L_ClassNotes_Ch2.fm
Is a buffer better than an ordinary gate in driving an LED? _____ (Yes/No).
The buffer has ______ (1/2/3) times drive
capability compared to an ordinary gate.
The buffer ______________ (also finds it
difficult to / can easily) drive an LED in
sourcing mode.
74LS00
Ordinary Gate
IOHmax = -0.4mA
IOLmax = 8.0mA
74LS37
Buffer Gate
IOHmax = -1.2mA
IOLmax = 24.0mA
So the best method to drive an LED is to use choice # ________________.
Choice #1:Use an ordinary gate’s sourcing capability.
Choice #2:Use an ordinary gate’s sinking capability.
Choice #3:Use a buffer gate’s sourcing capability.
Choice #4:Use a buffer gate’s sinking capability.
4
Totem-pole output stage of a gate
"TRANSISTOR" is the most basic element of all electronic circuitry. It
has three legs: BASE, COLLECTOR and EMITTER. Shown on the side
is a npn bipolar transistor.
Collector
Base
H
A transistor acts like a switch in a digital circuit. It either conducts or does
not conduct. If the BASE is held at HIGH voltage, it conducts from
collector to the emitter.
VCC (=5V) VCC
50Ω
’S00
VCC
3.5 kΩ
A
VCC
50 Ω
50 Ω
Source
900 Ω
2.8 kΩ
Source
Transistor
Y
Y
B
250 Ω
GND
74S00 2-input NAND from TI
www.ti.com
1/30/07
Y
Y=?
Y=?
Sink
500 Ω
Sink
Transistor
Emitter
American
Indian
Totempole
GND
Totem-pole
output stage
EE201L Class Notes - Chapter #2 Page 33 / 40
GND
GND
C Copyright 2007 Gandhi Puvvada
EE201L_ClassNotes_Ch2.fm
5
Open-collector output stage:
Suppose you want to generate Y = A B
We know we can do like this.
A
B
C D.
What happened if we do like this?
A
B
Y
C
D
C
D
?
Can we connect outputs
of two gates together
as shown? Yes / No
VCC
Source
50 Ω
ON
Sink
Y
OFF
Y
GND
Y
VCC
Source
50 Ω
OFF
Sink
Y
ON
GND
Short Circuit ???
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EE201L Class Notes - Chapter #2 Page 34 / 40
C Copyright 2007 Gandhi Puvvada
EE201L_ClassNotes_Ch2.fm
To avoid conflict between the blowers and the vacuum pumps,
let us remove the blowers!
Well, the blowers are there originally for a reason. If we remove the blowers, who will
create high pressure?
Let us install a small (weak) blower on the common line. This blower is ON all the
time. Also assume that it is specially designed so that it does not get overloaded.
If any of the vacuum pumps is on, because the vacuum pump is much stronger than the
small (weak) blower, the output pressure will be low. But if both vacuum pumps are
off, the small external blower will build-up the output pressure slowly to high pressure.
By analogy, we remove the source
transistors in the totem-pole output
stage of the NAND gates. The role of
the external blower is held by the
external pull-up resistance (usually
10Kohms) here.
Such gates without source transistor are
called "open-collector
output gates" because the
collector leg of the sink
transistor is left "open"
in the output-stage.
VCC = 5V
10KΩ
B
Imaginary AND gate
formed by the
wire-interconnection
A
Y
C
D
WIRE-ANDing
The wire-interconnection of the outputs of the open-collector gates is called
WIRE-ANDing, as it forms an imaginary AND operation of the outputs it connects.
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EE201L Class Notes - Chapter #2 Page 35 / 40
C Copyright 2007 Gandhi Puvvada
EE201L_ClassNotes_Ch2.fm
6
Exercise using the open-collector gates:
6.1
Draw gate-level logic to produce
G = (A + B) (C D) (E F)
using as few gates as possible,
using (a) Totem-pole output gates (b) Open-collector output gates
Open-Collector
Totem-pole
74LS01
74LS00
74LS03
74LS00
74LS05
74LS04
74LS09
74LS08
74LS12
74LS10
74LS22
74LS20
74LS33
74LS02
74LS03 is pin-for-pin
compatible with 74LS00
6.2
Find the logic function produced by the following logic. Point-out any errors.
’LS03
’LS00
A
B
C
D
6.3
C
D
F1
’LS09
’LS05
F2
E
The following logic is built using totem-pole output gates. Can you take advantage of WIREANDing in open-collector output gates and reduce the gate count (and there by cost)?
A
B
C
D
E
F
G
H
1/30/07
’LS03
A
B
’LS00
’LS08
’LS02
’LS00
’LS11
F3
’LS08
F4
EE201L Class Notes - Chapter #2 Page 36 / 40
C Copyright 2007 Gandhi Puvvada
EE201L_ClassNotes_Ch2.fm
7
A very common and useful application of open-collector gates in the design of systems
with multiple add-on cards:
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EE201L Class Notes - Chapter #2 Page 37 / 40
C Copyright 2007 Gandhi Puvvada
EE201L_ClassNotes_Ch2.fm
8
Gates with Tristate outputs, Forming Tri-state buses:
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EE201L Class Notes - Chapter #2 Page 38 / 40
C Copyright 2007 Gandhi Puvvada
EE201L_ClassNotes_Ch2.fm
1/30/07
EE201L Class Notes - Chapter #2 Page 39 / 40
C Copyright 2007 Gandhi Puvvada