Lesson 03: PS/2 Keyboard Interfacing
Introduction
1.
In this lesson, we will explain the communication protocol and scan codes used by a PS/2 (IBM Personal
System/2) keyboard.
2. PS/2 Communication Protocol
A PS/2 device and its host (i.e. a DE2-70 board or a computer) communicate with each other using 6-pin miniDIN connectors as shown below.
Pin
1
2
3
4
5
6
Function
Data
Not connected
GND
+5 V
Clock
Not connected
Pin diagram of a PS/2 Pin diagram of a PS/2 male
female connector*
connector*
* source: http://www.burtonsys.com/PS2_keyboard_and_mouse_mini-DIN-6_connector_pinouts.html
We will only look at PS/2 keyboard to its host communication. A PS/2 keyboard communicates with a host
device using 2 signals:
• A data signal
• A clock signal
Each data byte is known as a scan code and it is is sent serially using an 11-bit ‘packet’ on the data line. When
neither the keyboard nor the computer needs to send data, the data line and the clock line are High (inactive).
The transmission of a single scan code (or an 11-bit packet) consists of:
•
•
•
•
A start bit (logic ‘0’)
Eight data bits in low to high bit order (bit 0 or LSb first)
An odd parity bit
A stop bit (logic ‘1’)
The following sequence of events occurs during a transmission of a command by the keyboard:
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1. The keyboard checks to ensure that both the clock and keyboard lines are inactive. Inactive is indicated
by a High state. If both are inactive, the keyboard prepares the 'start' bit by dropping the data line
Low.
2. The keyboard then drops the clock line Low for approximately 35us.
3. The keyboard will then clock out the remaining 10 bits at an approximate rate of 70us per clock (~14
kHz) period. Note that the keyboard drives both the data and clock line.
4. The host (or the receiving system) is responsible for recognizing the ‘start’ bit and for receiving the
serial data. If the keyboard wishes to send more data, it restarts the sequence by sending a new ‘start’ bit.
This pattern repeats until the keyboard is finished sending data at which point the clock and data lines
will return to their inactive High state.
Question: What is the transmission time of a scan code?
11 * 70 us = 770 us
Question: What is the data rate (bytes per second) of a PS/2 device?
1/(770 us)= 1298 bytes per second
An example of the basic timing diagram of transmitting an data packet from a PS/2 keyboard to its host is
shown in the Fig. 1 below. Note that the least significant bit (LSb) is sent first.
Fig.1. Timing diagram of a PS/2 transmission.
Question: What is the scan code (in hex) described in the timing diagram below.
Idle
Clock
Idle
Data
101000112 = A316 = 10 x 16 + 3 = 16310
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Question: What is the scan code (in hex) described in the timing diagram below.
Idle
Clock
Idle
Data
000000002 = 0016 = 010
Question: What is the scan code (in hex) described in the timing diagram below.
No new scan code received from the PS/2 keyboard.
3. Design of a PS/2 Keyboard Receiving Subsystem
A simple receiving system can be achieved by implementing a ps/2 keyboard controller with a finite state
machine (FSM). Noise in the communication wires can cause glitches in both the data and clock lines. Since
the receiving system relies on the clock signal form the PS/2 keyboard to drive the data bits, we will need to
consider a filtering circuit for the clock signal. The general block diagram of a typical PS/2 receiving system is
shown in Fig. 2.
Clock Filter
CLOCK_50
KB_CLK
KB_CLK_FILTERED
scan_code_ready
Keyboard Controller
scan_code(7:0)
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KB_DATA
Fig.2. Block diagram of the PS/2 keyboard receiving sub-system.
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where
•
•
•
•
•
KB_CLK is the clock signal from the PS/2 keyboard,
KB_DATA is the data signal from the PS/2 keyboard,
CLOCK_50 is the clock signal from the host (50 MHz on the DE2-70 board),
scan_code is the scan code (8-bit data) received from the PS/2 keyboard and assembled in the
controller.
scan_code_ready is an output signal to other logic to indicate that a new and valid scan code is
available. This signal should be asserted (active) for 1 clock cycle.
A. Design of a Noise Filtering Circuit
When data is transmitted, a certain amount of noise is mixed with the actual digital signals. For applications that
require accurate values from digital inputs, it is necessary to incorporate digital filters into the circuits to remove
noise from the input signals. The purpose of the filter is to determine if an input signal has been stable in the
same state (0 or 1) for at least a certain period of time (i.e. at least 16 consecutive clock cycles). The filtered
output signal is then used as a noise-free signal in other components. We will need to design a filter circuit for
the KB_CLK signal from the PS/2 keyboard. For this design, if KB_CLK is in a state (0 or 1) for at least 16
consecutive CLOCK_50 cycles, it is considered as noise-free and the appropriate output should be updated for
the filtered output KB_CLK_FILTERED.
The VHDL code for the filter circuit:
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Now, complete the timing diagram below.
B. Design of a PS/2 Keyboard Controller
The controller waits for the start bit, then converts the next eight serial data bits to a scan code, and outputs the
8-bit scan code to the scan_code bus. The scan_ready signal is set to ‘1’ for 1 clock cycle whenever a new scan
code is received.
This simple controller can be implemented using a finite state machine. The controller will require an internal
register to assemble the scan code bits during the transmission.
Draw a state diagram or an ASM diagram for this controller.
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reset
Inputs:
KB_DATA: data bit from the keyboard
Wait
Internal registers:
Count: it keeps track of number of bits
received
R: a register to store the scan code
Count = 0
No
Outputs:
scan_code_ready: signal to indicate a new
and valid scan_code is available.
scan_code: scan code received from the
keyboard.
KB_DATA = ‘0’
Yes
Receive
R (Count)= KB_DATA
Count = Count +1
No
COUNT = 8
Yes
Ready
scan_code_ready
scan_code = R
Fig.3. An ASM diagram of a finite state machine to interface with the PS/2 keyboard.
Question: How many clock cycles will the scan_code_ready signal be active?
One clock cycle (in state ready).
4. PS/2 Keyboard Scan Code
When a key of a PS/2 keyboard is pressed, a ‘Make’ code is sent. The ‘Make’ code is normally 1 byte wide and
represented by two hexadecimal digits. The ‘Make’ codes of the main part of a PS/2 keyboard are shown in Fig.
4. For example, the ‘Make’ code of the ‘A’ key is 0x1C (or 1C16). Some special purpose keys, which are known
as the extended keys, can have 2 to 4 bytes. For example, the make code for the right control key is 0xE014.
When a key is released, a ‘Break’ code is sent. For most keys, the ‘Break’ code is a 2 byte packet of F0
followed by the ‘Make’ code of that key. For example, the break code of the ‘A’ key is 0xF01C.
When a key is held down continuously, the ‘Make’ code is transmitted repeatedly.
Examples:
• When we press and release the ‘A’ key, the keyboard transmits
0x1CF01C
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•
When we hold the ‘A’ key down for a while before releasing it, the keyboard transmits
0x1C1C…….1CF01C
•
When we first press the ‘Shift’ key and then the ‘A’ key, and release the ‘A’ key and release the ‘Shift’
key, the transmitted scan code sequence is
0x121CF01CF012.
Note that this sequence is how we normally obtain an upper case A. Note that there is no special code to
distinguish the lowercase and uppercase keys. It is the responsibility of the host device to keep track
of whether the shift key is pressed and to determine the case accordingly.
Fig.4. Scan code of the PS/2 keyboard. (source: Beyond Logic).
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