Measurement of External Jitter for True SNR
Estimation of A/D Converters
Turker Kuyel, PhD
Senior Member of the Technical Staff
Design Manager
Data Acquisition Products
High Performance Analog
2/17/2005
Outline
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What is jitter
Why is it important
How can it be reduced
How can it be measured
How can it be removed
References
2/17/2005
What is time jitter?
• Time Jitter is a measure of temporal noise
– A signal must be periodic to have jitter
– The period of a signal can be estimated within a time interval
• Uncertainty principle implies ∆F* ∆T=1
• A long time period is required to estimate a signal period with
low uncertainty
– Once the period is estimated (known), we can talk about
ideal “zero crossings”
– Jitter is the temporal deviation of the actual zero crossings
from the ideal zero crossings.
• Analyzed statistically
• Can be deterministic or random
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In what forms timing jitter can occur?
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Period of the signal might drift with time
– Phase locked loop, close-in phase noise
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There may be random variations of the zero crossings
• Can be normally distributed
• Other distributions can be observed
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There may be deterministic variations of the zero crossings
• Can be dependent on the architecture of the periodic waveform
generator:
• For example: Every 4Nth clock can be Gaussian around the desired
period, but 4N+1, 4N+2, 4N+3 clocks can have deterministic errors.
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Usually the answer is “all of the above”
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Do we care?
• Yes!
• Jitter is critical in high-speed digital
– 30ps rms jitter can be considered as “bad” for SERDES
• Jitter is critical in high-performance data converters
– 0.3ps rms can be considered as “bad” for ADS55XX
– ADC applications require 2-3 orders of magnitude better jitter
than high-speed digital applications
– Random and deterministic Jitter makes Signal-to-Noise
Ratio (SNR) of an ADC (DAC) look bad.
– Deterministic jitter makes Spurious Free Dynamic Range
(SFDR) of an ADC (DAC) look bad
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Jitter noise can exceed quantization noise
• Quantization noise of an N-bit ADC
SNR maxquantization = 6.02 * N + 1.76
• Jitter noise of an N-bit ADC
SNR max jitter = −20 log( 2πfε )
• Find ‘quantization noise equivalent’ jitter
1
ε <
,
0 .3 N
2 π f 10
f = input _ frequency
ε = rms _ jitter
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Jitter Tolerance of Nyquist ADCs (ps rms)
Fin
8bit
10bit
12bit
14bit
16bit
18bit
20bit
22bit
24bit
10KHz
64512
16128
4032
1008
252
63
16
4
1
100KHz
6451
1612
403
101
25.2
6.3
1.6
0.4
0.1
1MHz
645
161
40.3
10.1
2.52
0.63
0.16
0.04
0.01
10MHz
64
16.1
4.03
1.01
0.252
0.06
0.01
0.00
0.00
100MHz
6.4
1.61
0.40
0.10
0.025
0.006
0.00
0.00
0.00
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Critical Example: ADS5500
• 14-bit 125MSPS ADC
– Sampling speed is irrelevant
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Fin = 70MHz
SNR = 70dB typical @ Fin = 70MHz
Close to 12-effective-bits performance
SNR TESTING:
– Total jitter must be under 400 fempto-seconds !!!
– Can we guarantee that it really is ???
– If not, chances are, we are measuring jitter effects. We are
not measuring true SNR of ADS5500.
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Critical Example: ADS5500
• What needs to be under 400 fempto-seconds?
• In other words, what does “total jitter” mean?
• TOTAL JITTER is the RSS SUM of:
– External jitter of the clock source
– External jitter of the input source
– Internal jitter of the ADC
• S/H aperture jitter
• Internal clock jitter
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Critical Example: ADS5500
• Key Specifications: SFDR and SNR
• SNR is affected by random and deterministic jitter
– Random jitter show-up as a raised noise floor
– Deterministic jitter show up a “forest” of small tones.
• SFDR is affected by deterministic jitter
– Some of the deterministic jitter tones could be so high, it
could present the “worst spur”.
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Where do we look for jitter?
• Order of Importance:
1) Clock generator (ATE). This can be terrible.
2) Input generator (ATE)
3) Output drive load (di/dt) on the DUT board
4) Bypass and drive circuitry for Vref+ and Vref5) Chip design
6) PCB Layout. A simple PCB layout with a thick single ground
plane is the ‘last’ place to chase jitter. Do not start with this
one.
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How do we REDUCE jitter?
• Internal to ADC:
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Differential clock architecture
Differential input architecture
Fast clock rise/fall times.
Good chip layout, minimizing supply bounce and
coupling.
– Lowest possible digital signal amplitude (LVDS)
– Lowest possible digital signal rise/fall times.
– Good pinout. Lowest possible inductance.
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How do we REDUCE jitter?
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Frequency reference:
– Use an oven controlled crystal oscillator. Better than an
“atomic clock” over short time frames. Data capture time is
usually around 100us.
– Phase-lock the clock generator, input generator and capture
instrument to the oven-controlled-crystal.
– Wenzel Associates, www.wenzel.com makes the lowest jitter
OCXOs, according to AeroFlex Comstron. Comstron is the
synthesizer in Teradyne’s Catalyst test systems.
– On an ATE, lock to the 10MHz reference of the ATE. If the
ATE does not synchronize to its frequency reference, one
can find the correct capture window with an edge placement
search
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How do we REDUCE jitter?
• Input Generator:
– Use crystal, pll, mixer based systems for lowest
jitter: HP8662 has the lowest close-in phase noise.
HP8644B has better noise floor at higher
frequencies. HP8644B is also relatively clean from
non-harmonic spurs.
– Wenzel Associates can design custom arrays of
crystal oscillators for fixed frequencies, for
absolute lowest jitter (-173dB noise floor).
– Use a band-pass filter, crank the input amplitude.
2/17/2005
How do we REDUCE jitter?
• Clock Generator:
– Use HP8644B or alike.
• PN9000 measured HP8644B jitter to be 0.47ps. This includes
PN9000 noise also.
– Use a steep narrowband band-pass filter to reduce jitter. A
crystal filter is the most suitable.
– Route the clocks differentially.
– Gain the clocks on-chip.
– To observe the effects of gaining the clock, HP8133A clock
generator could be used (60ps rise time). HP8133A needs a
secondary HP8644B to set the frequency arbitrarily.
HP8133A jitter is measured around 1ps rms.
2/17/2005
How can we MEASURE jitter?
• Fine-coarse counter based time domain techniques:
Wavecrest DTS, 10ps accurate
• Flash ADC based digital scopes: LeCroy, Tektronix,
etc. 8-bits 4GSPS, 2-3 ps accurate.
• PLL and mixer based techniques: Comstron PN9000,
0.2ps accurate. Difficult to use. Performance as good
as its frequency synthesizer
• CommsADC based TI methods, 0.2ps accurate
• Better than 0.1ps ? Pure Research. Alfio Zanchi and
Yiannis Papantonopoulos reported 25 fs.
2/17/2005
How do we measure TOTAL jitter?
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Various methods are available at TI.
– Dual-SNRs (Burns, Kao, Kuyel) (1)
– Dual-Histograms (Kuyel) (2)
– Unwrap-FFT (Pearson. Method uses same dataset) (3)
To sensitize to aperture jitter and clock jitter, band-pass filter the
input, and use an Fin near the band-edge of the input S/H. This
means heavy undersampling of high Fin to increase sensitivity
to jitter. Assuming input is ideal, gives aperture jitter + clock
jitter.
In 1997, TLC876 (10bit 20MHz ADC with 250MHz BW)
measured the Teradyne HSD50 jitter around 12ps rms (1).
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Undersampled Sine Wave Capture
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Low-slew-rate Histogram
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High-slew rate Histogram
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Time Differential Sampling
ADC CLOCK
Transformer
Termination
Low-Jitter Sinewave
RF Splitter
Transformer
Termination
ADC INPUT
2/17/2005
How do we REMOVE jitter?
• Test for random vs. correlated (deterministic) jitter.
• If random, it can be removed.
• If deterministic, tones can be deleted after careful
investigation.
• Frequency synthesis based systems are known to
generate random jitter.
2/17/2005
How do we tell random vs. deterministic?
• The difference between Pearson’s and Kuyel’s
techniques gives the deterministic jitter in an rms
sense.
• Undersample the capture waveform.
– Run jitter analysis at every mKth sample
– Run jitter analysis at every mK+1th sample
– Run jitter analysis at every mK+2 sample
– See if there is any difference in jitter readings.
– If there is, then deterministic jitter is present
• If the jitter is mostly random, then it could be
removed. OCXO jitter is random.
2/17/2005
How do we REMOVE random external jitter?
• Measure total jitter with one of the available methods
(dual-SNRs, dual-hist, FFT-unwrap)
• Remove total jitter noise from the SNR calculations
• Measure internal jitter using Time Differential
Sampling technique
• Add internal jitter noise back into the SNR
calculations
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How do we measure Internal Jitter?
• Internal jitter is usually very low: TLC876 <1ps rms
• A high performance ADC should read ~0.1ps rms
• TIME DIFFERENTIAL SAMPLING (2):
– Use the same generator as signal and as clock.
– The capture waveform will be a noisy DC signal
– Delay the clock until minimum-slew-rate DC is captured. This
gives an indication of random noise in the system. This noise
is NOT internal jitter.
– Delay the clock until the maximum-slew-rate DC is captured.
This gives system noise + jitter noise.
– Internal_jitter_variance = MAXSR_variance –
MINSR_variance
– This technique can be extended to multiple points and curve
fitting results in more robust estimates (9)
2/17/2005
How do we remove EXTERNAL jitter?
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Run a random/deterministic analysis first
Measure TOTAL JITTER with dual-histograms
Measure INTERNAL JITTER with TDS
Subtract TOTAL JITTER and add INTERNAL JITTER
• Assuming even the best test setup, we may gain 12dB SNR, starting from ADS5500 and higher
2/17/2005
Some Jitter Measurement Results (1997-2004)
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A580 HSD channel: 11ps @ 20MHz (Measured with dual SNRs,
TLC876)
A580 HSD channel: 9ps @ 40MHz (Measured with dual-hist,
using THS1240, t0 divide-by-four)
A580 super-clock. 4.5ps @ 40MHz (Measured with dual-hist,
using THS1240)
Catalyst HSD channel: 33ps @ 65MHz (Measured with dualhist, using AD6640. Highly deterministic nature)
Catalyst pico-clock: 1.1ps @ 65MHz (Measured with dual-hist,
using AD6640)
HP8644B: 0.470ps @ 65MHz (measured with PN9000,
unfiltered)
HP8131A: 0.850ps @ 65MHz (Measured with PN9000)
2/17/2005
REFERENCES
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1) US 6,240,130 B1 (dual-SNR technique, Burns, Kao, Kuyel)
2) US 6,640,193 B2 (dual-hist, TDS, and removal techniques, Kuyel)
3) TI-Patent Pending (FFT-unwrap method, Chris Pearson)
4) LeCroy Digital Oscilloscopes “Accuracy in Time Jitter Measurements
with LeCroy Oscilloscopes”, LeCroy Corporation
5) Aeroflex Comstron Inc. “PN9000 Automated Phase Noise
Measurement Systems”
6) Aeroflex Comstron Inc.”Phase noise theory and Measurement”,
Apps note.
7) Wavecrest Corporation, “Digital Time Systems”
8) Rosing et al., “Off-chip Diagnosis of Aperture Jitter in Full-flash A/D
Converters, Feb. 1999, Jetta, pp. 1-8.
9) Zanchi and Papantonopoulos, “Measuring Sub-picosecond Jitter”,
CommsDesign, March 09, 2004
10) Wenzel Associates web page www.wenzel.com
11) Aeroflex Comstron web page www.aeroflex.com
2/17/2005