Slide -1
Capacitor Values
Which is Better: Use One Value Capacitor or
Three Different Values for the DPN?
"and why this is the wrong question.
Dr. Eric Bogatin,
Signal Integrity
Evangelist,
Bogatin Enterprises
Copies of this
presentation are
available on
www.beTheSignal.com
5/1/2012
 Bogatin Enterprises, a LeCroy Company 2012
www.beTheSignal.com
Slide -2
Capacitor Values
Overview
• Decoupling capacitors and the PDN
• The Problem we want to solve
• The key performance metric: the impedance profile
• The Bandini Mountain
• Impact of capacitor values
 Bogatin Enterprises, a LeCroy Company 2012
www.beTheSignal.com
Slide -3
Capacitor Values
The Power Delivery Network
Courtesy of Altera Corp
•
All the interconnect from Voltage Regulator
Module (VRM) to pads on the chip
•
Purpose:
Provide stable voltage to chip pads from DC to > BW
of the signals (rail collapse)
Provide low impedance return path for signals (ground
bounce, SSO, switching noise)
To help mitigate EMI emissions
 Bogatin Enterprises, a LeCroy Company 2012
www.beTheSignal.com
Slide -4
Capacitor Values
One Problem from Noise on
the PDN
500 MHz clock
Core PDN voltage noise– 200mv/div
Period of each clock
350ps
•
500 MHz clock (2 nsec
period)
•
Multiple drivers drawing
current through PDN at
500 Mbps, PRBS
•
PDN noise causes clock
jitter
100ps jitter/vertical div
In this case, ~ 1 nsec/v jitter
Ex: 100 mV PDN noise 100 psec jitter noise
Courtesy of Altera
 Bogatin Enterprises, a LeCroy Company 2012
www.beTheSignal.com
Slide -5
Capacitor Values
How to Break a PDN:
It’s the Peak Values that Cause Problems
Courtesy of Altera Corp
Core – 100mv/div
Measured impedance
profile from the chip
600 mV core PDN noise!
Yikes!
Peak
impedance
at 33 MHz
30 nsec
Core Logic activity
Microcode drives current draw with
high 33 MHz component
Courtesy of Altera
5
 Bogatin Enterprises, a LeCroy Company 2012
www.beTheSignal.com
Slide -6
Capacitor Values
Robust PDN Design Goal- Keep Peak
Impedances Below Target Threshold
1.2
1.0
If impedance profile is
everywhere below the
target impedance, PDN
noise will always be in
spec.
0.6
0.4
0.2
0.0
1E1
-0.2
0
20
40
Impedance, Ohms
Voltage
0.8
60
time, nsec
1
80
100
Target impedance
1E-1
1E-2
PDN impedance profile
1E-3
1E2
1E3
1E4
1E5
1E6
1E7
1E8
1E9
1E10
freq, Hz
 Bogatin Enterprises, a LeCroy Company 2012
www.beTheSignal.com
Slide -7
Capacitor Values
Examples of Measured
Bandini Mountains
L of the package leads, C of the on-die capacitance
SRF of the
on-package
capacitors
Courtesy of Altera Corp
Measured Impedance profile of core Vdd
From Intel Technology Journal, Nov 2005
 Bogatin Enterprises, a LeCroy Company 2012
www.beTheSignal.com
Slide -8
Capacitor Values
The Bandini Mountain:
The On-die Capacitance and Package
Lead Inductance Parallel Resonance
Connection to
the board
impedance
Bumps
Balls
PCB
Planes & Vias
& Vias
C on-die = 100 nF
Load
Package
Capacitor
Note: Lower L means lower peak impedance!
On-chip
Capacitance
Changing package lead inductance
L = 1 nH
With the board
impedance a dead
short
“Bandini Mountain” – Steve Weir
L = 0.1 nH
L = 0.01 nH
L = 0.001 nH
 Bogatin Enterprises, a LeCroy Company 2012
www.beTheSignal.com
Slide -9
Capacitor Values
Why PDNs Often “Work”
Target impedance = 2 Ohms
Target impedance = 0.4 Ohms
LVRM = 100 nH
RVRM = 0.005 Ohms
Con-die = 50 nF
Bulk C
On-chip
What the Chip Sees
Even with NO Decoupling
Capacitors
VRM
•
Why PDNs often work
If target impedance is high enough, may not need any board level decoupling capacitors
If target impedance is low, current spectrum may not have any large amplitudes at frequencies
where impedance is high
May be sufficient on-chip or on-package decoupling capacitance
www.beTheSignal.com
 Bogatin Enterprises, a LeCroy Company 2012
Slide -10
Capacitor Values
Which is Better:
3 caps, same value,
3 caps, different values?
VRM
Bulk
capacitors
Ceramic
decoupling
capacitors
PCB
Planes
Package
Which is better?
Chip
Including the whole ecology
How lucky do you feel?
What if the on-die cap is larger, smaller?
What if the package lead inductance is larger, smaller?
 Bogatin Enterprises, a LeCroy Company 2012
www.beTheSignal.com
Slide -11
Capacitor Values
Engineering the Bandini Mountain
•
Changing package
lead inductance
Chip-package design tradeoffs:
Increase on-die capacitance
Increase on-package capacitance
L = 1 nH
Decrease package lead inductance
•
L = 0.001 nH
At the board level
Not much: even a dead short shows a peak!
Reduce capacitor inductance (only if package
lead inductance is low)
Board as a dead short
R=1Ω
Make the board impedance look like a resistor
(decreasing the Q, damping the resonance)
R = 0.001 Ω
 Bogatin Enterprises, a LeCroy Company 2012
www.beTheSignal.com
Slide -12
Capacitor Values
Impedance Magnitude and Phase
C
L
R
L
The flatter the impedance
profile, the more it looks like a
resistor
R
C
 Bogatin Enterprises, a LeCroy Company 2012
www.beTheSignal.com
Slide -13
Capacitor Values
Impedance Profile and Phase
1 capacitor value
10 capacitor values
• Phase of the
Impedance profile
If you know the
impedance profile,
you know the phase
as well
Capacitive impedance,
phase is -90 degrees
Inductive impedance,
phase is +90 degrees
Flat impedance, phase
is ~ 0 degrees
The more resistive the
impedance profile, the
less the Bandini peak
impedance
 Bogatin Enterprises, a LeCroy Company 2012
www.beTheSignal.com
Slide -14
Capacitor Values
Impedance Profiles and the PDN
Ecology
Pkg + die
Pkg + die
•
To minimize the resonance
peaks, make the board
impedance look resistive =
flat impedance profile @
pkg-die resonance
•
If you don’t know the
package L or on-chip C, try
to make the board level
impedance profile flat up to
~ 100 MHz
•
The flatter the impedance
profile, the luckier you can
get
Just single value
capacitors
Just multiple
value capacitors
PDN ecology
PDN ecology
How do we sculpt a flat impedance profile with capacitors
and decrease ALL peak impedances?
 Bogatin Enterprises, a LeCroy Company 2012
www.beTheSignal.com
Slide -15
Capacitor Values
Summary
•
PDN noise contributes to bit errors and to jitter
•
Worse case voltage noise occurs when chip current spectral
peaks overlap impedance peaks
•
Peaks are the biggest problem to engineer away in PDN design
•
If you don’t engineer the impedance profile compared to the
target impedance, your design principle isO
“how lucky do you feel?
Key ingredient
 Bogatin Enterprises, a LeCroy Company 2012
www.beTheSignal.com
Slide -16
Capacitor Values
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Published by Prentice Hall, 2009
 Bogatin Enterprises, a LeCroy Company 2012
www.beTheSignal.com