HIGH-SPEED LOGIC CIRCUIT CONSIDERATIONS
w. H. Howe
General Electric Computer Department
Phoenix, Arizona
provements may com~ with machine organizations
which consume large amounts of circuits. These organizations are now becoming feasible due to increased reliability and the availability of low cost
devices through the semiconductor industry.
INTRODUCTION
This discussion is confined to circuits operating
at switching speeds sufficiently fast to require the
use of terminated transmission lines for all logic
interconnections other than to an adjacent device.
The discussion is further confined to significant
factors affecting circuit decisions in a high volume
commercial/industrial environment. Laboratory curiosities operating at absolute maximum speeds are
not considered in view of the extremely distorted
economics associated with experimental technologies. The factors under discussion are technology
considerations, economic considerations, logic arrays, power dissipation, and packaging media constraints. The discussion is not intended to be a
gross prediction of future practice, but rather a
snapshot of today's design considerations imposed
by present technology and Mother Nature's rather
rigid philosophy concerning the speed of light.
Since the transmission time through the interconnecting media is significant when compared to propagation delay time of the logic device, the physical
size of the system has some bearing on the definition of high speed. This discussion is concerned
with relatively large organizations such that a propagation delay time of 2 to 5 nanoseconds may be
considered high speed. More dramatic speed im-
TECHNOLOGY
The selection of a technology for circuit fabrication is heavily dependent upon timing, anticipated
volume, cost and required performance. The following -sequence of events usually occur in the development of a circuit family.
Device Availability. Either as a result of a specific
development contract or in the normal course of
funded research and development programs, an improvement in mask technology, process sequencing,
etc., permits a higher speed device to be fabricated
on an experimental basis. Historically, the device
has been first implemented as a transistor.
Circuit Design. The new device is exploited by the
user, as well as the manufacturer, to produce a desirable logic circuit. These circuits are generally
different since the user is not aware of all the process constraints nor the economic tradeoffs required
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for eventual success in the market place as a microcircuit.
User Selects Technology. If the user must exploit
his faster circuit as soon as possible, he may choose
immediate circuit implementation through the use
of one of the hybrid circuit technologies. The penalty for quick turn-around is higher cost in volume.
Meanwhile, the semiconductor manufacturer has
begun development of a silicon integrated circuit.
Manufacturer Announces Silicon Integrated Circuit.
The silicon circuit version may prove to be as fast,
or faster than the hybrid equivalent since he retains
control of all process optimization. The circuit development path is somewhat longer, but is being
reduced by the growing tendency on the part of
manufacturers not to disclose advanced technologies
until the silicon integrated circuit is well on its way
to market.
Let us, therefore, discuss technology in the light
of silicon integrated circuits. Silicon integrated circuit technology has been frequently described as a
cure-all for cost. Once, the circuits are in use, volume increases, causing costs to go down, increasing
the volume, etc., until the cost extrapolation goes
through zero. Some of these effects may be observed
in today's market where circuit costs are near one
dollar even at modest volumes. At one of the recent
conferences, several authors lamented the fact that
the longed-for impact of integrated circuits on the
computer business simply hadn't happened. A more
meaningful statement may well be that the impact of
the impact of the computer business on integrated circuits has not yet happened. The economic success of
these devices is highly volume-dependent; so much so,
in fact, that, to date, commercial computers are the
only logical market place for the latent high volume
all manufacturers may readily achieve. This relationship has caused a heavy emphasis on logic circuit and logic array development to reduce cost to
the fullest extent. Extensive research efforts have
been initiated to search for logic arrays which are
highly efficient, low in cost, and high in speed to
satisfy the needs of the computer industry. However, the tradeoffs in speed, cost, logic complexity,
and technology are inherent to the design of systems and are not separable in spite of the good intentions of the semiconductor manufacturers or the
abstract logicians. We would like to point out brief1y some of the tradeoffs available. One of the most
1965
interesting and significant paradoxes of the new
technology is the apparent reconciliation of a desire
to achieve high speed and low cost. The parameters
which yield high speed, i.e., low parasitics, small
device geometry, also yield lowest ultimate production cost in silicon integrated circuits. Past circuit
design practice has equated high speed with high
.cost. The first step in the assessment of circuit constraints is a careful analysis of the technology used
to make circuits and the latent cost significance of
the variables.
The following example has been normalized to prevent easy identification of a given semiconductor
device. The analysis technique was developed by
Mr. W. D. Turner! of General Electric and will be
explored in more detail in a forthcoming paper.
Two characteristic fabrication processes were analyzed and they may be generally described as diode
isolation and oxide isolation. Mask technology has
a critical effect on cost as will be demonstrated.
Table 1. Circuit Economics.
Isolation
Tpd.
Circuit/ chip
Critical area ratio*
Relative yield
Normalized yield
Circuits per wafer
X normalized yield
Wafer cost
Oxide isolation
premium
Relative chip cost
X 10-3
A
Oxide
4ns
B
Diode
3 ns
1
1
0.296 0.460
3.38
2.17
0.87
0.56
160
218
139
122
1.00
1.00
C
Diode
2 ns
2
0.256
3.90
1.00
766
766
1.00
D
Diode
5 ns
2
0040
2.50
0.64
316
202
1.00
0.25
9
8.2
1.3
5.0
Assuming reasonable cost levels for the cost of a
wafer and also assuming a reasonable value for absolute yield, one may compute the cost of a chip:
Wafer cost
Yield
~
~
$50
0.5
Chip cost = Wafer cost X relative chip cost
*Critical area ratio is the result of obtaining the chip
area of a given circuit and dividing by the area which is
critical to yield. Areas which are critical are those where
an oxide fault or misregistration may result in a circuit
failure.
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507
HIGH-SPEED LOGIC CIRCUIT CONSIDERATIONS
A
$.90
B
$0.82
Yield
C
$0.13
D
$0.50
Assembly, test and package costs must be estimated
to complete the comparison, but for the purpose of
this paper, assume a constant $.30 for the sum total
of these factors.
A
$1.20
B
$1.12
C
$0.43
D
$0.80
Cost per circuit (C&D contain 2 circuits per chip)
$0.40
$0.22
$1.12
$1.20
These basic costs are marked up in accordance
with the profit motive to produce quoted selling
price. It is possible, of course, that a comparison of
selling price may result in an inversion or distortion
of the rank of the products. It is equally possible
that a distortion of the basic economics of the process as a result of the battle in the market place
may cause slipped schedules, price renegotiations
and poor quality parts. Selling price alone is not an
adequate parameter.
As a final comment, the smallest device, which
was also the fastest, had the least latent cost.
Now it must be recognized that a study of this nature has certain inaccuracies, but it is important
that these studies be made to ascertain the inherent
speed/cost relationship which may be entirely different from the quoted costs received from semiconductor marketing organizations.
LOGIC ARRAYS
One factor of growing significance, as circuit size
is reduced, is the increasing amount of surface area
consumed by areas devoted to interconnections and
pads for interconnections. There have been marginal improvements over the past few years, but no
startling improvements have been made in comparison to reductions in the basic device geometry. As
has been pointed out in many recent papers, the
consumption of real estate may be reduced by interconnecting the logic circuits with the narrow lines
allowed by the masking technology, thus reducing
to a minimum the area requirements for external
lead pads. At this point, the semiconductor manufacturer relaxes and says in effect to the computer
designer: Reduce your logic to a few standard con-
figurations, and I will reduce costs by a large factor. Hence, we have a search for magic standard
logic functions. Other approaches such as varying
the final step of the masking process to provide
special logic connections over a matrix of logic circuits has been proposed. This has resulted in difficult layout requirements and a challenging problem
of computing optimum ratios for connecting leads,
logic parting problems, and so forth. Other methods
are variations on providing a circuit/logic matrix
where bad elements are disrupted and the logic restructed through adjoining elements usually at the
expense of speed. All of these approaches seem to
neglect the basic overriding economic significance
of device geometry.
Figure 1 illustrates the normalized economy of
chip size vs array complexity. As can be seen, the
smaller the chip, the larger the array which may
economically be placed on the chip. With a given
mask technology, most economy is achieved by having a high number of chips per wafer which will set
definite limits on logic complexity per chip. Most
manufacturers are concerned with having a given
chip, good or bad, rather than going through complex "rescue" operations involving additional processing even though the metallic interconnection
step is relatively inexpensive. The point here is that
small size permits high speed with lower costs and
that logic arrays are apt to be most effective when
they are small, thus producing chip sizes amenable
to the economics of a given mask technology. The
largest stumbling block then is the logic configuration itself.
Unfortunately, we haven't achieved either a magic logic function or a magic insight into the solution of the problem of finding a relatively small set
of standard functions. However, we have carefully
analyzed a number of products and have classified
the logic groupings obtained in Table 2.
Table 2. Gate Efficiency.
EffiGates per
Group
package
ciency
1
2
3
4
(non-functional)
(functional)
(functional)
(functional)
1-3
4-8
46-71
106
100%
96
87
84
Loss
4%
13
16
Comparing these efficiency figures with cost
economy ratios exhibited in Fig. 1 reveals that array technology is economically attractive and war-
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rants extensive development effort. This is even
more significant for high-speed circuit applications,
since the array permits extremely short runs, unterminated, for a large portion of the logic. It is also
interesting to note that these efficiencies were
achieved with a relatively small number of different
logic configurations. The number of different arrays
were, in fact, less than the number of different circuits available in most microelectronic logic sets.
1
POWER CONSTRAINTS
The latent difficulty in power dissipation is the
prime importance junction temperature rise has on
reliability. The logic array is very likely to compound what is already a difficult situation in a normally isolated and mounted single or double circuit
chip. Array size is very influential in making a bad
situation worse. For example, in a four gate struc. .
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509
HIGH-SPEED LOGIC CIRCUIT CONSIDERATIONS
rore with no internal interconnections, the external
leads provide a reasonable path to whatever heat
sink is provided. However, many eight and more
gate structures contain buried elements which must
dissipate through the silicon chip body or through
the small area metallic surface connections. The situation is compounded if oxide isolation is used,
since the oxide is such an excellent thermal barrier.
Since the array is to be embedded in a transmission line environment, termination resistors must
be provided for inputs and literally line drivers provided for outputs. What is generally overlooked is
the absence of these requirements for circuits operating in the highly localized environment inside the
array. The loads and distances are well known, the
geometry is well controlled, crosstalk can be designed to a relatively low value and noise can be
locally reduced. In fact, the interior portions should
be quite different from the exterior portions from
the design standpoint. Power dissipation is directly
proportional to the transport energy required;
hence, internal voltage swings and noise immunity
should be reduced to the lowest possible level.
The lead technology will eventually prove to be
the most constraining factor for conventional
mounting techniques such as the flip chip or bonded wire methods. At present, we do not normally
consider making surface connections to reduce the
problems associated with power dissipation; but it
is apparent that this approach is not too far off.
Consequently, the circuit selected must be capable of operating as a driver of internal logic elements as well as being driven by a very small swing
on its inputs. There are a few circuits capable of
this type of operation; most level detector designs
will function in this fashion and, of course, the
popular current mode logic can be designed to produce these desirable characteristics. Since the circuit must operate from, and drive, transmission
lines, the swin/power relationships imposed by the
transmission line media are of more than a passing
interest during the circuit design.
MEDIA CONSTRAINTS
A common approach to the design problem is to
assume the highest possible transmission line impedance to minimize circuit power and reduce heat
dissipation. Of the general spectrum of transmission
line media available, the most frequently used is the
multilayer stripline and in view of its high popular-
ity, the discussion is confined to this type of interconnection scheme. The multilayer structure has a
very significant set of economics which must be
satisfied to produce acceptable manufacturing costs.
Table 3 represents the type of analysis which must
be performed to relate transmission line characteristics to the manufacturing capability and to the required run density. Obviously, the transmission
media must connect logic; therefore, the economic
achievement of density is a prime requisite. As may
be imagined, the density and number of layers required to achieve a given logic organization are key
factors for attaining reliability, low lamination
costs and high overall media yield.
Table 3. Transmission Line Characteristics.
Impedance
ohms
100 ±
100 ±
100 ±
50 ±
50 ±
50 ±
10%
5%
10%
10%
10%
10%
Mech.
Tolerance Mech. Dim. Cross- Line
~w
~t
wn
tn
talk Density
mils
mils
percent runs/in
±I
±I
±2
±1
±.5
±2
±I
±I
±2
:±:1
:±: .6
±2
6
12
22
II
14
24
16.6 9
9.3
5
30.5 16.5
10
10
10
7.5
9.2
13
40
20
20
30
60
20
The most important variable in the determination of cost is the mechanical tolerances which must
be held in the fabrication of both the signal carrying conductors and the insulating dielectric. With a
high quality, tight tolerance process, line density
may be significantly increased causing the number
of layers to drop rapidly for a given level of crosstalk. A low tolerance process may cause an increase in crosstalk and an increase in the number of
layers required to do a given job. In addition to the
importance of crosstalk, the absolute impedance
variation affects cost since the impedance mismatches in the system cause reflections, which in
turn may affect the required noise immunity of the
circuits.
Assuming that manufacturing cost is entered into
a similar table as a function of tolerance and process variables, a selection that is economic may be
made. The cost picture is not yet complete without
some provision for logic changes -even after the normal debug and prototype cycle. Variable logic must
be allowed and it may not be possible to have transmission line impedances which are identical to line
impedances used in the multilayer boards. Two pro-
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PROCEEDINGS -
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cesses are assumed: transmission lines and perhaps
terminated short-run open wires. The circuit selected must be capable then of operating with two different impedances. The overall cost balance
achieved is very much a function of the machine
size and organization, since maximum flexibility in
hardware will almost certainly result in higher
costs.
The packaging technique utilized is constrained
by the need for allowing full interconnection with
stripline, a small but finite number of variable connections, efficient low reflection connectors and
some timing problems which will be briefly mentioned. If the machine is a large one, the timing
problems are compounded by the fact that the interconnecting line lengths are not the same. In some
areas, this may be lumped as a clock skew problem
and be adequately solved by control of the clock
widths necessary to handle timing/length delays.
This is not always efficient and the clock system
itself may suffer from the same problem. The packaging system must therefore be designed to accommodate slack to control run length differences. At
present, the use of slack to provide a variable degree of delay appears quite feasible in the design
and control of some segments of the machine.
SUMMARY
The variables briefly discussed here are significant in the selection of a logic circuit to be used for
a high speed commercial/industrial application.
The underriding implication is clearly the achievement of high circuit volume, as is typical in most
computer applications, and low cost. The tradeoffs
in technology selection have frankly been preoccupied with silicon integrated circuits since in a high
volume environment this basic technology has demonstrated definite cost advantages. In an absolute
maximum speed environment, constrained by a desire to deliver at the earliest possible time, other
hybrid technologies have a slight performance edge.
This performance-time gap is rapidly closing, although it will not, in all likelihood, become zero. It
is of prime importance that a technology be selected
which has a maximum opportunity of achieving low
cost. This normally points to excellence in masking
tolerances, large production wafers and the absence
of process sequences which prohibit the subsequent
diffusion of logic arrays. In today's market place,
we must plan for a maximum possibility of cost reduction over the life of the product.
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Logic arrays are significant in making technological cost reductions possible. If an organization is
structured in array fashion, then arrays may be substituted in place as they become available from the
suppliers of the technology. This capability may not
be quite so effective in a high-speed machine since
the operating speed itself causes the arrays to become somewhat different to reduce the effects of
power dissipation. The circuit must be capable then
of operating over a wide range of drive conditions
with power dissipation considered a variable.
The connection media is a strong function of the
manufacturing capability to produce precision lines
at low cost with commensurate high skill in the art
of quality lamination techniques. These manufacturing cost and reliability variables will affect the
final nominal impedance choice drastically. To a
lesser extent, the variation of impedances will also
partially determine noise immunity requirements of
the circuits, which in turn affect power dissipation,
etc. Impedance reflections do cause a significant
noise problem.
While discussing circuit considerations, we have
yet to discuss circuit design; and I think it proper
to avoid this subject. Of all the factors influencing
the selection of a circuit, the design variable is for
all practical purposes one and the same with the
technology. After all, the design which has the least
number of components and the highest component
tolerance immunity, coupled with speeds high as
compared to basic device Ft, has always been a
good choice. The difference today is that the good
choice now has become the economic choice as a
result of the continuing advances of the semiconductor industry.
ACKNOWLEDGMENTS
The extensive studies and evaluation analysis,
which have caused these conclusions to be reached,
were performed by C. A. Combs, W. H. Herndon,
J. W. Tarzwell, and W. D. Turner, all of the General
Electric Computer Department, Phoenix, Arizona.
The author is grateful for their helpful comments
in the preparation of this paper.
REFERENCES
1. W. D. Turner, "An Analysis of the Effects of
Technology on Integrated Circuit Shop Costs," G.
E. Computer Department internal paper.
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