A New Topology for Parallel Resonant DC Link
with Reduced Peak Voltage
V.V.Deshpande and S.R.Doradla
Department of Electrical Engineering
Indian Institute of Technology
KANPUR 208 0 1 6 INDIA
possible to reduce device voltage stresses to 1.2 - 1.5Vdc
[6]. Fig. 1 shows an actively clamped PRDCL circuit.
The circuit is first started by turning on two devices
in the same leg of the inverter so that the current iL,
builds up in the inductor L,. When the current in the
inductor equals (Idamp I,), the devices are turned off.
The quantity Idamp is the current required to overcome
the losses in the resonant circuit. Lr and C, form the
resonant circuit with the input voltage Vdc. In the absence
of clamping circuit the peak voltage would have reached
twice Vdc. With the clamping circuit s,-D, in Fig. 1, the
link voltage is not allowed t o reach 2 v d c . When the link
voltage v, reaches V,, the diode D, gets forward biased,
and the voltage is clamped to V,. When the current i,,
begins to reverse through the clamping capacitor C,,the
device S, is turned on. At the instant when the net charge
transferred to C, becomes zero, S, is turned off. Fig. 2
shows the link voltage U, along with the clamping current
i,, through the clamping circuit. It is seen that there is a
current jump with high di/dt
which appears twice in
AbstractA n e w topology for parallel resonant
dc link is proposed. It offers r e d u c e d p e a k dc link
voltage w i t h o u t generating high di/dt. The effect
of various parameters on the link voltage waveform
is discussed. A design procedure is outlined to determine the component values for a n y desired resonant frequency. A comparison w i t h the actively
clamped circuit is given. There is an excellent correlation b e t w e e n the experiniental and simulation
+
results.
I. I N T R O D U C T I O N
In order to achieve zero voltage and/or zero current
switching in the dc to ac converters, a variety of resonant links have been proposed such as resonant ac link,
resonant dc link, quasi-resonant dc link, and dc side coinmutation [1]-[4]. The parallel resonant. dc link (PRDCL)
has attracted a lot of attention as evident from the literature [ti]-[9]. This is because the PRDCL offers a simplified
power circuit with minimum number of power devices. Besides, it is easy to implement and control. Regeneration
of power to the supply source is possible by using dual
converter scheme [7]. This scheme, however, sufkrs from
a few disadvantages such as zero crossing failure, voltage
overshoot during mode change to regeneration, and higher
device voltage stresses exceeding twice the input dc voltage. The problems of zero crossing failure and voltage
overshoot could be overcome by using current initialization scheme [5]. The peak dc link voltage can be limited
by using either active or passive clamping circuits.
Va
vb
vc
A . PRDCL with clamping circuit
The PRDCL can be designed using either passive or active clamping circuit. The passive clamping circuit. limits
the peak voltage to about 2.5VdC and hence it is not sstisfactory. With the use of the active clamping circuit it is
0-7803-1456-5194 $4.00 01994 IEEE
260
Fig. 1 Actively clamped resonant dc link circuit.
2 times the resonant frequency is injected using an additional parallel resonant circuit L h and c h connected in
series with the resonant capacitor C,..This topology has
been arrived at from the following considerations.
A parallel resonant circuit is chosen in order to inject
a voltage so as to reduce the peak link voltage.
icc
I
c
Dc conducts
K
>
t
Sc conducts
Fig. 2 Output voltage and clamping current of PRDCL.
every resonant cycle. The magnitude of the current jump
is a function of K, where I< is defined as Vc/Vdc. This is
shown in Fig. 3. The presence of high di/dt gives rise
to EM1 and radio frequency interference (RFI). The link
frequency fo is also a function of I< as is shown i n Fig.
3. The variation of the lid< frequency results in jitter at
the output of the inverter. Therefore, a resonant topology which avoids the clamping circuit and still reduces
the device voltage stresses is highly desirable [IO]. This
objective has been fulfilled by the new resomiit topology
proposed here.
c,
The resonant circuit is inserted in series with
in
order to add the generated voltage with the output
volt age.
For Ch/Cr ratio of 2.0 (discussed in Sec. III A), a 25%
reduction in the peak dc link voltage is possible. The
circuit has been simulated using electromagnetic transient
program for dc transmission (EMTDC). The simulation
waveforms of the proposed dc link are shown in Fig. 5.
The link voltage waveform shows two peaks each with a
magnitude of 1.5 times the input voltage. The reduction
in the peak volta.ge is obtained due to the presence of the
11. PROPOSED RESONANT LINK
I
In order to reduce the peak dc link voltage without generating high di/dt in the circuit, a new topology as shown
A voltage of frequency
in Fig. 4 has been proposed.
I
I
1
Fig. 4 Basic circuit of the proposed resonant link.
200
n
<
n
N
W
Iy 20
L
v
-I
100
*-
U
n
>
v
Q)
L
LL
L
n
< 10
y
9
W
+J
C
f!
L
o
3
0
0
1.’2
1..4
1:s
1:8
2.’0
K
Fig. 3 Variation of link frequency and current jump with IC.
-100
0
20
40
60
Time (microsec)
Fig. 5 Siniulatioii waveromis of the proposed resonant link.
voltage V C h as shown in the figure. Also, it is seen that all
the current and voltage waveforms are smooth. A phase
plane plot of the proposed and the normal dc link are
shown in Fig. 6. For the normal dc link VC, against i ~ ,
has been plotted where as for the proposed link two plots
namely VC, vs i~,. and V C h vs i L h are given. The comparison of phase plane plots clearly shows the reduction
in the peak link voltage for the proposed topology.
The basic circuit shown in Fig. 4 suffers from instability
and does not reach steady state. This is evident from
the EMTDC simulation waveforms shown in Fig. 7. The
instability results because of the build up of energy in
the elements L h and c h in every resonant cycle. Also, it
has been found that during certain transient conditions
the voltage across the capacitor C, goes negative. This
situation results in improper operation of the circuit.
A . Pm clical Top0 logy
0
To overcome these problems the basic circuit of Fig. 4 is
improved and the resulting circuit is shown in Fig. 8. The
diode D, connected across C,. prevents the voltage across
C, from going in the negative direclion. The switch St,
connected across c h helps in resetting the voltage across
the capacitor ch to zero a t the begining of every resonant
cycle. Therefore, the switch is turned on at the end of
every resonant cycle. Thus, the addition of D, and s h
helps in bringing the circuit to steady state. The diode
Dh is necessary to avoid positive voltages getting applied
across sh. The resulting waveforms are shown in Fig. 9.
The waveforms clearly show that the circuit remains in
steady state. The componcnts D, and C, are added to
the circuit to clamp the link voltage to V,. This clamping
circuit is necessary because a peak overshoot of voltage
occurs whenever the direction of I , reverses due to the
change in operating mode from motoring to regeneration.
40
4
vCh vsl iLh
I
1
100
200
300
Time (microsec)
400
Fig. 7 Wavefoils of the basic circuit showing instability.
vc Dc
cc l +
'-
I
+ I Vdc
1
Fig. 8 Practical circuit to get steady state opeartion.
0
111. EFFECT OF PARAMETERS
-100
0
100
200
300
V o l t a g e vo, vCh (V)
Tlie effect of various parameters on the behaviour of the
circuit was studied using EhiITDC simulation. The results
are useful in designing a reliable resonant dc link circuit.
Fig. 6 Phase plane plots for the proposccl arid nornial dc link.
262
1
200
.a
0
<
-O
W
L
-I
hl
100
*-
E
7
m
>
U
0.01
I
I
\I!
I
"
E
>
L
y
0.1
o
0.001
0
>
-100
0.0001
0
11
-
I I I I I
I l l l I I I I I
I I I I I I I I I
I I I I I 1 1 1 1
Time (microsec)
Fig. 9 Steady state waveforms of the circuit of Fig. 8.
Fig. 10 Graph of noimalised difference vs capacitance ratio.
A . Variation i n
C. Vaviation in
ch/c,
As mentioned earlier, a proper choice of values of c h
and Cr is very important for getting minimum peak link
voltage. The condition for minimum peak voltage is that
Vml should be equal to Vmz. A plot of magnitude of the
difference between Vml and Vm:! against c h / c , . ratio is
shown in Fig. 10. It is seen that both the peaks are equal
for the ratio c h / c r equal to 2.0. M'hile studying the effect
of variation in c h / c r the values of resonant frequencies
f r due to L r and crand f h due to Lh and c1, have been
maintained constant by appropriately modifying L , and
L h . The above result is valid for any resonant frequency.
B. Variation i n
Lh
It is necessary to study the variation of the LI, keeping
values of all other components constant. If the value of
L h is reduced Vml reduces and Vnlz increases. Simillarly,
if the value of L h is increased then the opposite effect
is observed. This result is valid for small variation in L , , .
Therefore by making the inductor Lh variable over a small
range, it is possible to finely tune the circuit to oblaiii
Vml
= Vm2.
263
Idamp
The quantity Idamp is the initial current required in the
inductor L, at the begining of a resonant cycle to overcome the losses in the resonant circuit. It mainly depends
upon the Q factors of the inductors and the supply volta.ge Vde. It is possible to maintain the required value of
Idamp in the steady state. However, during transient state
it inay vary widely. Idamp in excess of the required value
tends to increase the magnitude of Vml. An insufficient
value of Idamp may result in zero crossing failure.
D. Variation in V,
As discussed earlier, the components D, and C, are
needed to prevent the overshoot of voltage whenever the
mode changes from motoring to regeneration. This mode
change results in a large pulse of voltage. By selecting
an appropriate clamping voltage, the peak voltage can
be limited to a safe value, and the circuit reaches steady
state within next few resonant cycles. Fig. 11 shows the
operation of the clamping circuit after the value of I, has
changed from +20 A to -20 A, for a clamping voltage
of 250 V. The clamping circuit can be replaced with a
transient absorber or a metal oxide varistor (MOV)of appropriate energy rating. This is feasible in circuits where
frequent mode change does not take place as in power
supplies and low power drives with less frequent reversals.
Fig. 12 Circuit used for state space analysis.
Equations (1) - (5) have been used for the simulation
of the circuit of Fig. 12 using SIMNON. The results of
siiiiulation agree completely with those of EMTDC.
B. Transfer Function
Time (microsec)
To simplify the analysis, the transfer function has been
derived assuming R h , R,., and I , to be zero. The transfer
function is
Fig. 11 Effect of clamping on the link voltage wav&onl~s.
IV. ANALYSIS AND DESIGN
A . S t a t e Space Representation
Where Vo(s)is the Laplace transform of v o ( t ) .From ( 6 )
the expression for U, to a step input is obtained by finding
the partial fractions and then taking the inverse Laplace
transforin. The final expression for v,(t) is given by
The circuit used for the state space analysis is shown i n
Fig. 12. The value of the current 1, is assumed constcant
for one resonant cycle. The state variables chosen are
i L r , i L h , V C r , and vch. The state equal,ions are
The radian €requencies w: and w; are
\\'here
The equation for the output voltage is
vo
= VCr
+
b =
VCh
c
The initial conditions are
=
d =
For a well designed circuit the locations of finite poles and
zeros are shown in Fig. 13.
264
J"I
Lh = 12.2pf1, and c h = 2.OpF. Fig. 14 shows the results
of the experiment. A comparison of these results with the
waveforms of Fig. 5 reveals complete agreement with the
siniulation results. For getting reliable operation of the
circuit, the capacitors used are of polypropelene type and
the inductors are made up of air core using litz wire. The
rating of sh is small compared to the output power rating. A careful physical layout of resonant components has
been made to avoid interactions of the two inductor magnetic fields. Alternatively, winding of inductors on low
permeability cores will help in reducing this interaction.
The dissipation in the device Sh due to discharge of capacitor c h is found to be negligibly small (less than one
watt). Therefore, the current rating of the device s h is
very small.
I
0-
Fig. 13 Locations of poles and zeros.
C.Design
The conditions for getting minimum link voltage are
obtained by differentiating (7) and equat<itigit to zero.
The equation thus obtained is
Equation (12) is satisfied for values of t = 0, T/2, T,
t l , and tg (Fig. 5 ) . Substituting these values o f t in (12),
the relations obtained are
2x
T = W1
wg
12
= 2Wl
= T-ti
(14)
(15)
Substituting (13)-(15) in (7), tlie required expressions
which facilitate the design of the resonant components are
For a desired resonant link frequency w1 and after selecting the value of any one componeut amongst L,., Lh,
Cr,c h , the remaining component values could be obtained
from (16)-( 18).
V. EXPERIMENTAL SETUP
A . Results
To confirm the operation of the new topology, tlie circuit has been fabricated and tested in the laboratory. The
resonant frequency fo is chosen to be 19 1tIIz for which the
various component values are Lr = 55p1-1, C,. = l . O p F ,
Fig. 14 Experimental results showing v o r w h and i L h .
(a)wo, u C h , i L h , X-axis 2OpSldiu; Y-axis 20 V/div and 10 Aldiv.
(b)vo, u c h , i L h , X-axis SpSldiu; Y-axis 20 V/div and 10 Aldiv.
265
VII. C O N C L U S I O N
B. Control
A block schematic of the control circuit is shown in Fig.
15. The circuit senses v, and V C h and generates two driving signals s(,?)and S h ( o n ) . The signal s(on)
is used to
trigger two devices in the same leg of the inverter so as to
build the required inductor current at the begining of the
resonant cycle. The control circuit can be simplified by
using S(,,) signal to turn on s h also. This will eliminate
the necessicity of sensing V C h and the associated circuit.
A new topology for resonant dc link has been proposed.
It uses four resonating elements. The peak link voltage
has been reduced by 25% with the current jumps completely eliminated. The currents have become smooth as
expected in resonant type inverters.. The circuit has been
simulated and the results have been experimentally confirmed on a hardware setup. The state space and transfer function analysis has provided a basis for the design
of the resonant inductors and capacitors of the proposed
new topology. A comparison with actively clamped circuit
reveals that the proposed topology reduces the losses in
the link by about 25 %. The reduced peak dc link voltage will result in economy from the standpoint of overall
cost of the inverter. It reduces EM1 due to smooth waveforms. This topology is potentially suited for many other
applications as well.
ACKNOWLEDGMENTS
The author V V Deslipande would like to thank Council
of Scieut,ific and Industrial Research (CSIR) for granting
research associateship to carry out the research work.
Fig. 15 Block schematic of the control circuit.
REFERENCES
VI. C O M P A R I S O N
As compared to the actively clamped circuit the proposed topology does not need the additional switching
device (SA is not considered because it is of very small current rating). This is possible at the cost of a n additional
resonant inductor and a capacitor. In tlie proposed topology the current jumps are completely eliminated. Table
I shows a comparison of losses [9]. The comparison has
been made assuming Io to be zero, v d c of 150 V and fo of
19 kHz. The comparison shows that tlie proposed topology reduces the power loss by about 25 %. Tlic proposed
topology could be further simplified by using transient absorbers where ever possible, as nientioned in Sec. I11 D.
TABLE I
COMPARISON O F LOSSES
Parameters
Losses in L,
Losses in S,
Losses in L h
Total losses
Active clamping
10.0 \v
9.0 \1‘
19.0I\\
I
I
Proposcd topology
9.0 I\
1.0 \V I i i i S,,)
4.0 I\\
\
1.1.0 \\.
..I
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266