R13
Code: 13A04501
B.Tech III Year I Semester (R13) Regular Examinations December 2015
ANTENNAS & WAVE PROPAGATION
(Electronics and Communication and Engineering)
Max. Marks: 70
Time: 3 hours
1
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
(i)
(j)
PART – A
(Compulsory Question)
*****
Answer the following: (10 X 02 = 20 Marks)
Radiated power density of an antenna is given by
W/m2. Find the maximum
directivity of the antenna.
Explain the terms “Radian” and “Steradian” with reference to the radiation pattern of antennas.
A magnetic field strength of 5 µA/m is required at a point on
which is 2 km from an
antenna in air. Neglecting ohmic losses, how much power must the antenna transmit if it is a
half-wave dipole?
Draw the E – plane view and H – plane view of a pyramidal horn antenna specifying important
parameters required for the design of the antenna.
List out advantages and limitations of Microstrip antennas.
Assuming perpendicularly polarized feeds, draw the corner reflectors and their images for angles
of 900 & 450.
Distinguish the differences between broadside array and end-fire array.
Give the different field regions of an antenna & specify them graphically with respect to antenna’s
position.
Calculate the distance beyond which the earth’s curvature is to be accounted at a signal frequency
of 10 MHz.
Calculate the maximum single hop distance for ‘D’ and ‘E’ layers if their heights are assumed to be
70 and 130 km respectively above the earth & the angle of incidence is 100 for both cases.
PART – B
(Answer all five units, 5 X 10 = 50 Marks)
UNIT – I
2
(a)
(b)
3
(a)
(b)
Derive the expression for radiation resistance of a short (Hertzian) electric dipole starting from far
field expressions.
Explain about different polarizations with suitable expressions and sketches.
OR
State and explain the following antenna parameters: (i) Directivity. (ii) Half Power Beam Width
(HPBW) with suitable examples.
A half-wave dipole is located on a perfectly conducting ground with sinusoidal current distribution.
Deduce the expression for average power radiated by the dipole.
UNIT – II
4
(a)
(b)
5
(a)
(b)
Derive far field expressions due to a small filamentary circular loop of radius ‘a’ carrying uniform
current of
.
With neat sketches, discuss about the folded dipole and its input impendence.
OR
Explain the working principle of Yagi – Uda antenna with suitable sketches.
Discuss about design considerations of pyramidal horn antenna.
Contd. in page 2
Page 1 of 2
R13
Code: 13A04501
UNIT – III
6
(a)
(b)
7
(a)
(b)
What are the characteristics of Microstrip antennas? Explain in detail.
State first null beam width, and find out its value and power gain(in dBs) of 2 m paraboloid
reflector operating at 6 GHz.
OR
Discuss about different structures of dielectric lenses, & their principle of operation with neat
sketches.
A parabolic dish provides a gain of 75 dB at a frequency of 15 GHz. Calculate capture area of the
antenna and half power and first null beam widths.
UNIT – IV
8
(a)
(b)
9
(a)
(b)
Deduce the expression for the Array Factor due to an N-element uniform linear antenna array and
draw its plot for N = 4.
With suitable block diagram, give the steps to measure radiation pattern of an antenna considering
E-plane & H – plane.
OR
With the suitable setup, explain the measurement of Gain of an antenna by absolute and by
comparison methods.
Consider two Hertzian dipoles are placed in free space along the z-axis but oriented parallel to the
x-axis. For the two element antenna specified above, sketch the normalized field pattern when
.
currents are fed in phase and the distance between them
UNIT – V
10
11
(a) Derive the expression for maximum usable frequency (MUF) pertaining to sky wave propagation.
(b) A transmitting antenna of 100 m height radiates 40 kW at 100 MHz uniformly in azimuth plane.
Calculate the maximum line of sight (LOS) range and strength of the received signal at 16 m high
receiving antenna at a distance of 10 km. At what distance would be signal strength reduce to
1 mV/m.
OR
(a) Discuss about the structural details of the region above the earth surface up to ionosphere.
(b) The maximum distance between the transmitting and receiving antenna of TV towers is 72 km. If
the ratio of height of transmitting and receiving antennae is 16:25, what are the heights of towers?
Assume that the radius of the earth is about 6.371 × 106 km.
*****
Page 2 of 2
R13
Code: 13A04502
B.Tech III Year I Semester (R13) Regular Examinations December 2015
DIGITAL COMMUNICATION SYSTEMS
(Electronics and Communication Engineering)
Time: 3 hours
1
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
(i)
(j)
Max. Marks: 70
PART – A
(Compulsory Question)
*****
Answer the following: (10 X 02 = 20 Marks)
Define quantization.
What are the differences between ideal sampling and practical sampling?
List the properties of matched filter.
What is meant by Inter-symbol interference?
What are the assumptions to be made in deriving the expressions for the probability of an error?
Define Matched filter.
What is meant by differential phase shift keying?
What are the two forms of synchronization required for the operation of coherent detector?
List the advantages of convolutional codes over block codes.
Draw the block diagram of Forward Error Correction System.
PART – B
(Answer all five units, 5 X 10 = 50 Marks)
UNIT – I
2
(a)
(b)
3
(a)
(b)
Draw and explain the block diagram of TDM system.
Give the comparison of DPCM and DM with standard PCM.
OR
Discuss the two major sources of quantizing error in DM systems.
Draw and explain the block diagram of a regenerative repeater.
UNIT – II
4
(a)
(b)
5
(a)
(b)
Explain in brief about Duobinary signaling scheme.
Write a brief note on Eye pattern.
OR
Explain in brief about Modified Duobinary signaling scheme.
Describe the baseband transmission of M-ary data.
UNIT – III
6
(a)
(b)
7
(a)
(b)
Explain the Gram-Schmidt orthogonalization procedure.
Write a brief note on signal constellation diagram.
OR
Explain the coherent detection of signals in noise.
With a neat sketch explain the working of correlation receiver.
UNIT – IV
8
(a)
(b)
9
(a)
(b)
Give the comparison of power and bandwidth requirements for various digital modulation schemes.
Derive the error probability for QPSK.
OR
Explain the generation and detection of BPSK.
Discuss in brief about Non-coherent detection of binary FSK.
UNIT – V
10
(a)
(b)
11
(a)
(b)
Explain the concept of Interleaving.
Discuss in brief about sequential decoding of convolutional codes.
OR
Describe the matrix representation of block codes.
With a neat sketch describe the operation of the ARQ system.
*****
R13
Code: 13A04503
B.Tech III Year I Semester (R13) Regular Examinations December 2015
LINEAR IC APPLICATIONS
(Electronics and Communication Engineering)
Time: 3 hours
Max. Marks: 70
PART – A
(Compulsory Question)
*****
1
Answer the following: (10 X 02 = 20 Marks)
Draw the ideal voltage transfer curve of Op amp.
Determine the output voltage for the inverting amplifier if the gain and the input voltage of the Op amp is
1000 and 20 mV dc respectively.
List out the properties of practical Op amp.
Draw the frequency responses (Gain Vs frequency) of open loop and closed loop operational amplifier.
Design a first order low pass filter at a higher cut off frequency of 1 kHz with a pass band gain of 2?
Draw the circuit diagram of non-inverting Summing amplifier.
Draw the circuit diagram and waveforms of zero crossing detector.
List out the applications of MPY634.
Define resolution and settling time.
What are the main advantages of integrated type ADC?
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
(i)
(j)
PART – B
(Answer all five units, 5 X 10 = 50 Marks)
UNIT – I
2
(a)
(b)
3
(a)
(b)
Compare different configurations of differential amplifier.
Draw the circuit of basic current mirror and explain its operation.
OR
Draw the various functional blocks of an operational amplifier IC. Explain each block.
Draw the equivalent circuit diagram of Op amp and derive the expression for gain of non-inverting
amplifier.
UNIT – II
4
5
(a)
(b)
Explain in detail about external frequency compensation techniques with neat sketches.
OR
Define slew rate and derive the expression for it.
Derive the input resistance and output resistance for a voltage shunt feedback amplifier.
UNIT – III
6
(a)
(b)
7
Design a differentiator to differentiate an input signal that varies in frequency from 10 Hz to about 1 kHz.
Write short notes on V-I and I-V converters using op-amps.
OR
Draw the circuit diagram of Instrumentation Amplifier and derive the expression for gain.
UNIT – IV
8
(a)
(b)
9
Design a 555 Astable Multivibrator to operate at 10 kHz with 40% duty cycle.
Draw the block diagram of PLL and explain its operation.
OR
Draw the circuit diagram of RC phase shift oscillator and derive the expression for its frequency of
oscillations.
UNIT – V
10
11
(a)
(b)
Draw the circuit diagram of Dual Slope ADC and explain its working with neat sketches.
OR
Explain the operation of Weighted Resistor DAC with the help of circuit diagram.
The basic step of a 9 bit DAC is 10.3 mV. If “000000000” represents 0 V. What output is produced if
the input is “101101111”?
*****
R13
Code: 13A04504
B.Tech III Year I Semester (R13) Regular Examinations December 2015
DIGITAL IC APPLICATIONS
(Electronics and Communication Engineering)
Time: 3 hours
Max. Marks: 70
PART – A
(Compulsory Question)
1
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
(i)
(j)
*****
Answer the following: (10 X 02 = 20 Marks)
Draw the ideal characteristics of a CMOS inverter and compare it with the actual characteristics
What is noise margin? Find out the noise margin from the actual characteristics of the inverter
Draw the transition times for CMOS circuits with: (i) ideal case of zero-time switching. (ii) a more
realistic approximation. (iii) Actual timing, showing rise and fall times.
What are the various steps in an HDL-based design flow?
What is a register? How many different types data can be entered and retrieved?
What is mean by Universal Register? Name any one commercial universal register.
Distinguish between Mealy and Moore machines with suitable diagrams.
A sequence detector produces a ’1’ for each occurrence of the input sequence ‘1001’ at its input.
Draw the state-transition diagram of the FSM realizing the sequence detector.
What is meant by PLD? What are the advantages of PLDs?
Explain positive and negative edge triggered Flip-Flops.
PART – B
(Answer all five units, 5 X 10 = 50 Marks)
UNIT – I
2
(a)
(b)
3
(a)
(b)
Compare the characteristics of the different types of MOS inverters in terms of noise margin and
power dissipation.
Draw neat circuit diagram, function table and logic symbol of a 2- input CMOS NAND gate.
OR
Explain the principle of a Emitter-Coupled Logic (ECL/CML) through Basic ECL inverter/buffer
circuit with input HIGH and LOW.
What are the advantages and disadvantages of ECL?
UNIT – II
4
(a)
(b)
5
(a)
(b)
Draw the VHDL program file structure and explain the same with the syntax of a VHDL entity
declaration and architecture definition.
Write the syntax of a VHDL function definition and write a VHDL function for converting
STD_LOGIC_VECTOR to INTEGER.
OR
Write the syntax of a VHDL component declaration and by making use of component declaration
write a VHDL program for a prime-number detector.
Write the syntax of a VHDL process statement and by making use of process statements write a
process-based dataflow VHDL architecture for the prime-number detector.
Contd. in page 2
Page 1 of 2
R13
Code: 13A04504
UNIT – III
6
Draw the logic symbol, truth table, logic diagram of a commercially available MSI 74x138 3-to-8
binary decoder and model the same using data flow-style VHDL program.
OR
Draw the logic symbol, truth table, logic diagram of a commercially available MSI 74x157 2-input,
4-bit multiplexer and model the same using behavioral-style VHDL program.
7
UNIT – IV
8
Draw the logic symbol, arithmetic conditions, logic diagram of a commercially available MSI
74x682 8-bit comparator and model the same using VHDL program.
OR
Describe the internal structure, functional operation and timing of edge-triggered commercially
available SSI 74x74 D flip-flop and model the same using behavioral-style VHDL program with
preset and clear.
9
UNIT – V
10
11
(a)
(b)
Draw the logic diagram of a simple 8x4 diode ROM and explain its operation.
List out commercial ROM types and compare them with respect to technology, read cycle, write
cycle and comment on each one.
(c) How the limitations of a ROM-based realization are overcome in a PLA based realization?
OR
n
(a) Sketch the basic structure of a 2 x b RAM and functional behavior of a SRAM cell.
(b) Explain how read and write operations are performed in a SRAM with the help of timing diagrams.
(c) In what way the DRAMs differ from SRAMs? Explain the read and write operations for one
transistor DRAM cell.
*****
Page 2 of 2
R13
Code: 13A04507
B.Tech III Year I Semester (R13) Regular Examinations December 2015
MICROPROCESSORS & INTERFACING
(Common to CSE and IT)
Time: 3 hours
Max. Marks: 70
PART – A
(Compulsory Question)
1
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
(i)
(j)
*****
Answer the following: (10 X 02 = 20 Marks)
Explain DAA and XCHG instruction of 8085.
Describe function of AEN and DT/ signal of 8086.
What is effective address? How it can be specified in instruction?
What is the difference between arithmetic and logical shift?
How to enable and disable interrupts in 8086?
Compare memory mapped I/O with I/O mapped I/O.
What is the function of In Service Register of 8086?
Write control word to set bit 4 of port C of 8255.
State extra hardware features of 8051 as compared to microprocessor.
Explain TCON and TMOD function registers of 8051.
PART – B
(Answer all five units, 5 X 10 = 50 Marks)
UNIT – I
2
Draw and explain architecture of 8085.
3
OR
Explain with neat diagram how 8086 access a byte or word from even & odd memory banks.
UNIT – II
4
5
Describe addressing modes of 8086 with suitable examples.
OR
Describe following instructions of 8086 with example:
(i) STOS. (ii) TEST. (iii) ROL. (iv) CMC.
UNIT – III
6
7
Draw and explain interrupt vector table of 8086.
OR
Interface 16-bit output port to 8086. The output port should be mapped in memory with address
40000H.
UNIT – IV
8
9
Explain mode 0. Mode 1 and mode 2 of 8253 timer with neat timing diagrams.
OR
Describe sequence of operations during data transfer between CPU and memory using 8237 DMA
controller.
UNIT – V
10
11
Draw and explain internal structure of port 1 of 8051.
OR
Explain bit level instructions of 8051 microcontroller with appropriate examples.
*****
R13
Code: 13A04508
B.Tech III Year I Semester (R13) Regular Examinations December 2015
LINEAR & DIGITAL IC APPLICATIONS
(Electrical and Electronics Engineering)
Time: 3 hours
Max. Marks: 70
PART – A
(Compulsory Question)
*****
1
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
(i)
(j)
Answer the following: (10 X 02 = 20 Marks)
List the characteristics of an ideal op-amp.
Enlist the features of an instrumentation amplifier.
Draw the block diagram of PLL.
What is meant by Regenerative comparator?
What are the advantages of active filters over passive filters?
What are the different types of oscillators?
Give the classification of Integrated circuits.
Sketch the logic levels for typical CMOS logic circuits.
List the applications of multiplexers.
What is meant by Decade counter?
PART – B
(Answer all five units, 5 X 10 = 50 Marks)
UNIT – I
2
(a)
(b)
3
(a)
(b)
Draw and explain the operation of op-amp based sample and hold circuit. And also draw the input and output
waveforms.
Define the following terms: (i) Slew Rate. (ii) Thermal drift.
OR
Draw and explain the operation of instrumentation amplifier using transducer bridge.
Design a differentiator to differentiate an input signal that varies in frequency from 10 Hz to about 1 KHz.
UNIT – II
4
(a)
(b)
5
(a)
(b)
Sketch the functional schematic of 555 timer and explain how it can be used as a monostable multivibrator.
And also draw the waveforms.
Calculate the values of the LSB and full scale output for an 8-bit DAC for the 0 to 10 V range.
OR
Draw and explain the operation of counter type ADC.
Define the following terms: (i) Resolution. (ii) Capture range.
UNIT – III
6
(a)
(b)
7
(a)
(b)
Draw and explain the operation of op-amp based triangular waveform generator and also determine the
frequency of triangular waveform.
A first order low-pass Butterworth active filter has a cut-off frequency of 10 KHz and unity gain at low
frequency. Find the voltage transfer function magnitude in dB, at 12 KHz for the filter.
OR
With a neat sketch, explain the operation of Quadrature oscillator.
If a band-pass filter has a lower cut-off frequency fL = 250 Hz and a higher cut-off frequency fH = 2500 Hz, then
find its bandwidth and the resonant frequency.
UNIT – IV
8
(a)
(b)
9
(a)
(b)
10
(a)
(b)
11
(a)
(b)
Give the comparison of various logic families.
Draw and explain the operation of CMOS three-state buffer. And also draw its functional table.
OR
Draw the circuit diagram of two-input LS-TTL NAND gate and explain its operation.
Write a brief note on CMOS transmission gate.
UNIT – V
Draw and explain the operation of 4-bit parallel binary adder/subtractor circuit.
Convert a T flip-flop to D type flip-flop.
OR
Design a code converter that converts BCD to excess-3 code.
List the applications of shift registers.
*****
R13
Code: 13A04509
B.Tech III Year I Semester (R13) Regular Examinations December 2015
LINEAR & DIGITAL IC APPLICATIONS
(Electronics and Instrumentation Engineering)
Time: 3 hours
Max. Marks: 70
PART – A
(Compulsory Question)
*****
1
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
(i)
(j)
Answer the following: (10 X 02 = 20 Marks)
Give the classification of ICs.
What is the significance of an AC amplifier?
Define comparator.
Draw the block schematic of the PLL.
Draw the basic CMOS inverter circuit.
List the characteristics of Emitter Coupled Logic (ECL).
List the features of VHDL.
What are the different ways to specify a time delay in a VHDL code?
Give the importance of three state devices.
Define clock skew.
PART – B
(Answer all five units, 5 X 10 = 50 Marks)
UNIT – I
2
(a)
(b)
3
(a)
(b)
Define the following:
(i) CMRR. (ii) PSRR. (iii) Slew rate.
Draw and explain the operation of current to voltage converter
OR
Design a differentiator to differentiate an input signal that varies in frequency from 10 Hz to about 1 kHz.
Discuss the different types of linear IC packages.
UNIT – II
4
(a)
(b)
5
(a)
(b)
Explain any two applications of PLL.
Draw and explain the operation of Antilog amplifier.
OR
A Schmitt trigger with the upper threshold level VUT = 0 V and hysteresis width VH = 0.2 V converts a 1 kHz
sine wave of amplitude 4VPP into a square wave. Calculate the time duration of the negative and positive
portion of the output waveform.
With a neat sketch explain the operation of triangular waveform generator.
UNIT – III
6
(a)
(b)
7
(a)
(b)
Give the comparison of logic families.
Explain how to estimate sinking current for low output and sourcing current for high output of CMOS gate.
OR
Discuss in brief about CMOS/TTL interfacing.
Explain the following terms with reference to CMOS logic:
(i) Logic levels. (ii) Power supply rails
UNIT – IV
8
9
(a)
(b)
Explain in detail about the steps involved in HDL-based design flow.
OR
Explain with an example, the syntax and the function of the following VHDL statements:
(i) Case statement. (ii) Loop statement.
Write a brief note on simulation.
UNIT – V
10
11
(a)
(b)
Design a logic circuit of Binary to Gray code converter and write a data flow VHDL program.
OR
Design a conversion circuit to convert a T flip-flop from D flip-flop.
Give the comparison between Moore and Mealy circuits.
*****