ISSN(Online)
ISSN (Print)
: 2320-9801
: 2320-9798
International Journal of Innovative Research in Computer and Communication Engineering
An ISO 3297: 2007 Certified Organization
Vol.3, Special Issue 8, October 2015
Second National Conference on Emerging Trends and Intelligence Technologies [ETIT 2015]
On 3rd October 2015, Organized by
Dept. of CSE, Anand Institute Of Higher Technology, Kazhipathur, Chennai-603103, India
Designing an Wideband Low Noise Amplifier
Using Different Low Power Techniques
K.E.Purushothaman
PG Scholar, Adhiparasakthi Engineering College, Melmaruvatthur, Tamil Nadu, India
ABSTRACT: In this paper resistive shunt feedback LNA amplifier has been designed. Resistive shunt feedback is a
feasible solution for wideband low noise amplifier design. Low noise amplifier is used in the front end of receiver.
Various low power techniques such as Domino logic, Dual rail logic are used to achieving low power, high noise-factor
and high bandwidth. Current reuse technique is implemented. Simulation results shows power, noise factor and so on.
KEYWORDS: Resistive shunt amplifier, low noise amplifier, current reuse, common gate amplifier.
1.
INTRODUCTION
Resistive shunt-feedback is a feasible option for LNA design. It provides wideband input matching with the aid of a
feedback network. Although low voltage & power design impose severe limitations in the design options. Table I
summarizes the design equations for input matching, gain and noise factor at low frequencies for a resistive shunt
feedback LNA with passive load.
As can be seen in the equations, the input impedance voltage gain, and noise factor of a shunt feedback LNA are
functions of output resistance (𝑅𝑜 ) & the feedback resistor(𝑅𝑓 ).Low supply voltage in nanometre CMOS technologies
limits the achievable 𝑔𝑚 and 𝑟𝑜 .In these equations,
TABLE 1
Equations for a Resistive Shunt Feedback LNA
s.no
Input Impedance
Voltage Gain
Resistive Shunt Feedback Amplifier
𝑅𝑜 + 𝑅𝑓
1 + 𝑔𝑚 𝑅𝑜
𝑅𝑜 (1 − 𝑔𝑚 𝑅𝑓 )
(𝑅𝑜 + 𝑅𝑓 )
Therefore, it is necessary to observe the effects of both 𝑅𝑓 &𝑅𝑜 are essential to 𝑔𝑚 for input matching, gain and NF.
Resistive shunt feedback amplifier is designed with passive load, active load and current reuse. Although an active load
entails a constant voltage drop, the achieved output conductance is a function of the drain current. When the drain
current is increased to improve gm, it leads to lower output resistance. The achievable gm versus RO (RO = ro1||ro2)
for an n-MOS with an active load biased at the new optional inversion coefficient for two different supply voltages.
When operating at a supply voltage of 1.2 V, the two curves meet each other at RO of 100 with gm of 60mS.
Accordingly, the solution at VDD of 1.2 V exists, though at the cost of high power consumption. Third section is
current reuse scheme facilitates doubling the effective gm without any extra power consumption or weakening of
output conductance compared with active load structure. Inverter-type input with current reuse is the most excellent
solution for low voltage and low-power applications.
Copyright @ IJIRCCE
www.ijircce.com
69
ISSN(Online)
ISSN (Print)
: 2320-9801
: 2320-9798
International Journal of Innovative Research in Computer and Communication Engineering
An ISO 3297: 2007 Certified Organization
Vol.3, Special Issue 8, October 2015
Second National Conference on Emerging Trends and Intelligence Technologies [ETIT 2015]
On 3rd October 2015, Organized by
Dept. of CSE, Anand Institute Of Higher Technology, Kazhipathur, Chennai-603103, India
II.
DESIGN CHALLENGES
Feedback Resistor is a determining factor in finding the finest design parameters in the design specifications. Voltage
gain or input matching criteria is dominant in choosing 𝒈𝒎 of the transistor. Also, this plot clearly shows the
transaction between voltage gain / noise factor and input matching in the resistive shunt-feedback LNAs. Resistive load
has been widely used in resistive shunt feedback topologies. While the resistive loads do provide advantages in terms
of bandwidth and NF over active loads, they are not optimal for low voltage designs because of the low voltage
headroom available
Power can further reduced by comparing different low power techniques like pass transistor logic, domino logic in the
low noise amplifier modified. A resistive load has been widely used in resistive shunt feedback topologies. While the
resistive loads do provide advantages in terms of bandwidth and NF over active loads, they are not optimal for ULV
designs because of the low voltage headroom available.Resistive shunt feedback with active load is another option.
Although an active load entails a constant voltage drop, the achieved output conductance is a function of the drain
current. When the drain current is increased to enhance gm, it leads to lower output resistance. Achievable gm versus
RO (RO = ro1||ro2) for an n-MOS with an active load biased at the new recommended inversion coefficient for two
different supply voltages. These curves are plotted together with the gm required for input matching, and the
intersection point of the gm versus RO curves and the input matching curve corresponds to a solution with an S11 of
18dB. When operating at a supply voltage of 1.2 V, the two curves meet each other at RO of 100 with gm of 60mS.
Consequently, the solution at VDD of 1.2 V exists, though at the cost of high power consumption. As can be seen from
the plot, this topology has no solution for a supply voltage of 0.5 V. The third option is the current reuse inverter-type
input. In this architecture, the current Reuse scheme facilitates doubling the effective gm without any extra power
consumption or deterioration of output conductance compared with active load structure. As illustrated in the figure,
the current reuse structure provides a solution even at low supply voltage (0.5 V). The intersection happens at RO of
210 and gm of 37mS. As a result, the inverter-type input with current reuse is the best solution for low voltage and lowpower applications.
The current reuse architecture shows the best performance for Low-power and low voltage applications. As a result,
this technique is employed to reduce power consumption and at the same time to improve the gain and noise
performance. Input matching is achieved using the standard resistive shunt-feedback technique.Furthermore, inductive
series peaking in the feedback loop is exploited to cancel the parasitic gate–source capacitance(Cgs)and the Miller
effect of the parasitic gate–drain capacitance, Cgd to extend the input matching and bandwidth.
In this section, the proposed resistive feedback LNA will be discussed in detail with a focus on the inductive series
peaking to enhance the gain, input matching, and noise performance.Inductive series peaking in the feedback path is
used in existing system. Low supply voltages impose several restrictions on the circuit topologies that can be used. One
common technique in LNA design is to use a cascade transistor for bandwidth and output resistance enhancement.
However, the voltage drop needed by this transistor makes it impractical at low supply voltages.
Consequently, other approaches must be used to extend the bandwidth of the amplifier, preferably without increasing
the power consumption. A conventional technique to extend the bandwidth without additional power consumption is to
use inductors to resonate with the parasitic capacitances of the transistors and (c) shows circuits with the inductor
placed at the input of the LNA and inside the feedback loop respectively.
To compare all three topologies in Fig.3, the effective gm is calculated for each. However, for the case where the
inductor is placed at the input, the last term in the denominator exists at the resonant frequency and dampens the
response so no gm boosting occurs. Fig.5 shows results for the effective gm for the three circuits. The bandwidth
enhancement for series peaking in the feedback loop is obviously higher than the inductive peaking at the input, and is
the approach adopted in the design presented here.
Copyright @ IJIRCCE
www.ijircce.com
70
ISSN(Online)
ISSN (Print)
: 2320-9801
: 2320-9798
International Journal of Innovative Research in Computer and Communication Engineering
An ISO 3297: 2007 Certified Organization
Vol.3, Special Issue 8, October 2015
Second National Conference on Emerging Trends and Intelligence Technologies [ETIT 2015]
On 3rd October 2015, Organized by
Dept. of CSE, Anand Institute Of Higher Technology, Kazhipathur, Chennai-603103, India
Another positive effect of adding the inductors inside the feedback loop is that R f and Cgd are not in parallel any more,
therefore, the bandwidth of the feedback loop is also broadened. From pole-zero perspective, this technique pushes the
dominant poles of the circuit to higher frequencies. The effect of inductor values on the position of dominant poles of
the circuit. Conjugate poles are pushed into the left side by increasing the value of inductors. However, after a certain
limit, the magnitude of the dominant poles from the origin gets reduced, leading to lower bandwidth. The exact
equations of the pole-zero locations are very complex to solve. Simulations are employed to find the optimum values of
the inductors.
Fig .1.Resistive shunt feedback amplifier wave generation
Fig .2. Existing system schematic diagram
Fig.3.proposed system of wideband LNA
Copyright @ IJIRCCE
www.ijircce.com
71
ISSN(Online)
ISSN (Print)
: 2320-9801
: 2320-9798
International Journal of Innovative Research in Computer and Communication Engineering
An ISO 3297: 2007 Certified Organization
Vol.3, Special Issue 8, October 2015
Second National Conference on Emerging Trends and Intelligence Technologies [ETIT 2015]
On 3rd October 2015, Organized by
Dept. of CSE, Anand Institute Of Higher Technology, Kazhipathur, Chennai-603103, India
1.
SIMULATION RESULTS
Fig.4.Existing system waveform
Fig.5.Proposed system waveform
III.
CONCLUSION
Design based on resistive shunt feedback amplifier has proposed in this paper .Two types of technique implemented for
wideband LNA design and achieving low power application such as Cellular/PCS ,GPS receiver, Cordless phone,
Wireless LAN ,Automotive RKE.
Copyright @ IJIRCCE
www.ijircce.com
72
ISSN(Online)
ISSN (Print)
: 2320-9801
: 2320-9798
International Journal of Innovative Research in Computer and Communication Engineering
An ISO 3297: 2007 Certified Organization
Vol.3, Special Issue 8, October 2015
Second National Conference on Emerging Trends and Intelligence Technologies [ETIT 2015]
On 3rd October 2015, Organized by
Dept. of CSE, Anand Institute Of Higher Technology, Kazhipathur, Chennai-603103, India
REFERENCES
[1]N. Stanic, P. Kinget, and Y. Tsividis, “A 0.5 V 900 MHz CMOS receiver front end,” in Symp. Very Large Scale Integr. (VLSI) Circuits, Dig.
Tech.Paper, Jun. 2006, pp. 228–229.
[2]M. Brandolini, M. Sosio, and F. Svelto, “A 750 mV fully integrated direct conversion receiver front-end for GSM in 90-nm CMOS,” IEEE J.
Solid-State Circuits, vol. 42, no. 6, pp. 1310–1317, Jun. 2007. PARVIZI .
[3]H.-C. Chen, T. Wang, H.-W. Chiu, T.-H. Kao, and S.-S. Lu, “0.5-V 5.6-GHz CMOS receiver subsystem,” IEEE Trans. Microw. Theory Tech.,vol.
57, no. 2, pp. 329–335, Feb. 2009.
[4]A. Balankutty, S.-A. Yu, Y. Feng, and P. Kinget, “A 0.6-V zero-IF/low-IF receiver with integrated fractional-N synthesizer for 2.4-GHz ISMband applications,” IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 538–553, Mar. 2010.
[5]A. Balankutty and P. R. Kinget, “An ultra-low voltage, low-noise, high linearity 900-MHz receiver with digitally calibrated in-band feedforward
interferer cancellation in 65-nm CMOS,” IEEE J. Solid-State Circuits, vol. 46, no. 10, pp. 2268–2283, Oct. 2011.
[6]A. Shameli and P. Heydari, “A novel power optimization technique for ultra-low power RFICs,” in Proc. Int. Symp. Low Power Electron. Design,
Oct. 2006, pp. 274–279.
Copyright @ IJIRCCE
www.ijircce.com
73