Optimizing High-Voltage Common Mode
Rejection Performance of the ACPL-x6xL
Ultra-Low Power Optocouplers
White Paper
By: YEE Chee Weng, PENG Jia
Abstract
The ACPL-x6xL products are optically coupled ultra-low
power 10 MBd digital CMOS optocouplers that operate
with low power consumption, especially when the light
emitting diode (LED) operates at low current. When
a current is applied to drive the LED, common mode
rejection (CMR) can be affected by leakage paths inherent
to the LED. This paper describes the optimization of CMR
performance with split limiting resistors at the LED.
Introduction
Common mode noise is often seen at the system application level where there is a difference in the ground
levels of an isolating component’s input control circuitry
and output control circuitry. This is especially true when
a ground line is floating (device ground connected to a
common line).
In the ACPL-x6xL family, the common mode rejection
(CMR) specification indicates the ability to reject common
mode noise. This is also known as common mode transient
rejection (CMTR). CMTR describes the maximum tolerable
rising/falling rate of a common mode voltage (given in
volts per microsecond, V/s). The CMTR specification
includes the amplitude of the common mode voltage
(VCM) that can be tolerated. The common mode voltage
slew rate that the optocoupler can tolerate and hold
the correct output state is referred to as common mode
transient immunity (CMTI).
Common mode noise can be coupled to the optocoupler output by external circuitry. Common mode noise,
especially in a high electromagnetic interference (EMI)
environment, can adversely affect the output state of the
optocoupler through a conductive medium, primarily capacitive and inductive parasitics, Metallic printed circuit
board (PCB) tracks that operate at high frequency can
couple charge to the LED input pin or to the optocoupler
output pin through parasitic capacitors between adjacent
metal tracks.
It is often difficult to identify the root cause of common
mode noise or interference that is introduced by the
circuit/system/application or by other forms of external
factors that couple noise. When the source of common
mode noise is identified, corrective measures are easy to
implement by adding decoupling capacitors or filters to
the system, or by adding some form of shielding.
HVCMR Measurement
CMR Measurement
Figure 1 shows the experimental test setup to measure the
Avago Technologies ACPL-M61L’s high-voltage common
mode rejection (HVCMR). Three production samples were
randomly selected for the measurements. VDD1 is the
transmitter supply voltage used to turn on the LED.
Limiting resistor R1 is connected to the LED anode and R2
is connected to the LED cathode. R1 and R2 connected in
this common-mode fashion, rather than a single resistor,
enhances CMR performance.
Figure 2 shows VCM applied to both grounds. The main
purpose is to monitor glitches at the output of the Avago
ACPL-M61L optocoupler. VCM is applied at a specific frequency in the form of pulses and at a common-mode
voltage level (VCM). The optocoupler output will be logic
low (VOL) with LED turned on. When the LED is turned off
by shorting the anode and cathode to ground, the optocoupler output changes to a logic high (VOH).
ACPL-M61L
R1
VDD2
VO
AMP
VDD1
C1
R2
GND1
GND2
VCM
Figure1. HVCMR measurement setup
On the output side of the ACPL-M61L, there is a photodiode to sense light from the LED. The photodiode signal
is amplified by an output amplifier (AMP). VDD2 is the
supply voltage of the detector. Decoupling capacitor C1
is between VDD2 and GND2 and filters power supply line
noise. A common supply voltage (VCM) is applied between
the two grounds, GND1 and GND2.
Transient
rising edge
VCM is adjusted to a particular amplitude, and the rising/
falling edge is adjusted to a particular slope until dipping
glitches appear at the output during the common mode
voltage’s rising and falling edges as the LED is turned on
or until peaking glitches appear at the output during the
common mode voltage’s rising and falling edges when the
LED is turned off. Under certain circumstances, glitches may
be present only at the falling edge of VCM or vice-versa.
To determine CMR, two adjustments can be made to VCM.
The first adjustment is to lessen the slope of the rising/
falling edge of VCM until glitches disappear completely.
The second adjustment is to reduce the VCM level until the
glitches disappear completely.
CMRH is the slew rate measurement when the optocoupler output has a logic high (VOH) with no dipping glitches.
Likewise, CMRL is the slew rate measurement when the
optocoupler output has a logic low (VOL) when the peak
glitches
just disappear. Slew rate is defined in Equation 1.

VCM
Slew Rate =
V/s (Eq. 1)
t

VCM : Common mode voltage
t
: Time rate of transient rising edge or transient
falling edge
Transient
falling edge
$VCM
VCM
$t
VOH
LED off
Dip
Peak
VOL
LED on
Figure 2. CMR test with transient ramp-up and ramp-down VCM
2
Parasitic Capacitance Effect
CMR Performance vs. Resistor_ratio
Figure 3 shows the optocoupler’s parasitic capacitors,
Ccathode and Canode. Ccathode is larger than Canode by the
C_ratio factor. Both the LED cathode and the photodiode
anode have larger areas than other functional blocks.
Their ground planes (GND1 and GND2) and lead frames
are large, therefore contributing to higher capacitance.
5 V operating voltage
ACPL-M61L
R1
VDD2
Ianode
VO
VDD1
Canode
C1
For Avago ACPL-M61L optimal CMR performance, a
Resistor_ratio value of 1.6 is recommended, as shown in
Figure 4 (dotted line). This is to minimize Ianode leaking
through parasitic capacitor Canode and maximize the
LED bias current. Likewise, more current flows through
R2 than parasitic capacitor Ccathode. To minimize LED
bias current from being diverted away, the Resistor_ratio
must be chosen correctly to match the parasitic capacitor
impedance characteristics of Ccathode and Canode.
40
Ccathode
35
R2
GND2
Icathode
VCM
Figure 3. HVCMR measurement setup (parasitic capacitances shown)
On the other hand, Canode is parasitic capacitor between
the LED anode and the photodiode anode, but the LED
anode’s lead frame is smaller than the photodiode anode’s
ground plane and lead frame. Therefore, Canode is smaller
than Ccathode. The C_ratio is defined in Equation 2.
Ccathode
C_ratio =
(Eq. 2)
Canode
Canode is between the LED anode and the GND2 ground.
Ccathode is between the LED cathode and the GND2
ground.
The parasitic capacitors leak current away from the
current flowing through the LED during AC operation.
Ccathode and Canode behave as an open circuit during DC
operation, and there is no DC current leakage.
Though resistors R1 and R2 are usually recommended to
have equal value, the parasitic capacitors Ccathode and
Canode cannot be neglected since the two terminals no
longer balance in common mode. Different R1/R2 ratios
are used.
Since Ccathode is bigger than Canode, the impedance of
Ccathode is smaller than the impedance of Canode. More
current (Icathode) will leak through Ccathode and less current
(Ianode) will leak through Canode during AC operation. In
order to minimize the leakage current flowing through
Canode and Ccathode, R1 and R2 are placed at the anode
and at the cathode of the LED respectively. Their resistance
ratio factor (Resistor_ratio) is defined by Equation 3.
R1
Resistor_ratio =
(Eq. 3)

R2
R1 is the limiting resistor between VDD1 and LED anode
R2 is the limiting resistor between LED cathode and
GND1.
3
CMR kV/Ms
GND1
33.3 33.8
33.3
24.4 25.6
24.2
30
25
20
15
10
5
0
1.2
Test conditions
LED = 2 mA
LED = 1.6 mA
VDD1 = 5 V, VDD2 = 5 V
R1 = R2 = ±1% Tolerance
1.3
1.4
1.6
1.5
Resistor ratio
1.7
1.8
Figure 4. CMR performance vs. Resistor_ratio (R1 and R2 ±1% tolerance,
VDD1 = 5 V, VDD2 = 5 V)
With a Resistor_ratio value from 1.4 to 1.6, a CMR of more
than 33 kV/s (blue graph ) is achieved with a 2.0 mA
LED bias current. With a smaller 1.6 mA LED drive current,
good CMR performance of more than 24 kV/s (red graph
) is achieved.
R1 + R2 = RTotal (Eq. 4)
R1
= 1.6 (Eq. 5)
R2
Substitute Eq. 5 into Eq. 4,
R
R2 = Total (Eq. 6)

2.6
R1 and R2 can be calculated with Equations 4 to 6. In
order to achieve excellent CMR performance, R1 = 1.1 k
and R2 = 680  are chosen to produce 2 mA of LED drive
current (blue graph ), while R1 = 1.4 k and R2 = 910 
are chosen for 1.6 mA of LED drive current (red graph ).
These values of resistors are widely available and are
highly recommended to have ±1% tolerance. The printed
circuit board should have good shielding to minimize EMI
that may affect CMR performance.
R1 –10%
R2 +10%
35 kV/μs
30 kV/μs
25 kV/μs
20 kV/μs
R1 ±1%
R2 ±1%
R1 –10% R1 +10% R1 +10%
R2 –10% R2 +10% R2 –10%
34.9
kV/μs
33.9 kV/μs
30.9 kV/μs 34.9 kV/μs
25.6 kV/μs
70
60
50
CMR kV/Ms
Figure 5 shows ACPL-M61L CMR performance when R1
and R2 have a ±10% tolerance. It can be seen that given
the same degree of tolerance in the resistor values, the
Resistor_ratio remains 1.6 and the optocoupler CMR performance remains optimized. However, when the resistors
do not rise or fall with the same tolerance (example R1
has a -10% tolerance but R2 has a +10% tolerance), CMR
performance is compromised because the Resistor_ratio
changes from the optimum value of 1.6.
58.7
58.7
58.7
58.7
58.7
57.6
58.7
58.7
58.7
55.4
40
30
Test conditions
LED = 2 mA
LED = 1.6 mA
VDD1 = 3.3 V, VDD2 = 3.3 V
R1 = R2 = ±1% Tolerance
20
10
0
1.2
1.3
1.4
1.6
1.5
Resistor ratio
1.7
Figure 6. CMR performance vs. Resistor_ratio (R1 and R2 ±1% tolerance,
(VDD1 = 3.3 V, VDD2 = 3.3 V)
15 kV/μs
R1 –10%
R2 +10%
R1 ±1%
R2 ±1%
R1 –10%
R2 –10%
R1 +10%
R2 +10%
10 kV/μs
5 kV/μs
70 kV/μs
0 kV/μs
60 kV/μs
58.7 kV/μs 58.7 kV/μs 58.7 kV/μs
50 kV/μs
40 kV/μs
58.7 kV/μs 58.7 kV/μs
Test conditions : LED = 2 mA
LED = 1.6 mA
1.8
VDD1 = 5 V
VDD2 = 5 V
R1 +10%
R2 –10%
30 kV/μs
Figure 5. CMR performance versus R1 and R2 tolerance,
(VDD1 = 5 V, VDD2 = 5 V)
3.3 V operating voltage
The recommended Resistor_ratio value of 1.6 can be
applied to a 3.3 V operating supply voltage, as shown in
Figure 6. With a Resistor_ratio range of 1.3 to 1.7, even
a lower LED drive current of 1.6 mA is able to exhibit
superior CMR performance. Both the blue graph
and
red graph
show a CMR of more than 50 kV/s. With a
3.3 V input supply voltage to bias the LED, a lower total
resistance value (R1+R2) is needed to drive the LED. More
current is concentrated to bias the LED and optimize the
CMR performance.
Similar to the 5 V operating voltage condition, ACPL-M61L
CMR performance is consistent when R1 and R2 with
±10% tolerance are chosen for a 3.3 V operating supply
voltage. As shown in Figure 7, a Resistor_ratio value of
1.6 applies when R1 and R2 tolerance changes relatively.
Again, CMR performance is not compromised as long as
the recommended Resistor_ratio value is set with ±1%
tolerance resistors.
For product information and a complete list of distributors, please go to our web site:
20 kV/μs
10 kV/μs
31.9 kV/μs
0 kV/μs
Test conditions : LED = 2 mA
LED = 1.6 mA
VDD1 = 3.3 V
VDD2 = 3.3 V
Figure 7. CMR performance vs. R1 and R2 tolerance,
(VDD1 = 3.3 V, VDD2 = 3.3 V)
Conclusion
Common mode noise occurs at the system application level where there is a difference in the ground level
of the optocoupler’s input control circuitry and output
control circuitry. It is difficult to identify the root cause
of common mode noise or interference. With ultra-low
power operation, the ACPL-x6xL family’s CMR performance can be optimized through application of split
limiting resistors at the LED.
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AV02-3053EN - May 25, 2012