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Chapter IV
Basic Boolean logic functions
The basic Boolean logic (also called bit logic) operations can be realized by means of
corresponding configuration of contacts.
AND and OR connections
The Boolean AND connection (operation) output has the signal state “1”, only when all of the
AND operation inputs have signals “1”. If even one input has a signal “0”, then the output
signal is also “0”. The implementation of Boolean AND operation in LAD, FBD and STL is
shown in Fig. 0.1. The AND connection can have more than two inputs.
I 10.0
0
1
0
1
I 10.1
0
0
1
1
Q 10.0
0
0
0
1
Fig. 0.1. Boolean AND connection with signal states and implementation in FBD, STL and LAD languages
The Boolean OR connection (operation) output signal is “1” if even one of the OR operation
inputs has signal “1”. The output will be “0” only if all connected inputs have signal “0”. The
implementation of Boolean OR operation in LAD, FBD and STL is shown in Fig. 0.2. The
OR connection can have more than two inputs.
I 10.2
0
1
0
1
I 10.3
0
0
1
1
Q 10.1
0
1
1
1
Fig. 0.2. Boolean OR connection with signal states and implementation in FBD, STL and LAD languages
In STEP 7 the AND and OR operations results are deposited in the RLO bit (result of the
logic operation). The RLO bit is a bit of the status words, which can have signal “1” or “0”
[6]. By first AND or OR operation the signal state of the operand is asked and the operation
result is stored directly in the RLO bit. The second operation also asks the signal state of an
operand. Now the result of the second operation is linked with the RLO bit value by following
the rules of Boolean algebra and the result is stored then in the RLO bit. These connection
operations are ending with the assignment of the RLO bit value to operand/operands or with a
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conditional jump. Sometimes it is necessary to set the RLO bit signal state to “0” or “1”
without using any operands. STEP 7 commands CLR and SET can do this in the STL
language.
The AND and OR connections can be combined to more complex operations in the program,
like AND-before-OR and OR-before-AND connections [16]. In AND-before-OR connection
the AND operation output is connected to an OR operation input. It is vice versa in
OR-before-AND connection. The implementation of these operations in FBD is shown in Fig.
0.3.
Fig. 0.3. The implementation of AND-before-OR and OR-before-AND connection in FBD language
AND-before-OR operation output has signal “1” if at least one of the AND connection results
is signal “1”. OR-before-AND operation output has signal “1” if both OR connections have
signal “1” as the result.
Negation
The Boolean negation is used to invert an operand or variable signal state. It means that the
output signal of the negation is “1” if the input signal is “0” and vice versa. The Boolean
negation implementation in LAD, FBD and STL is shown in Fig. 0.4.
I 10.0
0
1
Q 10.0
1
0
Fig. 0.4. Boolean negation operation with signal states and implementation in FBD, STL and LAD
languages
The negation can be used also by AND and OR connection outputs (Fig. 0.5). AND
connection with negation is called NAND connection and OR connection is called NOR
connection [6].
Fig. 0.5. NAND and NOR connection in FBD language
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The operation output signals can also be inverted by using the Boolean negation (NOT
operation). In Fig. 0.6 the output Q 10.3 signal is inverted.
Fig. 0.6. Inverted output in STL, FBD and LAD languages
Exclusive-OR connection
The Boolean Exclusive-OR connection (XOR) with two inputs has the output signal “1” if
both inputs have different signal states. This means that if one input has signal “1” and the
second one signal “0”, then XOR operation result is signal “1”. The implementation of
Boolean XOR connection in LAD, STL and FBD is shown in Fig. 0.7.
I 10.0
0
1
0
1
I 10.1
0
0
1
1
Q 10.0
0
1
1
0
Fig. 0.7. Boolean XOR operation with signal states and implementation in FBD, STL and LAD languages
The XOR operation can have more than two inputs. In that case, the result is signal “1” if the
number of inputs, which have signal states “1”, is an odd number.
XOR connection can be used together with AND and OR operations.
SR and RS flip-flops
SR and RS flip-flops are used to lengthen the lifetime of a briefly occurred signal state over
one program cycle. Therefore the SR and RS flip-flops are also called storage functions.
The use and operation of the SR flip-flop (dominant reset) and RS flip-flop (dominant set) is
shown in Figs. 0.8 and 0.9.
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For SR flip-flop if the input S (set) is “1” and the input R (reset) is “0”, then the output Q is
set to “1” and remains in that state until reset. A change in the input S has no effect on the
output Q if it has signal “1”. The output Q is reset to signal “0” if a signal “1” is given to input
R, unrelated to which signal state is currently on the input S. For this reason SR flip-flop is
called a dominant reset.
Q 10.0
0
0
0
0
1
1
1
1
I 10.0
0
0
1
1
1
0
0
1
I 10.1
0
1
0
1
0
0
1
1
Q 10.0
0
0
1
0
1
1
0
0
Fig. 0.8. SR flip-flop (dominant reset) signal states and implementation in FBD, STL and LAD languages
Q 10.1
0
0
0
0
1
1
1
1
I 10.2
0
0
1
1
1
0
0
1
I 10.3
0
1
0
1
0
0
1
1
Q 10.1
0
0
1
1
1
1
0
1
Fig. 0.9. RS flip-flop (dominant set) signal states and implementation in FBD, STL and LAD languages
For RS flip-flop if the input R is “1” and the input S is “0”, then the output Q is set to “0” and
remains until set. The output is set to “1” if a signal “1” is given to input S, unrelated to which
signal state is currently on the input R. For this reason it is called a dominant set. The change
in the input S has no effect on the output Q if it has signal “1” and input R has signal “0”.
RS and SR flip-flops can be made from AND and OR connections (Fig. 0.10).
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a)
b)
Fig. 0.10. SR (a) and RS (b) flip-flops using AND and OR connections in FBD
The set and reset of an operand/variable can be made in different parts of the user program by
using SET (S) and RESET (R) functions [6]. With these functions the RS and SR flip-flops
are split into separate SET and RESET operations. The drawback of splitting is losing the
program overview regarding in which condition an operand is set or reset. On the other hand,
one condition can be used for more than one SET and/or RESET operations (Fig. 0.11).
Fig. 0.11. Usage of SET and RESET functions in STL, FBD and LAD languages
Edge detection
Edge detection is used to discover signal state changes. A rising edge (signal changes from
“0” to “1”) is called a positive
1
edge and a falling edge (signal
Signal
changes from “1” to “0”) a
0
negative edge [6]. The edge
1
detection signal (pulse) is
Positive edge
formed from a continuous
0
signal, which is only one
1 program cycle
program cycle long (Fig. 0.12).
1
Negative edge
0
1 program cycle
Fig. 0.12. Duration of edge detection signals
For the realization of edge
detection with a PLC an
operand (variable) is required,
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which stores the signal state of the previous program cycle. There are standard functions to
detect edge changes. However, the edge detection can be made also with AND operation and
SR/RS flip-flops.
The rising edge (function) detects a signal state change from “0” to “1” by the specified input
operand IO (Fig. 0.13). The current signal state of the input operand IO at the RLO is
compared with the previous program cycle signal state of the input operand (edge operand
EO). If the previous signal state of the input operand was “0” and the RLO is “1”, then the
RLO will be “1” (pulse) and the impulse output IPO signal is set to “1” for one program
cycle. In all other cases the RLO and the impulse operand IPO signal states are “0”. The
previous program cycle falling edge detection RLO is stored in the edge operand EO [6].
IO
EO
&
Program cycle
EO
IPO
S
Input operand IO
IO
R
Q
Impulse operand IPO
Edge operand EO
1
2
3
…
n
1
0
1
0
1
0
Fig. 0.13. Rising edge detection with AND operand and SR flip-flop and signal states of the operands
Positive (rising) edge detection function of STEP 7 is shown in Fig. 0.14.
Fig. 0.14. Positive edge detection in STL, FBD and LAD languages
The falling edge (function) detects a signal state change from “1” to “0” by the specified input
operand IO (Fig. 0.15). The current signal state of the input operand at the RLO is compared
with the previous program cycle signal state of the input operand IO (the edge operand EO). If
the previous signal state of the input operand was “1” and RLO is “0”, then the RLO will be
“1” (pulse) and the impulse output IPO signal is set to “1” for one program cycle. In all other
cases the RLO and the impulse operand IPO signal states are “0”. The previous program cycle
falling edge detection RLO is stored in the edge operand EO [6].
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IO
&
IPO
EO
Program cycle
EO
R
Input operand IO
1
2
…
n
n+1
1
0
IO
S
Q
Impulse operand IPO
Edge operand EO
1
0
1
0
Fig. 0.15. Falling edge detection with AND operand and RS flip-flop and signal states of the operands
Negative (falling) edge detection function of STEP 7 is shown in Fig. 0.16.
Fig. 0.16. Negative edge detection in STL, FBD and LAD languages
In IEC 61131 commands R_TRIG (rising edge) and F_TRIG (falling edge) are used to detect
signal state (edge) changes.
Logical connective
Two operands/variables or one operand/variable and one constant value are linked together by
logical connectives. A logical connective does not transfer bit values to the next binary
position.
The standard IEC 61131 uses basic Boolean logic functions for Logical connectives. These
are AND, OR, XOR (Exclusive OR) and NOT (Negation).
STEP 7 logical connectives are always Word Logic operations, which compare pairs of
operands according to Boolean logic (bit by bit). The operands or the constant must be of data
type WORD (16 bits) or DWORD (32 bits). In Table 0.1 STEP 7 logical connective functions
in STL, FBD and LAD languages are shown.
Table 0.1. Logical connective functions in STEP 7
Name
AND
OR
XOR
STL
AW
OW
XOW
NOT
INVI
Word
FBD/LAD
WAND_W
WOR_W
WXOR_W
INV_I
Double Word
STL
FBD/LAD
AD
WAND_DW
OD
WOR_DW
XOD WXOR_DW
INVD
INV_DI
Comment
Logical AND connection
Logical OR connection
Logical exclusive OR
connection
Negation, also called as Ones
Complement
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STEP 7 uses accumulators ACCU 1 and ACCU 2 (Fig. 0.17) for logical connective
operations. Accumulators are special registers in CPU, which are used for buffering the data
used in a logical connective operation (read more about it in module 5.1). This means that
firstly the operand 1 (IN 1) data is loaded to ACCU 1. By loading operand 2 (IN 2) data the
data in ACCU 1 is shifted to ACCU 2 and then the operand 2 (IN 2) data is loaded to ACCU
1. The content of ACCU 2 (operand 1) is combined with the content of ACCU 1 (operand 2)
based on the logical connective operation. The operation result is stored in ACCU 1, which is
provided to the output operand (OUT) [6].
In logical AND connection the resulting (double) word bit is “1”, when the corresponding bits
of both input operands are “1” in the logical connective operation (Table 0.3). Logical AND
connection can be used to hide binary digits not needed or non-relevant. For this a mask is
used, where necessary or relevant binary positions have signal state “1” and others signal state
“0” (to be hidden). The mask can be a constant or a variable. The masking operand and the
mask are logically AND connected, by which the non-relevant binary digits are hidden (signal
state “0”) and the relevant binary digits states remain unchanged. In Table 0.3 input operands
IN 1 bit 2 and 3 are masked. Input operand IN 2 is used as a mask.
ACCU 1
ACCU 2
L MW 20
MW 20
………
L MW 22
MW 22
MW 20
AW
T MW 30
Logical connective
operation
Result
Fig. 0.17. Logical AND connection operation in STEP 7 and its visualization in STL and FBD languages
In logical OR connection the resulting (double) word bit is “1”, when at least one of the
corresponding bits of both input operands in the logical connective operation is “1” (Table
0.3). This operation is used to complement bit patterns. One or several binary positions with
the signal state “1” are inserted into a given bit pattern with logical OR connection. In Table
0.3 input operand IN 1 bit 2 and 3 signal states have to be “1”. So the input operand IN 1 bit
pattern is complemented by the signal state “1” in bit 2 and 3.
In logical XOR connection the resulting (double) word bit is “1”, when only one of the
corresponding bits of both input operands in the logical connective operation is “1” (Table
0.3). This operation allows discovering an operand bit signal state changes in one or several
binary positions (bit pattern). For this the operand old and new signal states are logically XOR
connected. At each position, where a signal change from “0” to “1” or “1” to “0” occurs, the
XOR operation provides the signal state “1”. Table 0.3 shows that signal changes have
occurred in bit 1 (form “1” to “0”) and 2 (form “0” to “1”). The input operand IN 1 has old
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signal states and input operand IN 2 new signal states. If after XOR operation an AND
operation is executed with new signal states (Table 0.2), then this allows us to discover only
signal state changes from “0” to “1”. For signal state changes from “1” to “0” an AND
operation with old signal states has to be used after XOR operation (Table 0.2).
Table 0.2. Signal state change discovering from “1” to “0” or from “0” to “1”
Signal change
discovering
Only signal changes
from “0” to “1” are
needed
Only signal changes
from “1” to “0” are
needed
Commands
Sample
Comment
L MW 20
L EW 10
XOW
L EW 10
UW
L MW 20
L EW 10
XOW
L MW 20
UW
…. 1010
…. 1100
…. 0110
…. 1100
…. 0100
…. 1010
…. 1100
…. 0110
…. 1010
…. 0010
Word with old signal states
Word with new signal states
Modified bit pattern in ACCU 1
Word with new signal states
End result in ACCU 1
Word with old signal states
Word with new signal states
Modified bit pattern in ACCU 1
Word with old signal states
End result in ACCU 1
By logical NOT (negation) connection result is the inverted input operand value (Table 0.3).
Read more about it in module 7.3.4.
Table 0.3. Samples of Logical connective operations
Function
Sample
AND
IN 1: …. 1010
IN 2: …. 1100
OUT: …. 1000
OR
IN 1: …. 1010
IN 2: …. 1100
OUT: …. 1110
XOR
IN 1: …. 1010
IN 2: …. 1100
OUT: …. 0110
NOT
IN 1: …. 1010
OUT: …. 0101
Some samples of the STEP 7 logical connectives are shown in Fig. 0.18. A logical OR
connection with word variables is shown in STL, a logical XOR connection with double word
variables is shown in FBD and a Ones Complement conversion (negation) with double word
variable is shown in LAD.
Fig. 0.18. Some samples of logical connective functions in STL, FBD and LAD languages
Self check
1. Which of these statements are true for the Boolean AND connection presented
below (multiple answers)?
a. Output is “1” if one input is “1”.
b. Output is “1” if all inputs are “1”.
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c. Output is “1” if exactly one of the inputs is “1”.
d. Output is “0” if all inputs are “0”.
2. Which of these statements are true for the Boolean OR connection presented below
(multiple answers)?
a. Output is “1” if one input is “1”.
b. Output is “1” if all inputs are “1”.
c. Output is “1” if exactly one of the inputs is
“1”.
d. Output is “0” if all inputs are “0”.
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3. NAND connection in STL languages looks as shown in …
a.
b.
d.
c.
4. In the STL language the presented program (below) looks in FBD languages as
shown in …
a.
b.
c.
d.
5. Which of these statements are true for the Boolean XOR operation presented below
(multiple answers)?
a. Output is “1” if at least one input is “1”.
b. Output is “1” if all inputs are “1”.
c. Output is “1” if exactly one of the inputs is 1.
d. Output is “0” if all inputs are “0”.
6. What is a RS flip-flop called (multiple
answers)?
a. a dominant set
b. a dominant reset
c. a storage function
7. A falling edge is a:
a. signal “0”
b. signal “1”
c. signal change from “1” to “0”
d. signal change from “0” to “1”
8. Logical AND connection of a word can be used to …
a. hide variable values not needed.
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b. hide binary digits not needed or non-relevant in a bit pattern.
c. find signal state changes from “1” to “0”.
d. find signal state changes from “1” to “0”.