Lecture #16
ANNOUNCEMENTS
• Midterm #1 Results:
– N=191; ave=44.3; σ=7.2; max=50; min=10
• HW#5 will be posted online today
OUTLINE
– Propagation delay
– Energy consumption of simple RC circuit
– RC circuit transient response examples
Reading for next Lecture
Textbook by J. Rabaey (online): Chapter 3
EECS40, Fall 2003
Lecture 16, Slide 1
Prof. King
Voltage Ranges for Digital Signals
• A digital signal varies with time, typically
between between ground (0 Volts) and the
power supply voltage (Vsupply).
• A digital voltage signal has two defined states
“high” (corresponding to logical state 1) or
“low” (corresponding to logical state 0)
• Each of the two states corresponds to a
range of voltages, for example:
logical 1 state: voltage > Vsupply/2
logical 0 state: voltage < Vsupply/2
EECS40, Fall 2003
Lecture 16, Slide 2
Prof. King
1
Propagation Delay tp
• The propagation delay tp of a logic gate defines
how quickly the output voltage responds to a
change in input voltage. It is measured between
the 50% transition points of the input and output
voltage waveforms.
Example: Output voltage changing from “low” to “high”
Vsupply
Vin
Vout
(
)
Vout (t ) = Vsupply 1 − e − t / RP C
0.5Vsupply
0 0.69RPC
EECS40, Fall 2003
time
Lecture 16, Slide 3
Prof. King
Formula for Propagation Delay tp
• A logic gate can display different response times
for rising or falling input waveforms, so two
definitions of propagation delay are necessary.
t pLH + t pHL
tp =
2
Example: Output voltage changing from “high” to “low”
Vout (t ) = Vhigh e − t / RN C
Vsupply
0.5Vsupply
Vout
Vin
0 0.69RNC
EECS40, Fall 2003
time
Lecture 16, Slide 4
Prof. King
2
Energy Consumption of Simple RC Circuit
• In charging a capacitor, the energy which is
1
2
delivered to the capacitor is CVsupply
2
• The energy delivered by the source is
∞
∞
∞
 dv 
2
w = ∫ p (t )dt = ∫ v(t )i (t )dt = ∫ Vsupply  C dt = CVsupply
 dt 
0
0
0
How much energy is delivered to the resistor RP?
RP
t=0
i
Vsupply
+
−
+
v
C
RN
–
EECS40, Fall 2003
Lecture 16, Slide 5
Prof. King
• In discharging a capacitor, the energy which is
1
2
delivered to the resistor RN is CVsupply
2
• Thus, in one complete cycle (charging and
discharging), the total energy delivered by the
2
voltage source is CVsupply
RP
Vsupply
EECS40, Fall 2003
+
−
t = t0
RN
Lecture 16, Slide 6
C
Prof. King
3
Power-Delay Product
• The propagation delay and power consumption
of a digital logic gate are related:
– The smaller the propagation delay, the higher the
switching frequency f can be.
Æ higher dynamic power consumption
2
pdynamic ∝ fCVsupply
• For a given digital-IC technology, the product of
power consumption and propagation delay (the
“power-delay product”) is generally a constant.
• PDP is simply the energy consumed by the logic gate
per switching event, and is a quality measure.
EECS40, Fall 2003
Lecture 16, Slide 7
Prof. King
RC Circuit Transient Analysis Example
The switch is closed for t < 0, and then opened at t = 0.
Find the voltage vc(t) for t ≥ 0.
t=0
3 kΩ
i
5V
+
−
+
vc
10 µF
2 kΩ
–
1.
Determine the initial voltage vc(0)
EECS40, Fall 2003
Lecture 16, Slide 8
Prof. King
4
3 kΩ
i
5V
+
−
+
vc
10 µF
2 kΩ
–
2. Determine the final voltage vc(∞)
3. Calculate the time constant τ
EECS40, Fall 2003
Lecture 16, Slide 9
Prof. King
vc (t ) = vc (∞) + [vc (0) − vc (∞)] e −t /τ
EECS40, Fall 2003
Lecture 16, Slide 10
Prof. King
5
DRAM (Dynamic Memory Device) Example
• The operation of a DRAM cell (which stores one bit
of information) can be modeled as an RC circuit:
to read data stored in cell
R=10kΩ
+
+
Ccell=0.1pF
Vcell
Cbit-line=1 pF
–
Vbit-line
–
• Suppose the bit line is pre-charged to 1 V before the
cell is read, and that the cell is programmed to 2 V.
What is the final value of the bit-line voltage, after
the switch is closed?
EECS40, Fall 2003
Lecture 16, Slide 11
Prof. King
DRAM Example (cont’d)
• The charges stored on Ccell and Cbit-line prior to
−13
−13
reading are Qcell ,initial = CcellVcell ,initial = (10 F)(2V ) = 2 ×10 C
and Qbit −line ,initial = Cbit −lineVbit −line ,initial = (10 −12 F)(1V ) = 1×10 −12 C
Qtotal ,initial = Qcell ,initial + Qbit −line ,initial = 1.2 × 10 −12 C
• The final voltages on each capacitor are equal.
⇒ Qtotal , final = CcellV final + Cbit −lineV final
• Total charge is conserved:
Qtotal , final = (Ccell + Cbit −line )V final = Qtotal ,initial
V final =
EECS40, Fall 2003
Qtotal ,initial
Ccell + Cbit −line
1.2 ×10 −12 C
=
≅ 1.09 Volts
1.1×10 −12 F
Lecture 16, Slide 12
Prof. King
6
DRAM Example (cont’d)
• Sketch the bit-line voltage waveform
Vbit-line (V)
1
t (ns)
0
• Is energy conserved? Explain.
EECS40, Fall 2003
Lecture 16, Slide 13
Prof. King
The Road Ahead
• We will be studying semiconductor devices
and technology for the next several weeks
– How does a transistor work?
(need to learn about semiconductors and diode devices first)
– How are transistors used as amplifiers?
• modeled as dependent current source
– How are transistors used to implement digital
logic gates?
• modeled as resistive switch
(circuit performance is limited by RC delay)
EECS40, Fall 2003
Lecture 16, Slide 14
Prof. King
7