Lecture #37
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OUTLINE
» Interconnect parameters
» Interconnect modeling
Reading (Rabaey et al.)
Chapter 4: pp. 104-127
Chapter 5: pp. 172-173
EECS40, Fall 2003
Lecture 37, Slide 1
Prof. King
Interconnects
• An interconnect is a thin-film wire that electrically
connects 2 or more components in an integrated circuit.
• Interconnects can introduce parasitic (unwanted)
components of capacitance, resistance, and inductance.
These “parasitics” detrimentally affect
– performance (e.g. propagation delay)
– power consumption
– reliability
• As transistors are scaled down in size and the number of
metal wiring layers increases, the impact of interconnect
parasitics increases.
→ Need to model interconnects, to evaluate their impact
EECS40, Fall 2003
Lecture 37, Slide 2
Prof. King
1
Interconnect Resistance & Capacitance
Metal lines run over thick
oxide covering the substrate
Æ contribute RESISTANCE
& CAPACITANCE to the
output node of the
driving logic gate
VDD
PMOS
NMOS
GND
EECS40, Fall 2003
Lecture 37, Slide 3
Prof. King
Wire Resistance
Rwire =
ρL
HW
= Rs
L
W
L
H
W
EECS40, Fall 2003
Lecture 37, Slide 4
Prof. King
2
Interconnect Resistance Example
Typical values of Rn and Rp are ~10 kΩ, for W/L = 1
… but Rn, Rp are much lower for large transistors
(used to drive long interconnects with reasonable tp)
Compare with the resistance of a 0.5µm-thick Al wire:
R = ρ / H = (2.7 µΩ-cm) / (0.5 µm) = 5.4 x 10-2 Ω /
Example: L = 1000 µm, W = 1 µm
Æ Rwire = R (L / W)
= (5.4 x 10-2 Ω / )(1000/1) = 54 Ω
EECS40, Fall 2003
Lecture 37, Slide 5
Prof. King
Wire Capacitance: The Parallel Plate Model
single wire over
a substrate:
electric field lines
tdi
Relative Permittivities
C pp =
EECS40, Fall 2003
ε di
t di
WL
Lecture 37, Slide 6
Prof. King
3
Parallel-Plate Capacitance Example
• Oxide layer is typically ~500 nm thick
• Interconnect wire width is typically ~0.5 µm wide (1st level)
⇒ capacitance per unit length = 345 fF/cm = 34.5 aF/µm
Example: L = 30 µm
Æ Cpp ≅ 1 fF (compare with Cn~ 2 fF)
EECS40, Fall 2003
Lecture 37, Slide 7
Prof. King
Fringing-Field Capacitance
For W / tdi < 1.5, Cfringe is dominant
Wire capacitance per unit length:
cwire ≅ c pp + c fringe =
EECS40, Fall 2003
wε di
2πε di
+
t di
log(t di / H )
Lecture 37, Slide 8
w =W −
H
2
Prof. King
4
Modeling an Interconnect
Problem: Wire resistance and capacitance to underlying
substrate is spread along the length of the wire
“Distributed RC line”
We will start with a simple model…
EECS40, Fall 2003
Lecture 37, Slide 9
Prof. King
Lumped RC Model
Model the wire as single capacitor and single resistor:
• Cwire is placed at the end of the interconnect
→ adds to the gate capacitance of the load
• Rwire is placed at the logic-gate output node
→ adds to the MOSFET equivalent resistance
Rwire
Cwire
substrate
EECS40, Fall 2003
Lecture 37, Slide 10
Prof. King
5
Cascaded CMOS Inverters w/ Interconnect
Equivalent resistance Rdr
Vin
(rwire, cwire, L)
Cintrinsic
Cfanout
Using “lumped RC” model for interconnect:
Rdr
Rwire
Cintrinsic
Cwire
Cfanout
τ D = Rdr Cintrinsic + ( Rdr + Rwire )(Cwire + C fanout )
= Rdr Cintrinsic + ( Rdr + Rwire )C fanout + ( Rdr + Rwire )Cwire
EECS40, Fall 2003
Lecture 37, Slide 11
Prof. King
Effect of Interconnect Scaling
2πε di L 
 L   ε di
2
(
)
WL
+
RwireCwire =  ρ

 ∝ ρε di L

log(t di / H ) 
 WH   t di
• Interconnect delay scales as square of L
⇒ minimize interconnect length!
• If W is large, then it does not appear in RwireCwire
• Capacitance due to fringing fields becomes more significant
as W is reduced; Cwire doesn’t actually scale with W for small W
EECS40, Fall 2003
Lecture 37, Slide 12
Prof. King
6