NASA Electronic Parts and Packaging (NEPP) Program
Surge Current Testing and
Derating for Solid Tantalum
Capacitors
Alexander Teverovsky
Parts, Packaging, and Assembly Technologies Office, Code
562, GSFC/ASRC Federal Space and Defense
Alexander.A.Teverovsky@nasa.gov
Outline
Do we need limiting resistors in series with tantalum capacitors?
 Surge current testing (SCT).
 Mechanism of failures.
 History of current derating.
 MIL-PRF-55635 requirements.
 Specifics of SCT.
 Effective resistance of the circuit, Reff.
 Correlation between Reff and equivalent
series resistance (ESR).
 Effect of ESR on VBR.
 Specified and real ESR values.
 Derating of surge currents.
 Conclusion.
ESA Sept. 2013
2
Mechanisms of Surge Current Failures
 Sustained scintillation breakdown.
If current is not limited, self-healing does not
have time to develop.
 Electrical oscillations in circuits with
high inductance.
Ignition due to exothermic reaction in
 Local overheating of the cathode. tantalum capacitors. Prymak 2006.
 Mechanical damage to tantalum
pentoxide dielectric caused by the
Ta
impact of MnO2 crystals.
MnO2
 Stress-induced-generation of electron
traps caused by electromagnetic forces
developed by high currents.
 All models require high currents that correspond to high rates
of voltage increase.
ESA Sept. 2013
3
Effect of dV/dt on Breakdown Voltage
(dV/dt ~ 105 to 106 V/sec)
160
140
VBR_3SCT, V
 Scintillation breakdown voltage,
VBRscint (dV/dt ~ 1 to 5 V/sec) is always
greater than the surge current
breakdown voltage, VBRSCT
Effect of dV/dt on VBR for 50V capacitors
120
100
80
60
40
 The rate of voltage increase changes
charges and electrical field
at the interface.
Accumulation of electrons
on traps at the MnO2-Ta2O5
interface with time increases
the barrier, the level of electron
injection, and the probability of
avalanching.
40
60
80
100
120
140
160
VBR_scint, V
Ta
MnO2
Fast voltage raise
Slow voltage raise
 A theory explains decreasing VBR with a rate of voltage increase.
 A resistor in series with a capacitor reduces dV/dt and failures.
ESA Sept. 2013
4
Requirements for Limiting Resistors
 History of requirements for circuit resistance (Rac):
 In the 1960s: 3 Ω per each volt of operating voltage.
 By the 1980s: 1 Ω per each volt.
 From the 1990s: 0.1 Ω per volt or 1 ohm, whichever is greater.
 Manufacturers consider surge current failures as the major
reason for voltage derating.
 Do we need derating of currents in addition to voltage?
 The limit for acceptable surge currents is set by the SCT
conditions: the current during applications should not exceed
the current during testing: Iappl.< Itest “use as tested”
 Improvements in reliability and the need to increase the
efficiency of power supply systems resulted in reduction of Rac.
 Can we allow circuit designs without Rac?
 Need a closer look at how the Itest is specified.
ESA Sept. 2013
5
MIL-PRF 55365 Requirements
 SCT per MIL-PRF-55365H:
 Nc = 4 surge cycles.
 Energy storage capacitor, CB = 20×CDUT
 Test voltage: VR
 Charge time, tch, and discharge time, tdisch, ≥ 1sec.
 Total DC resistance of the circuit, RC, including the wiring, fixturing, and output
impedance of the power supply should not exceed Rc = 1 Ω.
 Measurements after SCT: DCL, C, DF (still no requirements for ESR)
 Itest ≥ VR/(Rtc + ESRspec), where resistance of the test circuit, Rtc= 1 Ω.
 Failure condition: I = 1A after 1ms for C ≤ 330uF; 10ms for C ≤ 3.3mF, and
100ms for C > 3.3 mF.
New specification recognizes the role of
 Before 12/1/2012:
ESR as a limiting factor for surge currents.
 Nc = 10.
VR
Rated surge current: I
 tdisch = tch = 4 sec.
surge =
 Rc ≤ 1.2 Ohms.
ESRspec + 1
 CB ≥ 50 mF.
No specifics on Itest verification.
I
was not addressed.
test
ESA Sept. 2013
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Verification of SCT Conditions
5
1
4
0.8
3
0.6
I_0.1 Ohm
I_0.4 Ohm
I_0.7 Ohm
V_0.1 Ohm
V_0.4 Ohm
V_0.7 Ohm
2
1
V/Vo
 measurements of voltage after
some time of spike initiation;
 measurements of a current
spike amplitude.
I/Vo, A/V
 Two methods of SCT
verification:
SCT simulations for 220 µF capacitor at
Lc= 400 nH, ESR = 0.1Ω Rc-var
0.4
0.2
0
0
0
100
200
300
400
time, uS
 The rate of voltage increase is critical for SCT.
 A high current spike is a byproduct of the fast voltage raise,
rather than the major cause of failure.
 Even minor variations (~0.1 Ω) of Rc affect dV/dt and results
of SCT.
The amplitude of the current spike is the most adequate
characteristic of the SCT conditions.
ESA Sept. 2013
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Factors Affecting SCT Results
Effect of wire length
150
4" wires
120
12" wires
current, A
 Rc includes resistance of wires and
contacts.
 The length of wires affects inductance.
 Type of switch.
 The rate of voltage increase in
case of FET.
90
24" wires
47uF 20V
experiment
60
30
0
-30
0
10
20
Effect of resistance to FET gate on Vg and Isp for 47uF 20V capacitors
12
150
10
120
30
time, us
120
0 kOhm
90
110 nH
4
0 kOhm
1.6K Ohm
.8 k ohm
2
-15
0
15
30
45
time, us
60
75
60
30
0
0
90
400 nH
90
1.6 kOhm
current, A
current, A
gate voltage, V
6
50
150
0.8 kOhm
8
40
900 nH
60
47uF R=0.25Ohm
L-var. Simulation.
30
0
-30
-30
0
10
20
30
time, us
40
50
0
10
20
30
time, us
40
50
 SCT test conditions should be optimized by maximizing Isp.
ESA Sept. 2013
8
Effective Resistance of the Circuit
200
6V
10V
14V
18V
current, A
160
120
8V
12V
16V
20V
3SCT 220uF 6V
300
220uF 6V
80
0
0
15
30
45
60
75
90
time, us
200
240
220uF 6V
47uF 10V
160
120
80
20V
24V
28V
32V
0
20
40
voltage, V
60
80
100
after adjustment
poor contacts
0
36V
5
10
15
20
25
120
47uF 20V
80
35
-40
-10
0
10
20
30
40
50
60
70
Test anomalies, e.g. poor
contacts, can be
revealed by Isp(V) curves
time, us
 Isp increases linearly with voltage allowing for calculations of
the effective resistance of the circuit, Reff.
 Reff corresponds to the impedance of the circuit and includes
Rc, ESR, resistance of contacts, and circuit inductance, Lc.
ESA Sept. 2013
30
voltage, V
0
0
150
0
40
10uF 16V
40
good contacts
200
50
200
current, A
current spike, A
160
current spike, A
250
40
9
Effect of Reff on Breakdown Voltage
 Different lot date codes of 22 µF 35V capacitors.
TBJD226K035LRLB0024
TBJD226K035LRLB0024
0.24
90
0.22
80
VBR_SCT, V
ESR, Ohm
0.2
0.18
0.16
0.14
0.12
DC0513
DC0516
DC0824
DC0836
0.08
0.22
0.24
0.26 0.28
Reff, Ohm
0.3
0.32
0.2
0.3
40
0.2
20
0.1
0
0
-60
-40
-20
0
20
40
60
80
100
Reff, Ohm
VBR_SCT, V
0.4
47uF 20V VBR
220uF 6V VBR
47uF 20V Reff
220uF 6V Reff
60
50
DC0513
DC0516
DC0824
DC0836
30
0.34
 Effect of temperature
80
60
40
0.1
0.2
70
0.22
0.24
0.26 0.28
Reff, Ohm
0.3
0.32
0.34
 Parts with larger ESR had
greater VBR.
 Temperature decreases ESR
resulting in lower VBR.
 An increase in Reff by ~0.1Ω
results in increase of VBR ~10%.
temperature, deg.C
ESA Sept. 2013
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Correlation between ESR and Reff
47uF 10V uchips
Effective resistancde during SCT and ESR
99
ESR\TM8A106K016CBZ
Normal-2P
RRX SRMMEDFM
F=16/S=0
Data Points
Probability Line
0.4
0.35
y = 0.6118x + 0.1963
ESR\TM8T476K010CBZ
Normal-2P
RRX SRMMEDFM
F=16/S=0
cumulative probability, %
Reff, Ohm
0.45
Data Points
Probability Line
Reff\TM8A106K016CBZ
Normal-2P
RRX SRMMEDFM
F=16/S=0
50
0.3
0.2
0.25
0.3
ESR, Ohm
0.35
0.4
Data Points
Probability Line
Reff\TM8T476K010CBZ
Normal-2P
RRX SRMMEDFM
F=15/S=0
Data Points
Probability Line
10
20 lots of HV capacitors
1
0.10
0.8
0.24
0.38
0.52
0.66
0.80
R, Ohm
0.7
Reff, Ohm
5
0.6
0.5
0.4
0.3
0.2
0
0.1
0.2
0.3
0.4
ESR, Ohm
ESA Sept. 2013
0.5
0.6
0.7
 Effective resistance of SCT:
V
Reff = R ≈ Rc + ESR
I sp
 Optimized set-up: Rc is in the range
from 0.1 Ω to 0.2 Ω.
11
Application vs. Test Conditions
 Typical application conditions:
Example:
• A 15µF 10V CWR06
 No limiting resistors, minimal inductance.
capacitor with specified
 No contact resistance.
ESR=2.5Ω and real ESR =
 Resistance of the circuit, Rac, is minimal. 0.5Ω is used in a 5V line.
 The current is limited mostly by ESR.
 Surge Current Test conditions:




Contact resistance of fixtures.
Limiting resistor (up to 1 Ω).
Relatively long wires and inductance.
No requirements for Itest verification.
• During application the part
can experience a spike:
Iappl = 5/0.5 = 10 A.
• During the testing it will be
verified to the current:
Itest ≥ VR/(Rtc + ESRspec)
Itest =10/(1+2.5) = 2.8 A
 Parts with poor contacts in the fixture can pass the testing.
There might be a substantial difference in inrush currents
between application and test conditions.
ESA Sept. 2013
12
Real and Specified Values of ESR
99
10
LDC0513
cumulative probability, %
LDC0836
50
LDC0824
LDC0516
10
5
22uF 35V
ESRmax=0.4Ohm
ESR_spec/ESR_avr
CWR06-09
8
CWR11
CWR29
6
4
2
0
1
0.08
0
0.12
0.16
0.20
ESR, Ohm
0.24
0.28
2
4
6
8
10
12
14
16
18
ESR_spec, Ohm
 ESR distribution can be described by a normal function.
 The distributions are rather tight: STD ~ 30% to 50% of ESRavr.
 Different lots of the same part type might have different ESR.
 Only a maximum value of ESR is limited. Real ESR values
might not correlate with the limit.
CWR06
CWR11
CWR29
6.92
2.72
2.04
Navr
 Navr = ESRlimit/ESRavr
STD
2.64
0.83
1.02
 CWR06 have Navr ~7, CWR29 ~2. Lots QTY
14
20
23
ESA Sept. 2013
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Surge Current Derating
 SCT requirements (rated current):
I test =
Rtest = 1 Ω.
Rtest
VR
+ ESRspec
,
 During applications, possible current spike: I a = α × VR
derating α = Va /VR , Rac – additional resistance
Rac + ESR
,
 Derating Criterion: Ia < β×Itest , where β ≤ 1 is the current
derating coefficient.
 Substitution gives:
Rac >
α
α
× Rtest + × ESRspec − ESR
β
β
 At low voltages capacitors can tolerate much higher current
spikes, so there is no need in derating currents on the top of
voltage derating => Rac > α × Rtest + α × ESRspec − ESR
 Rac is not necessary if Ips_max < Itest at a clamping time τ ≤ 10 us.
ESR
 Unless SCT is done at the optimized conditions, or α <
ESRspec + Rtest
additional resistance is necessary.
ESA Sept. 2013
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When Additional Resistor is
Necessary?
 If SCT is carried out at the optimized conditions (Rtc< 0.5 Ω, and
Isp is verified at real ESR values), then
Rac > α × Rtc + (α − 1) × ESR
 If Rac < 0.05 Ω, no resistance required.
(1 − α ) × ESR > α × Rtc
ESA Sept. 2013
0.6
0.5
Rac, Ohm
 At the existing SCT requirements
per M55365, additional resistance
is necessary in most cases.
 If SCT is carried out at
Rtc = Reff – ESR < 0.5 Ω,
the additional resistor is not
necessary if
Required series resistance
at different ESR, Rtc and α
0.4
0.3
0.2
0.1
0
1.E-2
Rt=1.2, a=0.5
Rt=1, a=0.3
Rt=0.2, a=0.5
1.E-1
ESR, Ohm
Rt=1.2, a=0.3
Rt=0.5, a=0.5
Rt=0.2, a=0.3
1.E+0
Rt=1, a=0.5
Rt=0.5, a=0.3
15
Algorithm for Surge Current Derating
VR
, Rtc = 1 Ω
Rtc + ESRspec
2/ In case of using power supplies (PS)
with current compliance, make sure that
the clamping time τ ≤ 10us. IPS = Imax PS.
3/ Estimate ESR as ESRspec/N, where
N=7, 3, 2 for CWR06/11/29 respectively.
4/ Reff = VR/Isp, where Isp is the surge
current spike amplitude.
5/ SCT should be carried out at a min.
wire length, no limiting resistors, and Isp
should be verified to be greater than
Isp > VR/(0.5 + ESR)
1/ I test =
6/ Standard voltage derating: α = 0.5
7/ Actual derating: αd = Vapp/VR
8/ Suggestions for further actions:
- experimental data for ESR,
- calculate actual Rtc = Reff – ESR,
- SCT at greater voltage levels, …
ESA Sept. 2013
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Conclusion
 Tantalum capacitors manufactured per MIL-PRF-55365
might fail because the surge current test conditions during
manufacturing are less stressful compared to application
conditions.
 Measurements of current spike amplitudes during SCT
allow for estimations of the effective resistance of the test
circuit, Reff, and should be used to assure that the parts are
properly stressed during the testing. Acceptable test
conditions can be determined as Reff ≤ 0.5 + ESR.
 An algorithm and procedures necessary for selection of
limiting resistors to derate surge currents or for making a
decision to use tantalum capacitors without additional
resistors are suggested.
ESA Sept. 2013
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