1/4
Semiconductor Business Group
Industrial Devices Company
Panasonic Corporation
Design Guide for PCB Layout [Low-side Step-down Chopper Circuit for Standby Power Supply]
[Chopper Circuit Example]
LINE
Separate the pattern
into front and back
stages of Cout.
[Layout Example]
CIN
Vout
ZD
Input
+
Cout
+
+
Dout
+
Dout
Output
CIN
DIN
Rb
DIN
DR
Lout
NTRL
S S
PC
RETURN
D
DR
Separate the pattern
into front and back
stages of CIN.
Cout
Lout
ZD
S S
D
IPD
IPD
D ：DRAIN
S ：SOURCE
BP：BYPASS
FB：FB
BP S S FB
CBP
PC
Rb
BP S S FB
CBP
PC
[Attentions for PCB Layout]
No.
Attentions
Object
1
Design the patterns of the loop in which switching current flows when IPD is ON (red dotted line), and the loop in which
switching current flows when IPD is OFF (blue dotted line), as short and wide as possible to reduce impedance.
These loops are called as "power loop" hereafter.
Noise reduction
2
Separate the pattern of the front stage of CIN from the power loop.
Noise reduction
3
Allocate the AC line connected to the input filter away from the power loop.
Noise reduction
Surge withstand
4
Do not connect components for control (CBP, PC) to the power loop.
(When using MIP384, the capacitor between FB and S pins is included.)
Stability for control
5
Separate the Source pattern of the power loop from the Source pattern of the control circuit block.
Stability for control
6
Allocate control circuit pins and connected patterns away from the power loop.
Stability for control
7
Allocate the ceramic capacitor between BP and S pins as close to each pin as possible.
(When using MIP384, the capacitor between FB and S is included.)
Stability for control
Surge withstand
8
Do not connect ZD for output voltage detection to the power loop.
Stability for control
9
Separate the power loop from the output voltage line (stable), the back stage of Cout.
Stability for Output line
10
Allocate the Input block away from the Output block. (Allocate as the Input block, the power loop, the Output block are in line.)
Noise reduction
11
Take measures to prevent the noise generated at relays or lamps in AC line from affecting IPD.
Surge withstand
Design Guide for PCB Layout [Low-side Step-down Chopper Circuit for Standby Power Supply]
No. 注意点
2/4
Semiconductor Business Group
Industrial Devices Company
Panasonic Corporation
説明
Design the pattern of the power loop as short and wide as
possible.
Because high-frequency large current, which may cause noise, flows in the power loop, design the pattern as
short as possible to minimize the area inside the loop.
2
Separate the pattern of the front stage of CIN from the
power loop.
To prevent the noise generated at the power loop from propagating to the front stage of CIN, separate the
pattern into front and back stages of CIN. To flow all current flowing in the power loop into the input capacitor
and prevent the heat generated at IPD from propagating to the input capacitor, narrow the patterns of the
positive/negative junction of the input capacitor. It is also intended to prevent the surge current generated at
AC line from propagating to IPD by passing the input capacitor.
3
Allocate the AC line connected to the input filter away from
the power loop.
It is intended to prevent the noise generated at the power loop from propagating to the AC line connected to
the input filter directly and optimize the effect of X-capacitor and line filter, etc. It is also intended to prevent
the surge current generated at AC line from propagating to IPD.
4
Do not connect components for control (CBP, PC) to the
power loop.
(When using MIP384, the capacitor between FB and S pins
is included.)
Because large voltage fluctuation or high-frequency current is generated at the power loop, do not connect
components for control to the power loop for stable operation.
5
Separate Source pattern of the power loop from Source
pattern for IPD control circuit block.
Because the Source of the power loop is unstable, allocate the Source pattern of the power loop in the circuit,
which is different from the IPD control circuit, and each Source pattern are connected to each Source pin of
IPD. Do not connect components for control to the power loop.
6
Allocate control circuit pins (BP, FB) and connected
patterns away from the power loop.
(Be careful to the FB pin particularly.)
The power loop may be noise source due to the large voltage fluctuation or high-frequency current flowing.
Allocate control pins away from the power loop to avoid the effect of noise. In particular, as the FB pin is the
most important and sensitive to noise of control pins, design the pattern connected to FB pin not to be
affected by the noise.
7
Allocate the ceramic capacitor between BP and S pins as
close to each pin as possible.
Allocate the ceramic capacitor between BP and S pins as close to each pin as possible and do not connect it
to the power loop. This capacitor may affect not only stable operation but also surge withstand capability.
8
Do not connect ZD for output voltage detection to the power
loop.
Because large voltage fluctuation or high-frequency current is generated at the power loop, connect the
circuit for feedback or output voltage detection to the pattern of back stage of Cout.
9
Separate the power loop from the pattern of the back stage
of Cout.
To prevent the noise generated at the power loop from propagating to the back stage of Cout, separate the
pattern into the front and back stages of Cout. To flow all current flowing in the power loop into the output
capacitor, narrow the patterns of the positive/negative junction of the output capacitor.
10
Allocate the Input block away from the Output block.
(Allocate as the Input block, the power loop block, and the
Output block in line.)
Allocate the Input block away from the Output block to prevent the noise generated at AC line or the power
loop from propagating to the Output block.
11
Take measures to prevent the noise generated at relays or
lamps in AC line from affecting the IPD.
Take measures to prevent the noise generated at relays or lamps in AC line from propagating to IPD.
(e.g., Allocate IPD peripheral circuits away from the noise source or the channel of noise propagation, or
connect capacitors to the noise source, etc.)
1
Check List of PCB Layout [Low-side Step-down Chopper Circuit for Standby Power Supply]
No.
3/4
Semiconductor Business Group
Industrial Devices Company
Panasonic Corporation
Check Items
1
The pattern of the power loop is as short and wide as possible.
2
The pattern of the front stage of the input capacitor CIN is separated from the power loop.
3
AC line connected to the input filter is allocated away from the power loop.
4
Components for control (the capacitor between BP and S pins, Opto-isolators) are not connected to the power loop.
5
The Source pattern of the power loop is separated from the Source pattern of the control circuit.
6
Control circuit pins and connected patterns are allocated away from the power loop.
7
The ceramic capacitors between BP and S pins and FB and S pins are allocated close to each pin.
8
Components for output voltage detection (ZD, shunt regulators) are not connected to the power loop, but to the pattern of
the back stage of Cout.
9
The power loop is separated from the Output voltage line (stable), the back stage of Cout.
10
The Input block is allocated away from the Output block. (The Input block, the power loop block, and Output block are
allocated in line.)
11
PCB layout is designed to prevent the noise generated at relays or lamps in AC line from affecting IPD.
Check
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