Design IP Brochure
Cadence IP Factory
Get on the Fast Track to SoC Design Innovation
Version 2.2
Cadence Design IP Overview
Integration-Focused for Reduced Risk
Cadence IP Factory provides integration-focused IP and IP
subsystems that are proven to reduce risk and accelerate the
development of leading-edge SoCs. Our interface IP for key
memory, storage, and interconnect standards—in addition to our
core building-block IP—help you design and integrate the highest
quality SoCs with optimal performance and power.
Integration of IP has traditionally been a challenge for SoC
designers. By building our IP from the ground up, and by focusing
on integration, we help you significantly reduce both integration
effort and risk. In addition, our ability to deliver fully integrated
controller, PHY, and firmware solutions at both the interface and
subsystem level further reduces your integration effort.
We Always Listen to You
Unique Customization Infrastructure
We always listen to our customers and want to meet their needs.
Prior to its realization, every SoC project is discussed with you and
examined in detail.
We can deliver IP configured to your specific SoC design
requirements, providing only those features and performance
levels needed for your particular application.
®
“...we respond quickly, and we listen
to the customer very closely. I spend
most of my time in front of customers.
I want to be their trusted partner, to
provide the best tools and solutions,
and to help them work through some
of the most challenging designs they
have.”
Lip-Bu Tan interviewed by Richard Goering on August 27, 2013
Standards-Driven Design IP Targeted to Your
Needs
Supporting advanced capabilities Cadence Design IP offers
superior performance and power-optimized solutions. Our
extensive support for new standards, such as TSMC 28HPC,
ensures power- and cost-efficient design. No matter if the
application is a high-performance datacenter or a power-sipping
mobile device, we provide you with IP which is targeted to your
specific needs.
Using our customization infrastructure eliminates the need to
compromise—you can specify the IP around your design rather
than building your design around the IP. Furthermore, each of
our customized IP solutions is fully verified and delivered with
complete documentation plus an integration and verification
environment that is perfectly matched to the IP.
Proven Partner You Can Count On
Cadence Design IP is silicon proven and has been extensively
validated. We offer comprehensive IP solutions that are in volume
production and have been successfully implemented in more than
400 applications. With 13 years of experience delivering winning
IP solutions, Cadence is a proven partner you can count on.
“You have to rely on partners, you
have to rely on experts, whether
that’s hardware/software codesign,
analog-mixed signal, analysis tools,
signoff, DFT.”
Martin Lund being interviewed at MemCon 2013 by ChipEstimate.
tv’s Sean O’Kane
“By delivering our interface, memory,
analog and systems/peripheral IP to
this 28HPC process, our customers
in the smartphone, tablet, and other
high-volume consumer markets can
take advantage of the 10 percent
smaller die size and 30 percent
power reduction benefits of this new
process.”
Martin Lund, September, 2014
2
Design IP Brochure Version 2.2
ip.cadence.com
Interface IP Solutions
We offer various complete, configurable, and production-proven interface protocols, such as Ethernet, MIPI®, PCI EXPRESS®, and USB. All
these solutions are designed with your SoC in mind, so that there is no need for you to design around our IP. Pre-verified solutions help
you save time and effort and allow you to focus on your own design priorities. Moreover, our highly configurable architecture provides
you with numerous customization options, including software and prototyping solutions.
PHY
IP
Protocols
Performance
TSMC
Controller PCS
65nm
LP
Ethernet
MAC
PCS
Converter
DSI
MIPI
CSI
DigRF
10M/100M*
•
•
10M/100M/1G
10M/100M/1G*
•
•
10/40G
10/40G
•
•
•
•
LPe
LPe
LP
28nm
HPL HPM HPC
16nm
LP
FF
•
•
•
40/100G
40/100G
10G
10/40G
•
•
•
•
10/40G
10/40G
•
•
•
•
40/100G
40/100G
•
•
•
•
XAUI/XAUI20
10/20G
•
•
•
•
QSGMII R1.2
5G
•
DSI TX
1.5Gbps/lane
•
†
†
†
†
†
†
CSI-2 RX
1.5Gbps/lane
•
†
†
†
†
†
†
CSI-2 TX
1.5Gbps/lane
•
†
†
†
†
†
†
DigRF v4, v1.10
3Gbps/lane
•
‡
‡
‡
‡
‡
‡
UniPro 1.6
3 or 6Gbps/lane
•
‡
‡
‡
‡
‡
‡
Device v1.1
Audio/Data
•
Manager v1.1
Audio/Data
•
Master
Audio
•
Gen 1
2.5Gbps
•
•
•
•
Gen 2
5Gbps
•
•
•
•
Gen 3
8Gbps
•
•
•
•
Gen 4
16Gbps
•
M-PCIe ECN, SL
HS-G2/HS-G3
•
•
•
•
M-PCIe ECN, ML
HS-G2/HS-G3
•
•
•
•
USB 2.0
480/12/1.5Mbps
•
•
•
USB 3.0
5Gbps and legacy
•
•
•
USB 1.1
12/1.5Mbps
•
•
•
•
•
USB 2.0
480/12Mbps
•
•
•
•
•
•
•
USB 3.0
5Gbps and legacy
•
•
•
OTG
USB 2.0
480/12/1.5Mbps
•
•
•
•
•
•
•
•
•
Hub
•
•
•
•
•
•
SM
UniProSM
SLIMbus®
SoundWire
PCI EXPRESS
10M/100M
55nm 40nm
PCIe®
M-PCIe™
Host
USB
Device
USB 2.0
480/12/1.5Mbps
•
HSIC Interface
USB 2.0 HSIC
480Mbps
•
SSIC Interface
USB 3.0 SSIC
5/2.5/1.25Gbps
•
Table 1:  Interface IP Solutions
ip.cadence.com
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
* Soft PHY available
† – D-PHY
‡ – M-PHY
Design IP Brochure Version 2.2
3
Denali Memory IP Solutions
We offer the broadest and most configurable portfolio of the industry’s widely used memory and storage protocols.
Our Denali® Memory IP gives you the added value of multi-standard DDR support by providing controller IP that supports DDR4, DDR3,
DDR3L, LPDDR2, and LPDDR3 as a single IP solution. In order to address a wide range of applications, our DDR PHY IP includes two
families of DDR solutions, High-Speed (HS) and Low-Power (LP). Delivery options include soft, firm, hard, and full custom IP.
We also offer advanced memory IP solutions created by the best experts in the field to provide you with the controller, PHY, and
verification IP you need for your design.
PHY
Protocols
Maximum
Speed
Controller
TSMC
Soft
40nm
LP
28nm
GF
ST
28nm
28nm
G
HPM
HPC
LP
FF
SLP
HPP
FDSOI
•
DDR
DDR400
•
•
DDR2
DDR800
•
•
DDR2/DDR
DDR800
•
•
DDR3*/DDR2
DDR800
•
•
DDR1333
•
•
•
•
•
•
•
•
•
DDR1600
•
•
•
•
•
•
•
•
•
DDR2133
•
•
•
•
•
•
DDR1600
•
•
•
•
•
•
DDR2400
•
•
•
•
•
•
DDR2667
•
•
•
•
DDR3200
•
DDR1600
•
•
•
•
•
•
DDR2400
•
•
•
•
•
•
DDR2667
•
•
•
•
DDR3*
DDR4
DDR4/DDR3*
•
•
•
•
•
DDR3200
•
LPDDR
DDR400
•
•
LPDDR2
DDR800
•
•
LPDDR2/LPDDR
DDR800
•
•
LPDDR2/DDR3*
DDR800
•
•
LPDDR2
DDR1066
•
•
•
•
•
•
DDR1333
•
•
•
•
•
•
DDR1600
•
•
•
DDR1333
•
•
•
DDR1600
•
•
•
DDR1333
•
•
•
DDR1600
•
•
•
DDR1333
•
•
•
DDR1600
•
•
•
DDR2400
•
•
DDR2667
•
•
DDR3200
•
•
DDR2400
•
•
DDR2667
•
•
DDR3200
•
200MHz
•
LPDDR2/DDR3*
LPDDR3
LPDDR3/LPDDR2
LPDDR3/LPDDR2/DDR3*
LPDDR4/LPDDR3
LPDDR4/LPDDR3/DDR4/
DDR3
Wide I/O
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Table 2:  Denali Memory IP Solutions
4
16nm
* DDR3 includes DDR3L support
Design IP Brochure Version 2.2
ip.cadence.com
Storage IP Solutions
Cadence storage IP solutions consist of two popular technologies, NAND Flash and SD/SDIO/eMMC. These memory technologies address
the needs of a broad range of market requirements.
The Cadence NAND Flash Controller IP supports all major NAND Flash manufacturers handling asynchronous devices and also meeting
standards such as ONFI 1, ONFI 2, ONFI 3, ONFI 3.2, Toggle 1, or Toggle 2. The Cadence NAND Flash PHY IP supports speeds up to
DDR800 for most process nodes, and is available as soft IP with a delay-locked loop (DLL) for your specific process and library.
The Cadence SD/SDIO/eMMC IP is compliant with the latest versions of Secure Digital and Embedded Multimedia Memory Card
standards, which makes our IP the perfect choice for both high-performance and low-power solutions.
SD/SDIO/
eMMC
NAND Flash
IP
Performance
Controller
NAND Flash Async, ONFI 3.2/2/1, Toggle 1/2 Controller
533MTps
•
NAND Flash ONFI 4/3/2/1, Toggle 1/2 DLL PHY
800MTps
NAND Flash ClearNAND Controller
200MTps
NAND Flash PHY for FPGA
200MTps
PHY
Soft
•
•
•
•
SD 4.0 Host
312MBps
•
•
Combo SD/SDIO-3.0/eMMC 4.41 Host
104MBps
•
•
Combo SD 4.0/eMMC5.0 Host
400MBps
•
•
Combo SD 3.0/eMMC 5.0 PHY
400MBps
Flash QSPI Controller
•
52MBps
•
Table 3:  Storage IP Solutions
High-Definition Display IP Solutions
The saying that a picture is worth a thousand words has never been as true as it is today. High-definition display has become an integral
part of any consumer device, with each product having specific display requirements, as well as needing to support industry-standard
interfaces and protocols.
Recognizing this fact, the newest addition to our IP portfolio includes solutions for HDMI®, DisplayPort™, MHL™, MyDP™, DP++™,
and eDP™. Our High-Definition Display IP supports the latest standard features such as 4Kx2K resolution, multiple streams, 3D video,
enhanced audio, content protection, and mobility.
PHY
Controller/Solution
IP
MHDP TX
MHDP RX
HDCP
PHY
MHDP TX
MHDP RX
Protocols
TSMC
Performance
65nm
LP
GP
•
•
HDMI1.4
3Gb per lane
MHL 2.1
3Gbps
HDMI1.4
3Gb per lane
MHL 2.1
3Gbps
DP1.2
HBR , SST
•
•
6Gbps per stream
•
•
HDCP 1.4
HDCP 2.2
MHDP TX
6Gbps per lane
HDP TX
3Gbps per lane
MHL TX
3Gbps per lane
MHDP RX
3Gbps per lane
HDP RX
3Gbps per lane
SMIC
40nm
LP
28nm
HPM
65nm
HPC
LL
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Table 4:  High-Definition Display IP Solutions
ip.cadence.com
Design IP Brochure Version 2.2
5
Analog IP Solutions
As an established industry leader in analog design tools, we offer some of the world’s fastest and lowest power analog IP solutions.
TSMC
IP
65nm
AFE
LP
General AFE
•
Wi-Fi AFE
•
LTE AFE
•
G
40nm
LP
G
HPL HPM HPC
•
Power/
Timing
Monitor
ADC and DAC
LTE/Advanced LTE AFE
•
Medium-speed ADC (20 to 250MSps)
•
Low-speed ADC (<10MSps)
•
High-speed DAC (250MHz to 3.52GHz)
•
Medium-speed DAC (20 to 250MHz)
•
•
•
•
•
•
•
•
•
•
•
•
•
16nm
LP
•
•
•
•
•
•
Low-speed DAC (<10MHz)
•
•
•
12b 160M ADC
•
•
12b 320M ADC
•
•
7b 3.52G WiGiG ADC
•
•
•
•
•
•
•
•
•
•
LDO
•
•
POR
•
•
•
PLL/DLL
•
•
•
•
Voltage Monitoring IP
•
QSGMII/XAUI/Double XAUI
•
•
•
PCIe3/2/1 PHY
•
•
•
PCIe3/2/1 + SRIS + L1 sub-states PHY
•
•
•
•
•
protocol
16G Mutli-
•
protocol
•
PCIe4, USB3.1, HMC-15G-SR
PCIe2/3, USB3
protocol
•
10GKR, PCIe3, XAUI, CEI-6G
•
•
10GKR, PCIe3, XAUI, CEI-6G
•
PCIe2, SATA 3.1,USB3.0, MIPI M-PHY
•
•
DisplayPort TX 1.2a, SGMII
•
HK
•
LP
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
10G-KR PHY
•
•
10G EPON/GPON PMA
•
•
•
SATA 3.1 PHY
•
USB 1.1 PHY (USB 2.0 Full Speed)
•
•
USB 2.0 PHY
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
USB 3.0 PHY
•
•
USB 2.0 HSIC PHY
•
M-PHY (HS-G3)
D-PHY
•
SLP
•
PCIe2/3, USB3
M-PHY (HS-G2)
•
LP
•
•
•
USB 3.0 SSIC ( M-PHY)
LPe
•
•
12b 80M ADC
Temp Monitoring IP
LPe
•
Audio
6G Mutli- 10G Multi-
High-Speed SerDes
G
•
12.5G Chip-to-Chip PHY
USB
LP
SMIC UMC
55nm 40nm 28nm 28nm 40nm
•
PCIe4 + SRIS + L1 sub-states PHY
MIPI
FF
65nm
•
TriBand (802.11n/ac/ad) AFE
High-speed ADC (250MSps to 3.52GSps)
GF
28nm
•
•
•
•
•
•
•
•
•
•
•
Table 5:  Analog IP Solutions
6
Design IP Brochure Version 2.2
ip.cadence.com
Systems and Peripherals IP Solutions
Peripheral building blocks and efficient microprocessors have become an essential part of almost every SoC design. We offer peripheral,
8051 processor, and legacy processor IP. Our Systems and Peripherals IP solutions are architected to quickly and easily integrate into your
design, with configurability and compatibility being important features. All of our peripheral IP is compatible with the ARM® AMBA®
Specification, Revision 2.0.
Compatibility
Timer
Peripheral
Bus
Serial Interfaces
Audio Connectivity
IP
PWM
Pulse Width Modulator
AMBA Rev. 2.0
WDT
Watchdog Timer
AMBA Rev. 2.0
RTC
Real-Time Clock
AMBA Rev. 2.0
TTC
Triple Timer Counter
AMBA Rev. 2.0
AHBC
AMBA Rev. 2.0
AHB2APB Bridge
AMBA Rev. 2.0
APIC
Advanced Peripheral Interrupt Controller
AMBA Rev. 2.0
SMC
Static Memory Controller
AMBA Rev. 2.0
GPIO
General Purpose I/O, provides up to 32 programmable ports
AMBA Rev 2.0, I2C bus specification
version 2.0 (100kHz and 400kHz)
I2C
Inter-Integrated Circuit Bus, functions as a master or slave in
a multi-master, two-wire serial I2C bus
AMBA Rev 2.0, I2C bus specification
version 2.0 (100kHz and 400kHz)
I2C HS
AMBA Rev. 2.0
SPI
AMBA Rev. 2.0
UART
AMBA Rev. 2.0, Philips Inter-IC Sound Bus
Specification (1986, revised in 1996)
8051 Processor
AMBA Rev. 2.0
R8051XC2
Legacy Processor
Arbiter for ARM AMBA AHB interface
ARM AMBA AHB to APB Bridge IP
Inter-Integrated Circuit Bus, High-Speed version
Serial Peripheral Interface Bus
Universal Async Receiver Transmitter
Configurable single- or multi-channel Inter-IC Sound (I2S)
bus interface controller
Unidirectional and self-clocking interface for connecting
digital audio equipment
Intel 8051-compatible µC, fully configurable
Compatible with Intel MCS 51 instruction
set
T8051
Compatible with Intel MCS 251 instruction
set
80251XC
Intel 80251-compatible µC, over 12 times faster than the
80C51 from Intel
C68000
MC68000-compatible microprocessor
Compatible with M68000 instruction set
Fully compatible with TMS320C25
Obsolete Parts
Replacement
I2S
S/PDIF
Compatible with Intel® MCS® 51
instruction set
8051
Microcontroller
Description
AMBA Rev. 2.0
TMS320C25
Compatible with Intel 80C86 or 80C186
instruction set
C80186
Compatible with i387SX instruction set
C387L
Tiny 8051-compatible µC, very small gate count
TI TMS320C25-compatible Digital Signal Processor
Series of high-performance, 16-bit microcontrollers
compatible with Intel 80C186EC, Intel 80C186XL, Intel
80C186EA, with extended versions of peripherals
Intel i387SX-compatible 80-bit math co-processor
Compatible with Z80 instruction set
Z80
Zilog Z80-compatible microprocessor
Improved Zilog Z80-compatible CPU
S80
Zilog Z80-compatible microprocessor, speed improved
®
Table 6:  Systems and Peripherals IP Solutions
ip.cadence.com
Design IP Brochure Version 2.2
7
Cadence Design Systems enables global electronic design innovation and plays an essential role in the
creation of today’s electronics. Customers use Cadence software, hardware, IP, and expertise to design
and verify today’s mobile, cloud, and connectivity applications. www.cadence.com
© 2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence, and Denali are registered trademarks of Cadence
Design Systems, Inc. AMBA and ARM are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights
reserved. MIPI® is a registered mark of MIPI Alliance, Inc. The terms HDMI and HDMI High-Definition Multimedia Interface, and the HDMI Logo
are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other countries. MHL, Mobile High-Definition Link and
the MHL Logo are trademarks or registered trademarks of the MHL, LLC. PCI-SIG®, PCIe®, and PCI EXPRESS® are registered trademarks of PCISIG. JEDEC® and the JEDEC logo are registered trademarks of JEDEC Solid State Technology Association. Intel and MCS are trademarks of Intel
Corporation in the U.S. and/or other countries. ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All others
are the property of their respective holders.
Cadence IP Factory Version 2.2