Homework 9 Solutions and Rubric
EE 140/240A
1. Circuit Design Decisions
a. bandgap reference driving a 5k load
There are two constraints for this circuit: high gain, and low output impedance.
Of the topologies that we know about, the two stage amplifier with compensation for stability is the best option. The input common mode should be
somewhere around 0.6V. This means that either an NMOS or PMOS input is
fine. The output should be 1.2V with a 1.6V supply, so output swing is not a
problem.
b. digital voltage regulator
The amplifier in the digital regulator is up for debate. The regulation requirements of the circuit will determine the amount of loop gain (and therefore
forward gain) needed in the circuit. Typically, the gain needed in a PMOS
low-dropout regulator is modest. So, to reduce power consumption and improve stability, a single-stage active load amplifier is recommended. However,
any choice here is acceptable. The input common mode will be 1V with a 1.6V
supply, so NMOS is recommended although PMOS with low overdrive could
work.
c. analog voltage regulator
See digital voltage regulator explanation. If you would like to read more
about voltage regulator amplifier design, take a look at chapter 4 of Prof.
Alon’s PhD thesis. It goes into some details that are beyond the scope of
this class, but the discussion regarding loop gain should be discernible. The
input common mode will be 1.2V with a 1.6V supply, so only NMOS will work.
d. ADC comparator with 1.25V input and 1.25V supply
Because of the input common mode voltage at the top rail, it is necessary
to use an NMOS input folded cascode.
e. VGA with 0V input and 1.25V supply
Because of the input common mode voltage at the bottom rail, it is necessary
to use a PMOS input folded cascode. In addition, because the output of the
amplifier needs to swing to the bottom rail, the amplifier will need a second
stage and some careful thinking.
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2. Voltage Regulator
a. f = 1
b. The output voltage is changed by changing the potentiometer P1 and
therefore the voltage divider at the positive input of the amplifier.
c. The output will change by approximately 10% assuming that the forward
gain of the amplifier is high.
d. Call the voltage at the positive input of the amplifier v + . The feedback
will cause the negative terminal to be equal (approximately). That means that
+
a current of v /100 mA will flow through T2 and T3. β times less current will
flow through T1.
e. Let’s take a look at the loop gain. Apply a perturbation vx at the base
of T1. This will induce a voltage at the emitter of T1:
ve1 =
1
vx
1 + sC1 /gm1
To derive this expression, it was assumed that the impedance looking into
the bases of T2 and T3 were very large. Now we continue to the emitter of T2
and T3:
ve2,3 =
1
1
vx
(1 + sC/2gm2,3 ) (1 + sC1 /gm1 )
For this expression, it was assumed that gm2,3 R 1. Then, we know that
vx is simply −Ave2,3 , so the total loop gain is approximately:
T =A
1
1
(1 + sC/2gm2,3 ) (1 + sC1 /gm1 )
The pole contributed by the RC at the load is at ωp,load = gm2,3 /C1 , and the
pole contributed by the capacitor at the emitter of T1 is ωp,T 1 = gm1 /C2 . Recall
that the current through T1 is lower, so that pole will be a lower frequency.
f. Suppose that the output voltage is 1V. That means that the gm of T2
and T3 is 192µS. The gm of T1 is a further β times lower than each of these.
If we assume β = 100, the gm of T1 is 1.92µS. The pole at the emitter of T1
will be at a frequency of approximately 3 Hz. By this interpretation, the circuit
(without load) is unstable.
g. Stable could be interpreted two ways. If you wanted a reference that
effectively blocked changes in battery voltage (unlike this one), you could build
a bandgap reference and use that as the voltage at the positive terminal. If
you wanted the loop to have higher phase margin, you could use an amplifier
with a significantly gain. In reality, it is necessary to have a very large load
current. The current through T1 needs to be much higher to make the pole
at the emitter of T1 dominant and stabilize the system. Using 100nF at the
emitter of T1 was a poor choice.
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3. VGA
a. Ratios of 1, 2, and 4 are needed to obtain every integer gain between 1
and 8.
b. Gain error is 1/Af . The worst gain error will then occur when f = 1/8.
c. If we assume that the only source of error is gain error, then 1/Af = 0.004.
Therefore, A = 2000.
d. Now suppose that the only source of error is settling, or RC error. In that
case, we need to have 6 or 7 settling time constants within 10µs. Let’s just call
it 1µs. That would require an open-loop corner frequency of 1Mrad/s. From c,
we know that the gain must be 2000, so ωu ≈ 2GRad/s.
4. SAR ADC
a. The comparator compares at ground.
b. No. Notice that if the input voltage is greater than VDDA /2, the voltage
at the positive terminal of the comparator will be less than 0V (and therefore
outside of the rails) during the very first comparison. There is also the hold
phase where the voltage will always go below the bottom rail, but no comparison
is done.
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