EMP 33(2) #18936
Electric Power Components and Systems, 33:159–169, 2005
c Taylor & Francis Inc.
Copyright ISSN: 1532-5008 print/1532-5016 online
DOI: 10.1080/15325000590462756
A New Parallel Resonant DC Link for
Soft Switching Inverters
HULYA OBDAN
HACI BODUR
ISMAIL AKSOY
NUR BEKIROGLU
GULDEREN YILDIRMAZ
Yildiz Technical University
Besiktas, Istanbul, Turkey
In this article, a new parallel resonant DC link (PRDCL) that provides soft
switching (SS) and pulse width modulated (PWM) operation for inverters is
presented. The new PRDCL ensures zero crossings for a time period, and at
any time required for SS and PWM operation of the inverters, respectively.
Moreover, the proposed PRDCL is realized by using only one auxiliary active
switch, has a simple structure and ease of control, and operates under SS
conditions. All switches in the soft switching inverters (SSI) equipped with
the new PRDCL operate with soft switching, and are subjected to no additional
voltage and current stresses. A detailed steady-state analysis of the proposed
PRDCL is presented, and this theoretical analysis is verified by a prototype of
a 250 V, 50 kHz and 1250 W circuit.
Keywords parallel resonant DC link, PWM inverter, soft switching, soft
switching inverter
1. Introduction
Due to its high power density, fast transient response and ease of control, pulse width
modulated (PWM) technique is widely used in the industry. It is well known that
in order to obtain higher power density and faster transient response, switching frequency should be increased, but in that case electro-magnetic interference (EMI) and
radio-frequency interference (RFI) noises and switching losses in semiconductor devices increase as well. In order to decrease these noises and losses, soft switching (SS)
techniques should be used instead of hard switching (HS) techniques. SS techniques
are formed by the circuits called snubber cells, and basically provide zero voltage
switching (ZVS) and/or zero current switching (ZCS) for semiconductor devices. This
SS concept has been very popular for the last 20 years and continues to be so [1–15].
Resonant techniques are used generally to provide soft switching in soft switching inverters (SSI). In fact, this is not a new idea because resonant circuits had been
used to achieve the forced commutation of thyristors for many years. SS inverters
Manuscript received in final form on 11 December 2003.
Address correspondence to Dr. Hulya Obdan, Yildiz Technical University, Department
of Electrical Engineering, 34349, Besiktas, Istanbul, Turkey. E-mail: obdan@yildiz.edu.tr
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are divided into two broad categories, namely, pole commutated and resonant DC
link inverters (PCI and RDCLI). While PCI basically has one resonant tank per
pole or leg and a capability of PWM operation, RDCLI has one common tank on DC
link but not the PWM operation capability. Moreover, PCI has more components
and a higher cost than its RDCLI counterpart [12, 13].
A lot of research on RDCLI having the cheapest solution for SS has been
presented in recent years. RDCL inverters are divided into two major groups,
namely, basic resonant and parallel resonant DC link inverters (BRDCLI and
PRDCLI). The inverter is connected to the voltage source via an inductor, there
is not the PWM operation capability, and the inverter voltage stress is very high
in the BRDCLI basically. To restrict the voltage stress, the active and passive
clamped (AC and PC) BRDCL inverters have been improved. Also, the quasi
resonant (QR) subgroups of these inverters have been presented to provide the
PWM operation capability for these inverters, which can generally operate with
discrete pulse modulation (DPM) [1–3, 6, 8–10].
In the PRDCLI, the inverter is connected to the DC source by a switch, a PWM
operation capability is existent, and the inverter voltage is minimum. All PRDCL
inverters can be described as active clamped and quasi resonant. The studies on
the soft switching inverters have been concentrated on the area of the PRDCLI in
recent years. More PWM operation capability, more output performance, higher
switching frequency and lower cost than the studies presented previously are aimed
in these studies [4, 5, 7, 11]. Three switches in [4], a switch and a voltage source in
[5], a switch and a resonance interval in [7], and a switch and a magnetic coupled
inductor in [11] are used basically and additionally.
In this study, a new PRDCL circuit for SS inverters is presented. It ensures
that DC link voltage falls to zero at any time required and stays at zero for a time
period needed. Thus, it provides SS and PWM operation for the inverters. Also,
the new PRDCL operates under SS, is implemented by using only one auxiliary
active switch, and so has a simple structure and ease of control. The proposed new
PRDCL is analyzed in detail, and this analysis is entirely verified by a prototype
of a 250 V, 50 kHz and 1250 W circuit.
2. Operation Modes and Analysis
2.1. Definitions and Assumptions
The scheme of the proposed new PRDCL circuit is given in Figure 1. The circuit
basically consists of a main switch, an auxiliary circuit, and an equivalent inverter
circuit. The main switch (S1 ) consists of a main transistor (T1 ) and its body diode
(D1 ). The auxiliary circuit consists of an auxiliary transistor (T2 ), an auxiliary
diode (D2 ), a center tapped and magnetic coupled resonant inductor (2Lr ), and
a resonant capacitor (Cr ). DF , Tinv , and Io are the equivalent elements of the
inverter feeding an AC motor as a load. The auxiliary transistor T2 has a lower
power rating and is faster than the main transistor T1 . In order to simplify the
steady state analysis for one switching cycle of the circuit given in Figure 1, the
following assumptions are made:
1. Input voltage Vi and output current Io are constant.
2. Resonant circuits are ideal.
3. Voltage drops and parasitic capacitors of semiconductor devices are ignored.
Resonant Link for Soft Switching Inverters
161
Figure 1. New PRDCL circuit.
2.2. Operation Modes of the Circuit
Within one switching cycle in the steady-state operation of the proposed circuit,
7 modes occur. The equivalent circuit diagrams of the operation modes are given
in Figure 2, and Figure 3 represents key waveforms.
Mode 1 [t0 < t < t1 : Figure 2a]. At the beginning of this mode, the equations
ii = Io , IT 1 = Io , iT 2 = 0, iDF = 0, iLr = 0, and vCr = Vi are valid. At t = t0 , as
the main transistor T1 is in the on state and conducts the output current Io , the
turn on signal is applied to the gate of the auxiliary transistor T2 and this mode
starts. For this mode, the following equations can be written as
iLr = iT 2 =
Vi
(t − t0 )
Lr
iT 1 = Io + iLr
(1)
(2)
When the current of the left half of the resonant inductor reaches a desired “threshold current” value at the instant t = t1 , this mode is terminated by removing the
turn on signal of T1 . Hence, the following equations hold for this state:
ILr1 = iLr (t1 )
(3)
Lr
ILr1
Vi
(4)
t01 =
The energy stored in the inductor during this mode must compensate for the
resonant losses in consecutive intervals, and ensure the DC link voltage to fall
to zero and then to rise again to source voltage Vi . Also, the auxiliary transistor T2
is turned on under zero current switching (ZCS) because of Lr in this mode.
Mode 2 [t1 < t < t2 : Figure 2b]. Prior to this step, the main transistor T1 conducts
the current I0 + Ilr1 and auxiliary transistor T2 conducts the current Ilr1 . Just after
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Figure 2. Equivalent circuit schemes of the operation modes in the presented PRDCL.
T1 is turned off at the instant t = t1 , the equations ii = 0, iT 1 = 0, iT 2 = Ilr1 ,
iDF = 0, iLr = Ilr1 , and vCr = Vi are valid at the beginning of this stage.
At t = t1 , as transistor T1 is turned off, a parallel resonance between the left
half of the resonant inductor and the resonant capacitor starts via Lr -T2 -Cr under
the output current Io . For this resonance
iLr = iT 2 = (ILr1 + Io ) cos(ω(t − t1 )) +
Vi
sin(ω(t − t1 )) − Io
Z
vCr = Vi cos(ω(t − t1 )) − Z(ILr1 + Io ) sin(ω(t − t1 ))
(5)
(6)
Resonant Link for Soft Switching Inverters
163
Figure 3. Key waveforms concerning the operation modes in the presented PRDCL.
are obtained. In these equations
1
Lr Cr
Lr
Z=
Cr
ω=√
are valid.
(7)
(8)
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At t = t2 , this mode terminates as the voltage of the DC link or the capacitor
Cr falls to zero. The current and the energy of the inductor reach their maximum
values at the same time. For this state
(9)
iLr (t2 ) = ILr2 = ILr max = (ILr1 + Io )2 + (Vi /Z)2 − Io
WLr (t2 ) = WLr2 = WLr max =
t12 =
1
2
Lr ILr
max
2
Vi
1
arctg
ω
Z(ILr1 + Io )
(10)
(11)
can be written.
The DC link voltage drops softly from Vi to zero because of the resonance, and
so the main transistor T1 is turned off under zero voltage switching (ZVS) in this
mode.
Mode 3 [t2 < t < t3 : Figure 2c]. Just after the DC link voltage drops to zero,
the diode DF that symbolizes the reverse recovery diodes of the inverter starts
conducting and this mode begins at t2 . At the beginning of this mode, the following
equations hold: ii = 0, iT 1 = 0, iT 2 = Ilr max , iDF = Ilr max + I0 , iLr = Ilr max ,
and vCr = 0. This mode continues until the turn on signal of the transistor T2 is
removed from its gate at t3 . For this mode
iLr = iT 2 = ILr max
(12)
vCr = 0
(13)
t23 = tZVOL
(14)
can be written. The duration of this mode can be chosen freely and the DC link
voltage remains zero during the mode. Therefore, all inverter switches can be easily
switched under ZVS in this stage.
Mode 4 [t3 < t < t4 : Figure 2d]. Just after the auxiliary transistor T2 is turned off,
the diode DF is turned off and the diode D2 is turned on simultaneously at t3 . The
following equations hold in the beginning of this mode: ii = 0, iT 1 = 0, iT 2 = 0,
iDF = 0, iLr = Ilr max , and vCr = 0. A parallel resonance between the right half
of the resonant inductor and the resonant capacitor starts via the resonant path
Cr -D2 -Lr under the constant current Io at the same time. For this resonance
iLr = iD2 = (ILr max − Io ) cos(ω(t − t3 )) + Io
(15)
vCr = Z(ILr max − Io ) sin(ω(t − t3 ))
(16)
are obtained. When Cr voltage or DC link voltage reaches the source voltage Vi at
t4 , the diode D1 is turned on and this stage stops. The following equations hold for
this state:
iLr (t4 ) = ILr4 > Io
t34 =
Vi
1
arcsin
ω
Z(ILr max − Io )
(17)
(18)
Therefore, the auxiliary transistor T2 is turned off with ZVS as the DC link voltage
increases softly from zero to the source voltage Vi due to the resonance in this mode.
Resonant Link for Soft Switching Inverters
165
Mode 5 [t4 < t < t5 : Figure 2e]. Just after the diode D1 is turned on at t4 , the
equations Ii = −(Ilr4 − Io ), iT 1 = 0, iT 2 = 0, iDF = 0, iLr = Ilr4 , and vCr = Vi are
existent at the beginning of this mode. For this mode
iLr = iD2 = −
Vi
(t − t4 ) + ILr4
Lr
(19)
is derived. D1 conducts the excess of the current iLr from Io during this stage.
When this current drops to Io , D1 is turned off and this mode stops. For this state
t45 =
Lr
(ILr4 − Io )
Vi
(20)
can be written. Therefore, a part of the energy stored in the inductor is transferred
to the voltage source and the load over this mode. The turn on signal should be
applied to the gate of the main transistor T1 during this mode, and so T1 is turned
on under ZVS at the end of this stage at t5 .
Mode 6 [t5 < t < t6 : Figure 2f ]. At the beginning of this mode, ii = 0, iT 1 = 0,
iT 2 = 0, iDF = 0, iLr = Io , and vCr = Vi are valid. When D1 is turned off and T1
is turned on simultaneously at t5 , this mode begins. For this mode
iLr = iD2 = −
Vi
(t − t5 ) + Io
Lr
(21)
is obtained. When the current iLr of the inductor drops to zero at t6 , this mode is
finished. Thus,
t56 =
Lr
Io
Vi
(22)
can be written. Therefore, the energy stored in the resonant inductor is transferred
to the load completely, and the diode D2 is turned off under ZCS at the end of this
stage.
Mode 7 [t6 < t < t7 = t0 : Figure 2g]. During this mode, the load is fed by the DC
voltage source via the main transistor T1 . For this mode
iT 1 = Io
(23)
t67 = tFEED
(24)
can be written. The duration of this mode is a large part of the switching cycle of
the PRDCL circuit.
Consequently, one switching cycle is completed and another cycle starts at the
moment a turn on signal is applied again to the gate of the auxiliary transistor T2
at t = t7 = t0 .
3. Circuit Features
The proposed new PRDCL circuit provides most of the desirable features of the similar circuits presented previously, and overcomes most drawbacks of these circuits.
The features of this new circuit can be summarized as follows.
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1. All semiconductor devices in the circuit are switched under soft switching.
The main switch is turned on and off with ZVS. The auxiliary switch is
turned on with ZCS and off with ZVS. The equivalent diode operates under
ZVS, and the auxiliary diode is turned on under ZVS and turned off under
ZCS.
2. The main switch of this circuit and also all switches of the inverter considered
to control are not subjected to any additional voltage stresses. Moreover, the
current stresses on the main and auxiliary devices of the circuit are very low.
3. The PRDCL circuit has a more simple structure and more ease of control
than most of the similar circuits presented previously. Because the circuit
is realized by using only one auxiliary switch, an auxiliary diode, and a
resonant inductor and a resonant capacitor.
4. The new PRDCL ensures zero crossing on the DC link voltage at any time
and for a time period required for the PWM and SS operation of the inverter,
respectively.
5. The circulating energy is quite small and it is slightly dependent on the load
current because the fall and the rise of the zero crossing are provided by
nearly a quarter resonance.
6. The auxiliary switch and diode devices are subjected to a voltage by nearly
twice the input voltage. It can be considered as a drawback of the new
circuit.
7. The leakage inductance of two sections of the resonant inductor should be as
small as possible to turn off the auxiliary devices with soft switching and to
protect them from additional voltage stresses. If can be implemented with a
good magneting coupling between two half windings of the inductor.
4. Experimental Results
To verify the theoretical analysis of the proposed new PRDCL circuit, a prototype
of a 1250 W and 50 kHz PRDCL, shown in Figure 4, was realized experimentally.
The oscillograms given in Figure 5 were obtained from the operating circuit with a
digital camera.
With reference to the handbooks of the manufacturers, the IGBT used as the
main switch S1 owns V = 500 V, I = 20 A, tr = 100 ns, and tf = 400 ns. The
Figure 4. Experimental circuit diagram for ACQPRDCL.
Resonant Link for Soft Switching Inverters
167
Figure 5. Some experimental oscillograms with 100 V/div. (a) The voltage and current
of S1 for HS, with 10 A/div and 1 µs/div; (b) The voltage and current of S1 for SS, with
20 A/div and 2 µs/div; (c) The voltage and current of T2 for SS, with 20 A/div and
2 µs/div; and (d) The voltage and current of DC link, with 10 A/div and 2 µs/div.
values of the IGBT used as the auxiliary transistor T2 are V = 600 V, I = 10 A,
tr = 50 ns, and tf = 200 ns. Also, the D2 and DF diodes own V = 600 V, I = 8 A,
trr = 60 ns.
The oscillograms given in Figure 5a are the voltage and current waveforms of
the main switch operating at hard switching conditions. From this figure, it can be
seen that the main switch is turned on and the main diode is turned of with hard
switching simultaneously, and also a short circuit by means of these main devices
occurs at the same time. Also, the main switch is turned off with hard switching
losses of very high values occur in this hard switching case.
From the voltage and current waveforms of the main switch S1 , given in
Figure 5b for the soft switching case, it can be seen that S1 is turned on and
off with ZVS through the inductor Lr and the capacitor Cr , and so the switching
losses of S1 are nearly zero.
From the voltage and current waveforms of the auxiliary transistor T2 , given
in Figure 5c for the soft switching, it is clearly seen that T2 is turned on under
ZCS by the inductor Lr and turned off under ZVS by the capacitor Cr , and so
the switching losses of T2 are nearly zero. Unfortunately, the transistor T2 and the
diode D2 are subjected to a voltage by about twice the input voltage Vi .
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The output voltage and current waveforms are shown in Figure 5d. The voltage
falls to zero from Vi , stays at zero for a time and rises again Vi . The fall and rise
periods of the output voltage are implemented by a resonance between Lr and Cr ,
and so the circuit can operate at relatively high frequencies without dependence on
the output current. Also, zero crossings are achieved for a time period required for
SS operation, and at any time needed for PWM operation of the inverters.
Additionally, because of the turn on delay time of the concerning diodes, small
spikes, collapses and slight ripples are shown on all waveforms in Figure 5 after the
turn on and off processes of the switches.
Consequently, to provide SS and PWM operation of the inverters, the proposed
new PRDCL circuit generates perfectly zero crossing on the DC link by using only
one auxiliary transistor. Also, it has seen that the efficiency of the proposed circuit
is increased to about 97% from value of 93% in its counterpart hard switching
version at 5 A of the output or inverter current. It should be now noted that this
proposed circuit will mainly provide soft switching and so many more advantages
than that given here for inverters.
5. Conclusion
In this study, a new PRDCL circuit is presented. This circuit provides zero crossings
on the DC link to implement the SS and PWM operation of the inverters. The new
circuit combines the most desirable features of the circuits presented previously and
overcomes most drawbacks of these circuits by using only one auxiliary transistor.
Subsequently, all semiconductor devices in the circuit operate under SS, the circuit
can successfully operate under various load conditions, and it has a simple structure,
low cost and ease of control. Consequently, new PRDCL circuit was analyzed in
detail. It was observed that the theoretical analysis of this circuit was exactly
verified by a prototype of a 1250 W and 50 kHz PRDCL circuit.
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