272
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010
Single-Phase to Single-Phase Full-Bridge Converter
Operating With Reduced AC Power in the
DC-Link Capacitor
Isaac Soares de Freitas, Member, IEEE, Cursino Brandão Jacobina, Senior Member, IEEE,
and Euzeli Cipriano dos Santos Jr., Member, IEEE
Abstract—This paper presents a control technique based on input and output ac power synchronization to reduce the low frequency ac power and the dc-link voltage fluctuation of a singlephase full-bridge converter. The control technique is based on a
technique in which the load voltage is synchronized with the input
grid voltage for both constant (Mode I) and variable (Mode II)
phase angle. Such approach allows for a reduction in the capacitor
size. A capacitor bank design approach is also proposed. The technique has been achieved for the same input and output converter
frequency. Simulated and experimental results are addressed.
Index Terms—AC–AC power conversion, ac–dc power conversion, pulsewidth modulated power converters.
I. INTRODUCTION
INGLE-PHASE ac–ac power converter with a dc-link capacitor can be obtained by using four legs (full-bridge converter), three legs (shared-leg converter) and two legs (halfbridge converter) [1]–[3]. The full-bridge topology is shown in
Fig. 1. A wide class of single-phase equipments can be built from
single-phase ac–ac dc-link converters. This is the case of line
voltage regulators, universal active power filters, standby power
supplies, and uninterruptible power supplies [1], [2], [4]–[9].
Single-phase ac–ac dc-link converters can also be found as part
of three-phase equipments [3]. This kind of converter provides
sinusoidal input current with unitary power factor, and it is effective to protect the load against line disturbances. Consequently,
it is recommended to furnish stable ac voltage to critical loads,
such as computers, telecommunication systems, and biomedical instrumentations. Most of these applications have same input
and output converter frequencies.
The reduction of the dc-link capacitor size and of the dc-link
voltage fluctuation is an important issue in the case of unidirectional power switch three-phase two-level converters [10]–[15]
and multilevel converters [16], [17]. Among these papers, it can
S
Manuscript received January 6, 2009; revised March 2, 2009 and May 16,
2009. Current version published February 12, 2010. This work was supported
by the National Council for Scientific and Technological Development, by the
Coordination for the Improvement of Higher Education Personnel, and by the
Foundation for Research Support of the State of Paraı́ba, Joao Pessoa, Brazil.
Recommended for publication by Associate Editor J. R. Espinoza.
I. S. de Freitas is with the Department of Electrical Engineering, Federal University of Paraiba, João Pessoa 58059-900, Brazil (e-mail: isaac@ct.ufpb.br).
C. B. Jacobina and E. C. dos Santos, Jr., are with the Department of Electrical
Engineering, Federal University of Campina Grande, Campina Grande 58109970, Brazil (e-mail: jacobina@dee.ufcg.edu.br; euzeli@dee.ufcg.edu.br).
Digital Object Identifier 10.1109/TPEL.2009.2031225
Fig. 1.
Single-phase to single-phase full-bridge dc-link converter.
be highlighted [12], in which the dc-link capacitor is practically
eliminated. In this case, the input grid current is not sinusoidal
and the dc-link voltage presents a noticeable fluctuation. The
dc-link capacitor can be also eliminated in bidirectional ac–ac
matrix or sparse matrix converter topologies, but in this case
several bidirectional power switches are required [18].
Unlike three-phase converters, single-phase ones have low
frequency ac power in the dc-link capacitor, which implies in
additional complexity. Therefore, large capacitors are required
to maintain the dc-link ripple inside an acceptable range. The
dc-link capacitor of a diode rectifier single-phase-based converter is reduced when the ac output voltage is synchronized
with the dc-link ripple voltage [19]. Input–output voltage synchronization technique has already been used in [20] to reduce the extra ac capacitor power of a half-bridge single-phase
converter.
This paper presents a synchronization technique between input and output ac powers, which permits to reduce the ac dc-link
power and, consequently, the dc-link capacitor size, of a singlephase full-bridge converter (Fig. 1). In such scheme, the outer
loop synchronization determines the input and output reference
converter voltages, which in turn, are the input of the pulse width
modulation strategy. That technique can be directly adapted and
employed for three-leg and two-leg ac–ac dc-link converters
to reduce the ac capacitor power. The technique is suitable for
applications in which the grid and the load operate at same frequency. In this case, it is required the control of the input grid
current and the load voltage to follow sinusoidal constant frequency reference signals with unitary input power factor and
constant amplitude, respectively. This requirement is found for
example in line voltage regulators, universal active power filters,
and uninterruptible power supplies.
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II. CONVERTER VOLTAGES
The full-bridge converter (shown in Fig. 1) is connected to the
grid by the filter reactance Xg . It comprises an eight switches
power converter and a dc-link composed of a capacitor bank.
The output converter side is connected to the single-phase load
by the filter impedance Zf . Switch pairs qg 1 − q g 1 , qg 2 − q g 2 ,
ql1 − q l1 , and ql2 − q l2 have complementary conduction states.
The conduction state of all switches can be represented by a
homonymous binary variable qg 1 , qg 2 , ql1 , and ql2 , where q = 1
indicates a closed switch while q = 0 indicates an open one.
The converter grid voltage vg and the converter load voltage
vl can be expressed as a function of the converter pole voltages
vg 10 , vg 20 , vl10 , and vl20 , that depend on the power devices
conduction states, that is
vg = vg 10 − vg 20 = (qg 1 − qg 2 ) vc
(1)
vl = vl10 − vl20 = (ql1 − ql2 ) vc
(2)
where, vc denotes the dc-link capacitor voltage.
III. PULSEWIDTH MODULATION (PWM) STRATEGY
Carrier-based PWM [21]–[23] can be used to generate the
gating signals for the system as shown in Fig. 1.
Considering that vg∗ and vl∗ are the desired reference voltages,
the reference pole voltages can be expressed as
vg∗10 = vg∗ + vg∗20
(3)
∗
∗
vl10
= vl∗ + vl20
.
(4)
Relations (3)–(4) can be reformulated as
∗
vg∗10 = vg∗ + vµg
(5)
∗
vg∗20 = vµg
(6)
∗
vl10
∗
vl20
=
vl∗
=
∗
vµl
.
+
∗
vµl
(7)
(8)
The problem to be solved is how to determine vg∗10 , vg∗20 ,
∗
and vl20
once the desired voltages vg∗ and vl∗ have been
∗
∗
specified. The voltages vµg
and vµl
can be calculated by taking
the apportioning factor µs into account, i.e.,
1
∗
∗
∗
(9)
vµs = vc µs −
− µs vsm
ax + (µs − 1) vsm in
2
(1 − µs ) tos ] of the switching period (T ). The apportioning factor can be changed as a function of the modulation index to
reduce the harmonic distortion (THD) of the converter voltages [24], [25].
Once the pole voltages have been defined, pulsewidths τg 1 ,
τg 2 , τl1 , and τl2 can be calculated by using [21]
T
T
+ vj∗0 for j = g1, g2, l1, or l2
(11)
2
E
where E = vc∗ is the reference dc-link voltage.
Alternatively, gating signals can be generated by comparing
∗
∗
, and vl20
with a high fremodulating signals vg∗10 , vg∗20 , vl10
quency triangular carrier signal.
τj =
IV. DC-LINK CAPACITOR POWER AND VOLTAGE
From Fig. 1 and neglecting the switching frequency effect, the system voltages and currents in
steady state are eg (t) = Eg cos(ωg t), vg (t) = Vg cos(ωg t −
θg ), ig (t) = Ig cos (ωg t + φg ), vl (t) = Vl cos(ωl t + ε), and
il (t) = Il cos(ωl t + ε + φl ), where Vg , Vl , Ig , and Il are the
grid and load converter voltages and currents amplitude, respectively; θg is the power angle, ε is a general load voltage
phase angle, and φg and φl are the input and output power factor angles, respectively. The input and output power are given by
pg (t) = vg (t) ig (t) and pl (t) = vl (t) il (t), respectively. Neglecting the converter power losses, the dc-link capacitor power
can be written as
Vg Ig
Vl Il
cos (θg + φg ) −
cos(φl )
pc (t) = pg (t) − pl (t) =
2
2
Vg Ig
cos (2ωg t − θg + φg )
+
2
Vl Il
cos (2ωl t + 2ε + φl ) .
−
(12)
2
Assuming no capacitor losses, the average value of pc in
steady state must be zero. This means that the input and output
active power are the same. Hence, the first term in brackets must
be zero. Then
∗
vl10
,
∗
∗
where vsm
ax = max (ϑs ) and vsm in = min (ϑs ), and ϑs =
{vs∗ , 0}, for s = g or l. Equation (9) was derived by using the
same approach as used to obtain the equivalent one for the
three-phase PWM modulator [24], [25].
The apportioning factor µs (0 ≤ µs ≤ 1) is given by
µs =
tois
tos
(10)
and indicates the distribution of the free-wheeling period tos
(period in which voltages vs10 and vs20 are equal, for s = g
or l) between the beginning (tois = µs tos ) and the end [tof s =
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273
Vg Ig cos (θg + φg ) = Vl Il cos(φl ).
(13)
and, therefore,
pc (t) = Nl
cos φl
cos (2ωg t − θg + φg )
cos (θg + φg )
− Nl cos (2ωl t + 2ε + φl )
(14)
where Nl = 1/2Vl Il is the load apparent power.
From (14), the capacitor voltage can be achieved by solving
pc = vc ic = Cvc
dvc
,
dt
(15)
i.e.,
cos φl
Nl
dvc
vc
=
cos (2ωg t − θg + φg )
dt
C cos (θg + φg )
(16)
− cos (2ωl t + 2ε + φl )
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010
cos φl
cos (2ωg t − θg + φg )
cos (θg + φg )
− cos (2ωl t + 2ε + φl ) dt + ϑo (17)
Nl
vc dvc =
C
vc2
cos φl
Xcg sin (2ωg t − θg + φg )
= Nl
cos (θg + φg )
(18)
− Xcl sin (2ωl t + 2ε + φl ) + ϑo
where Xcg = ω g1C , Xcl = ω l1C and ϑo is a dc value.
Therefore, the capacitor voltage can be written as follows:
vc = ϑ o + ∆
(19)
where
∆ = Nl Xcl
cos φl
fl
sin (2ωg t − θg + φg )
cos (θg + φg ) fg
− sin (2ωl t + 2ε + φl )
(20)
vcm in
Nl Xcl
≃E−
2E
fl
cos φl
+1 .
fg cos (θg + φg )
(24)
Therefore,
∆vcm ax ≃
Nl Xcl
E
fl
cos φl
+1 .
fg cos (θg + φg )
(25)
From (25), it can be seen that the increase of the capacitance
size reduces the peak-to-peak voltage.
For same grid and load frequencies (ωg = ωl = ω) and unitary input power factor (cos φg = 1), (22) can be written as
follows:
Nl X c
kε cos (2ωt + β)
vc (t) ≃ E +
(26)
2E
where
kε = kφ2 − 2kφ cos (θg + 2ε + φl ) + 1
1
cos φl
and
, Xc =
cos θg
ωC
cos φl − cos (2ε + φl )
β = arctan
.
cos φl tan θg + sin (2ε + φl )
kφ =
and fl and fg are the load and grid frequencies, respectively.
√
Consequently, for same input and output frequencies, the ac
By expanding (19) in Taylor series around vc = ϑo = E
(once the dc-link voltage is well known as being composed of voltage can be reduced by increasing the capacitor C, or through
a dc value overlapped by a small ac component) the dc-link reducing kε by proper choosing the value of phase angle displacement ε.
voltage can be expressed as follows:
The maximum and minimum values of vc (t) are given by


∞
n
n+1
n
∆
∆2
(−1)
∆
Nl X c

−
+
(2j −3).
vc = E +
kε
(27)
vcm ax ≃ E +
2E
8E 3 n = 3
n!
2n E 2n −1 j = 2
2E
(21)
The power series in (21) shows that the capacitor voltage is
composed of a dc component and an ac component with infinite number of frequencies. However, for practical values of
the capacitor size and the dc-link reference voltage, the capacitor voltage is well represented by the first two terms in (21)
(i.e., E + ∆/2E). This approximation results in the following
expression:
cos φl
Nl Xcl fl
sin (2ωg t − θg + φg )
vc ≃ E +
2E fg cos (θg + φg )
(22)
− sin (2ωl t + 2ε + φl ) .
Therefore, the value of the ac capacitor voltage frequency is
near twice that of the input and output frequencies.
In order to analyze voltage fluctuation, let us define
the maximum (peak-to-peak) capacitor voltage as ∆vcm ax =
vcm ax − vcm in , where vcm ax and vcm in are the maximum
and minimum values of vc (t) given by (22). The maximum value (vcm ax ) occurs when sin (2ωg t − θg + φg ) = 1
and sin (2ωl t + 2ε + φl ) = −1, simultaneously, and the minimum value (vcm in ) occurs when sin (2ωg t − θg + φg ) = −1
and sin (2ωl t + 2ε + φl ) = 1, simultaneously. Hence,
Nl Xcl fl
cos φl
vcm ax ≃ E +
+1
(23)
2E
fg cos (θg + φg )
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Nl X c
kε .
(28)
2E
Consequently, the maximum capacitor voltage fluctuation
∆vcm ax = vcm ax − vcm in is given by
vcm in ≃ E −
Nl X c
kε .
(29)
E
Next, it will be shown in a synchronization technique, between input and output voltages, that results in reduction of
kε .
This analysis can be expanded to take into account the existence of harmonic in the input voltage. In this case, it can
be shown that the maximum capacitor voltage fluctuation has
an additional smaller term proportional to the amplitude of the
harmonic and the inverse of its frequency.
∆vcm ax ≃
V. SYNCHRONIZATION TECHNIQUE
In the case of same grid and load frequencies, i.e., ωg =
ωl = ω, input and output voltages synchronization can be used
to reduce kε and the capacitor voltage fluctuation as well.
The term kε reaches its maximum and minimum value for
ε = − (θg + φl + π) /2 and ε = −(θg + φl )/2, respectively.
This can be also seen from the expression (14) for dc-link capacitor power.
The boost filter reactance Xg can be chosen based on the
input current ripple and voltage drop along the inductor for
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275
VI. CAPACITOR BANK DESIGN
In order to correctly apply the input voltage with amplitude
Vg and the output voltage with amplitude Vl , the dc-link voltage
vc has to be larger than both Vg and Vl at any instant. Therefore,
the minimum value of vc given in (24) must satisfy
vcm in ≥ max(Vg , Vl ).
(30)
By choosing the case limit, i.e., vcm in = max(Vg , Vl ), the
impedance Xcl can be written from (24) as
Xcl =
Nl
2E
fl
fg
E − max (Vg , Vl )
cos φl
1+
2N l X g cos φ l
E g2
2
.
(31)
+1
Once load and grid voltages are specified, the average value of
the capacitor voltage must be chosen based on the acceptable dc
voltage fluctuation (E − max (Vg , Vl )). Hence, the impedance
Xcl , and consequently the capacitor C, can be calculated from
(31).
On other hand, when grid and load frequencies are the same,
from (28) the impedance Xc can be written as
Xc =
E − max (Vg , Vl )
.
Nl
2E kε
(32)
By using Mode II of the synchronization technique (ε =
), expression (32) can be written as
θ +φ
− g2 l
Xc =
Fig. 2. (a) k ε as a function of the load power factor φ l for ε = 0, ε = −(θg +
φ l )/2 and ε = −(θg + φ l + π)/2. (b) Optimum angle ε and the power angle
θg as a function of load power factor.
maximum load power. It was shown by [26] that a boost filter
reactance of Xg = 0.2 pu satisfy both design requirements. If
Xg = 0.2 pu, then the power angle θg is limited to θg m ax ≃ 12◦ ,
i.e., |θg | ≤ 12◦ , when the system power varies from no-load to
full-load condition.
√ Assuming rated conditions (Nl = 1 pu and Vl = Eg =
2 pu for root mean square voltages at 1 pu), kε is illustrated in Fig. 2(a) for ε = 0◦ , ε = − (θg + φl ) /2, and ε =
− (θg + φl + π) /2, as a function of load power factor (φl ≤ 0
implies in inductive load and φl ≥ 0 implies in capacitive
load). The term kε reaches zero when ε = − (θg + φl ) /2
and θg = ±φl , i.e., cos(θg ) = cos(φl ), and when ε = 0 and
θg = −φl . Fig. 2(b) shows the optimum angle ε and the power
angle θg as a function of load power factor.
Two modes of synchronization for vl can be conceived: in
Mode I, vl is synchronized with eg with ε constant equal to
ε∗ (ε∗ being the rated value of − (θg + φl ) /2 or simply 0), or
Mode II, vl is synchronized with eg with ε variable equal to
− (θg + φl ) /2 (using measured values of θg and φl ). Mode I is
the simplest one and Mode II can be used if φl and θg change
slowly and the load frequency ωl is allowed to change with a
tolerance ∆ωlm ax , i.e., ωl = ωlN ±∆ωlm ax , where ωlN is rated
load frequency. In Mode II the reduction of ∆vc is maximal.
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E − max (Vg , Vl )
.
N l cos φ l
2E cos θ g − 1
(33)
Therefore, the capacitor can be designed from (33) based on:
the maximum value of dc power (Pl = Nl cos φl ); the chosen
dc-link voltage (E); the maximum acceptable voltage fluctuation (E − max (Vg , Vl )); the maximum load power factor angle
(φlm ax ); and the maximum power angle (θg m ax = ±12◦ ).
The capacitor size reduction achieved with the synchronization technique (32), when compared to the general case (31),
can be indicated by
δc =
C2
Xcl
=
=
C1
Xc
kε
cos φ l f l
cos θ g f g
+1
(34)
where C1 and C2 are the required capacitance value for same
voltage fluctuation in the general case and when the synchronization technique is used, respectively. Hence, when the synchronization technique is used, the required capacitance is only
a fraction δc of the capacitance required in the general case.
By using Mode II of the synchronization technique (ε =
−(θg + φl )/2) and fl /fg = 1, the expression for δc in (34)
can be written as
cos φl − cos θg .
(35)
δc = cos φl + cos θg √ Assuming rated conditions (Nl = 1◦pu and Vl = Eg =
2 pu), δc is illustrated in Fig. 3 for ε = 0 , ε = − (θg + φl ) /2,
and ε = − (θg + φl + π) /2, as a function of load power factor.
One can see from Fig. 3 that the capacitor can be significantly
decreased by using the synchronization technique. On other
276
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Fig. 4.
Fig. 3. Relation δc (C 2 /C 1 ) between the capacitance in general case (C 1 )
and that with synchronization technique (C 2 ).
TABLE I
CAPACITANCE SIZE REDUCTION AS A FUNCTION OF THE POWER FACTOR ANGLE
hand, when the load power factor is close to zero, no capacitor
reduction is achieved. However, this condition is not a usual
case.
The capacitor size reduction is mainly a function of the maximum load power factor angle. In Table I, δc is given for eight
values of load power factor angle. Even if the load power factor is small as cos φl = 0.33, the required capacitance for same
ripple is half of the one in the general case.
The capacitor design presented here was based on the case of
ideal capacitor and steady-state, where no dc power is absorbed
by the capacitor. However, real capacitors appear to have a dc
power component term. An additional parameter to incorporate
this fact on the capacitor model is the equivalent series resistance
(ESR). This term has the effect of increasing the total dc-link
voltage. Moreover, the dc-link voltage becomes noisier due to
the series resistance voltage been submitted to high frequencies
capacitor power. However, the ESR decreases with the increase
of the capacitor size and frequency. In fact, it is smaller than
0.1 Ω for an electrolytic 1000 µF capacitor. Therefore, the net
effect on the capacitor size caused by the ESR can be neglected.
VII. CONTROL SYSTEM
Fig. 4 presents the block diagram of the proposed control
system. The dc-link voltage vc is controlled at a reference value
by using controller Rc that provides the amplitude of the reference current Ig∗ . The instantaneous reference current i∗g is
synchronized with eg in order to control the power factor. This
synchronization is obtained via blocks SYNe and GENig . The
synchronization is implemented by processing eg through a zero
crossing detector followed by a phase-comparator. The output
angle δg of block SYNe indicates the instantaneous phase of eg .
The current controller is implemented using a controller indicated by the block Rg . The controller Rl defines Vl∗ , in the case
in which an output closed loop is required.
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Block diagram of the control scheme of the full-bridge converter.
The synchronization is implemented in Modes I and II. In
Mode II, the power factor angle φl and the input power angle θg
must be measured. In this paper, these angles were measured by
using a cross-zero detector scheme applied to the reference load
voltage vl∗ and measured load current il to determine φl , and
applied to reference grid voltage vg∗ and measured grid current
ig to determine θg .
The synchronization is achieved by using block SYNe.
Modes I and II are selected by the switch ks . The block GENvl
is similar to block GENig .
VIII. SIMULATION RESULTS
The parameters used in the simulation tests were fs =
10 kHz, C = 1100 µF, Lg = 10 mH, Eg = Vl = 220 V, ωl =
ωg = 120 πrad/s, and E = 350 V.
Fig. 5(a) and (b) shows the simulated capacitor voltage (top), grid current (middle) and load current (bottom)
for ε = −(θg + φl )/2 (Mode II) and ε = −(θg + φl + π)/2,
respectively.
The case of no synchronization is implemented considering
ε = −(θg + φl + π)/2, which means the worse case of synchronization, or, in other words, when the rectifier and inverter
operates with different frequencies. In this case, when the synchronization technique is applied, the reduction in the dc-link
voltage fluctuation is close to 80%.
IX. EXPERIMENTAL RESULTS
The full-bridge converter has been implemented in the laboratory. The set-up used in the experimental tests is based
on a microcomputer equipped with appropriate plug-in boards
and sensors. In the experimental tests the following parameters were used: fs = 10 kHz, C = 1100 µF, Lg = 6 mH, and
ωl = ωg = 120 πrad/s.
Fig. 6(a)–(c) shows experimental results for the converter supplying a RL single-phase load (Pl = 125 W, cos φl = 0.946)
with Eg = Vl = 100 V and E = 120 V. The waveforms in these
figures are the capacitor voltage for ε = 0 – Mode I – (top), ε =
−(θg + φl )/2 – Mode II – (middle) and ε = −(θg + φl + π)/2
(bottom). As expected from the theoretical analysis, the fluctuation reduction in the dc-link voltage is obtained with synchronization technique, especially for Mode II, which provides 85%
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277
Fig. 7. Peak–peak capacitor voltage fluctuation (top) and peak grid current for
several values of load power with and without the proposed algorithm (bottom).
Fig. 5. Simulated (top) capacitor voltage, (middle) grid current, and (bottom)
load current. (a) ε = − (θg + φ l ) /2. (b) ε = − (θg + φ l + π) /2.
Fig. 6. Experimental (top) ac capacitor voltage for ε = 0, (middle) ε =
− (θg + φ l ) /2 and (bottom) ε = − (θg + φ l + π) /2.
Fig. 8. Experimental capacitor voltage (top), grid voltage and current
(middle), load voltage and current (bottom) for cos φ l = 0.99. (a) ε =
− (θg + φ l ) /2. (b) ε = − (θg + φ l + π) /2.
of reduction when compared to the worst case. On the other
hand, Mode I gives 70% of reduction in the dc-link voltage
fluctuation. But besides that, in Mode I, it is not necessary to
acquire the load power factor.
Fig. 7 shows the experimental value of peak-to-peak capacitor voltage and input peak current for several values of load
power ranging from 100 to 2000 W and constant power factor
cos (φl ) = 0.99. The tests were carried out with the Mode II
and without the algorithm when the maximum dc-link voltage
fluctuation might happen considering ε = −(θg + φl + π)/2. It
can be seen that dc-link capacitor voltage fluctuation increases
with the load power when the algorithm was not used. On the
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Fig. 9. Experimental capacitor voltage (top), grid voltage and current
(middle), load voltage and current (bottom) for cos φ l = 0.55. (a) ε =
− (θg + φ l ) /2. (b) ε = − (θg + φ l + π) /2.
other hand, the synchronization technique keeps the dc-link
voltage fluctuation constant, even changing the power load. In
this test and in the next ones, it was used Eg = Vl = 220 V and
E = 350 V.
Figs. 8 and 9 show the capacitor voltage, grid voltage and
current, filtered load voltage, and load current for Pl = 1200 W
with cos φl = 0.99 and cos φl = 0.55 for ε = −(θg + φl )/2
and ε = −(θg + φl + π)/2. Note that the voltage fluctuation
is smaller when the technique is used and it increases, when
decrease the load power factor.
Fig. 10(a) and (b) shows the grid voltage and current, load
voltage and dc-link voltage with and without the synchronization technique. These results are obtained for the case in which
there is 20% of third harmonic present in the grid voltage. Even
in this case, the control technique permit to reduce the dc-link
voltage fluctuation.
Fig. 11 shows the capacitor voltage, grid current, load current
for a change of load from 2000 to 100 W and back to 2000 W.
Note that, even in the case of hard load transient the dc-link
voltage is under control. In Fig. 11, a different waveform presentation was used (obtained from oscilloscope).
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Fig. 10. Experimental results with distortion in the grid voltage (20% of third
harmonic). (a) ε = − (θg + φ l ) /2. (b) ε = − (θg + φ l + π) /2.
Fig. 11. Experimental load transient for a change of load from 2000 to 100 W
and back to 2000 W.
X. CONCLUSION
This paper has presented a synchronization technique to reduce the ac power and voltage fluctuation in the dc-link of
single-phase full-bridge converters. It has been considered viable for applications where the load frequency is equal to the
input frequency. Two modes of synchronization for the converter
www.DownloadPaper.ir
DE FREITAS et al.: SINGLE-PHASE TO SINGLE-PHASE FULL-BRIDGE CONVERTER OPERATING
voltages were proposed. In Mode I, the converter load voltage is
synchronized with the grid voltage with a constant phase angle.
In Mode II the converter load voltage is synchronized with grid
voltage for a variable phase angle equal to − (θg + φl ) /2. In
Mode II, the reduction of the ac dc-link power is maximal. The
technique can be directly adapted to be used for three-leg and
two-leg ac–ac dc-link converters, in order to reduce the ac dclink power. Simulated and experimental results have been presented to demonstrate the effective performance of the method.
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Isaac Soares de Freitas (S’04–M’09) was born in
Itaporanga, Paraı́ba, Brazil, in 1982. He received the
B.S., the M.S., and the Ph.D. degrees in electrical
engineering from the Federal University of Campina
Grande, Campina Grande, in 2004, 2005, and 2007,
respectively.
From 2006 to 2007, he was with the Electric Machines & Power Electronics Laboratory, Texas A&M
University, College Station, as a Visiting Scholar. He
has been with the Department of Electrical Engineering, Federal University of Paraı́ba, João Pessoa, since
July 2008, where he is currently a Professor of electrical engineering. His research interests include power electronics and electrical drives.
Cursino Brandão Jacobina (S’78–M’78–SM’98)
was born in Correntes, Pernambuco, Brazil, in 1955.
He received the B.S. degree in electrical engineering from the Federal University of Paraı́ba, Campina Grande, in 1978, and the Diplôme d’Etudes
Approfondies, and the Ph.D. degrees from Institut
National Polytechnique de Toulouse, Toulouse,
France, in 1980 and 1983, respectively.
From 1978 to March 2002, he was with the Department of Electrical Engineering, Federal University
of Paraı́ba, Campina Grande. He has been with the
Department of Electrical Engineering, Federal University of Campina Grande,
Campina Grande, since April 2002, where he is currently a Professor of electrical
engineering. His research interests include electrical drives, power electronics,
and energy systems.
Euzeli Cipriano dos Santos Jr. (S’04–M’08) was
born in Picuı́, Paraı́ba, Brazil, in 1979. He received
the B.S., the M.S., and the Ph.D degrees in electrical
engineering from the Federal University of Campina
Grande, Campina Grande, in 2004, 2005, and 2007,
respectively.
From 2006 to 2007, he was with the Electric Machines & Power Electronics Laboratory, Texas A&M
University, College Station, as a Visiting Scholar.
From August 2006 to March 2009, he was with the
Centro Federal de Educação Tecnológica da Paraı́ba,
UNED/CZ, Cajazeiras. He has been with the Department of Electrical Engineering, Federal University of Campina Grande, since March 2009, where he
is currently a Professor of electrical engineering. His research interests include
power electronics and electrical drives.