Indian J Phys (August 2013) 87(8):733–740
DOI 10.1007/s12648-013-0294-4
ORIGINAL PAPER
Analysis of interface states and series resistances in Au/p-InP structures
prepared with photolithography technique
D Korucu1*, Ş Karataş 2 and A Türüt3
1
Department of Material Science and Engineering, Faculty of Engineering, Hakkari University, Hakkari 38400, Turkey
2
Department of Physics, Faculty of Sciences and Arts, University of Kahramanmaraş Sütçü İmam, Kahramanmaraş 46100, Turkey
3
Department of Engineering Physics, Faculty of Science, Medeniyet University, Istanbul 34100, Turkey
Received: 24 January 2013 / Accepted: 10 April 2013 / Published online: 9 May 2013
Abstract: Some electronic parameters such as ideality factor, barrier height, series resistance and interface state densities
of the Au/p-InP Schottky barrier diodes with 100 and 200 lm diameter contacts have been investigated. We have
calculated electronic parameters of these two diodes and compared using experimental forward bias current–voltage
(I–V) and reverse bias capacitance–voltage measurements at room temperature. The values of ideality factor and barrier
height for the 100 and 200 lm diameter diodes have been obtained as 1.07, 0.84 and 1.08, 0.80 eV, respectively. In
addition, we have calculated interface state density (NSS) as a function of energy distribution (ESS–EV) of these diodes and
compared them. The energy distribution of interface states density has been determined from the forward bias I–V characteristics by taking into account the bias dependence of the effective barrier height. Density of interface states in the
considered energy range are in close agreement with values obtained for 100 and 200 lm diameter Au/p-InP.
Keywords:
Au/p-InP structures; III-V Compounds; Barrier height; Series resistance; Ideality factor; Interface states
PACS Nos.: 73.30.?y; 73.40.Ns; 73.61.Ey
1. Introduction
Due to importance of performance and reliability of
Schottky barrier diodes (SBDs) in electronics industry,
their electrical characteristics have been extensively studied [1–8]. Indium phosphide (InP) is probably the best
understood binary semiconductor after silicon and gallium
arsenide. Indium phosphide is used primarily for the fabrication of optoelectronic devices, because it operates at
high efficiency and high power. Indium phosphide is also
used in certain appropriate areas such as high-performance
integrated circuits [1–3]. Indium phosphide is considered
for a variety of device applications including microwave
diodes, field effect transistors, solar cells and photo
detectors. The most widely used contact SBDs require a
complementary understanding of their electrical characteristics. It is well known that the electrical characteristics
*Corresponding author, E-mail: dkorucu@yahoo.com
of metal/semiconductor contacts are controlled mainly by
their surface properties [4, 5]. Therefore, one of the key
advantages of indium phosphide is its potential for fabrication of very small devices. Because indium phosphide
and its ternary (InGaP) and quaternary (InGaAsP) derivatives have relatively higher refractive indices than those of
other optical materials, these compounds allow for devices
with much sharper and smaller bends. At the same time,
one of the promising materials for space solar cells is the
III–V semiconductor (indium phosphide) which has shown
good performance in both homojunction and heterojunction structures [4–8].
The Schottky barrier height is an important parameter
which determines the electrical characteristics of metal–
semiconductor (MS) contacts and has crucial importance
for successful operation of semiconductor devices. Schottky barrier height is defined as difference between edge
of respective majority- carrier band of semiconductor and
Fermi level at the interface. Most of the experimental and
theoretical studies have been made on nature and formation of the barrier height at MS contacts [1, 9–11]. It is
Ó 2013 IACS
734
well known that, unless specially fabricated, a SBD possesses a thin interfacial native oxide layer between the
metal and semiconductor. The existence of such an insulating layer converts the devices to metal-insulatingsemiconductor (MIS) diode and may have a strong influence on the diode characteristics as well as a change of
the interface state charge with bias which gives rise to an
additional field in the interfacial layer [12–14]. Furthermore, analysis of the I–V characteristics of the SBDs at
room temperature does not give detailed information
about their conduction process or the nature of barrier
formation at MS interface [15]. The dependence of the
diode contact diameter on I–V characteristics allows us to
understand different aspects of conduction mechanisms.
For, studies on these subjects in literature are limited.
Thus, fundamental mechanisms that determine the barrier
height are still not fully understood.
Indium phosphide (InP) is of considerable interest in
optoelectronic applications and high speed electronic
devices. This is due to a direct band gap and high electron
mobility of InP, both of which are very important in fabricating some useful devices in technology [16–18]. Thus,
in recent years there has been growing interest in the field
of InP semiconductors due to their successful application in
optical and electronic devices. For instance, Gullu and
Turut [19] have formed quercetin/p-InP organic–inorganic
(OI) solar cell via solution-processing method and characterized by current–voltage (I–V) and capacitance–voltage
(C–V) measurements at room temperature. Ocak et al. [20]
investigated the electrical and photoelectrical properties of
a ZnO/p-InP hetero-junction obtained by dc sputtering
process. Song et al. [21] have also suggested that the barrier inhomogeneities can occur as a result of inhomogeneities in the interfacial oxide layer composition, nonuniformity of the interfacial charges and interfacial oxide
layer thickness. Asubay et al. [22] have determined laterally homogeneous BH of a number of metal/p-type InP
(Cu, Au, Al, Sn, Pb, Ti, Zn) by help of the linear relationship between effective BHs and ideality factors. Tung
[23] and Sullivan et al. [24] have modeled imperfect
Schottky contacts by assuming lateral variations of the
barrier height. They found larger ideality factors and
smaller effective barrier heights when they increased the
inhomogeneity of barriers.
Generally, main electrical parameters such as SBH,
ideality factor (n), series resistance (RS) and interface states
(NSS) are the most important parameters of the (SBDs). In
this study, forward bias current–voltage (I–V) characteristics of Au/p-InP (MS) contacts have been studied at room
temperature and characteristic Schottky diode parameters
such as ideality factors and barrier heights deduced from
the current–voltage (I–V) characteristics have been compared with each other.
D Korucu et al.
2. Experimental details
The Au/p-InP SBD structures were fabricated using p-type
single crystals InP wafer with \100[ surface orientation,
having a thickness of 350 lm, 20 diameter and 4–8 9 1017
cm-3 carrier concentration (given by the manufacturer).
Before the SBD fabrication process, InP wafer was degreased for 5 min in organic solvent of trichloroethylene
(CHClCCl2), acetone (CH3COCH3) and methyl alcohol
(CH3OH), etched in a sequence of sulfuric acid (H2SO4)
and hydrogen peroxide (H2O2), 20 % hydrofluoric acid
(HF, a solution of nitric acid (6HNO3):1HF:35H2O, 20 %
HF and finally quenched in de-ionized water of resistivity
of 18 MX cm for a prolonged time. Preceding each
cleaning step, the wafer was rinsed thoroughly in de-ionized water of resistivity of 18 MX cm. After the surface
cleaning of InP wafer, low resistance ohmic contacts to
p-InP wafers were made by using high purity (99.999 %)
Al with a thickness of about 2,000oÅ and Al was evaporated onto whole back side of InP wafer at a pressure about
10-6 Torr in high vacuum system. The ohmic contacts
were formed by a temperature treatment at 400 °C for
3 min. For Schottky diode formation, the InP wafer was
placed on a rotating table. The rotating table was rotated at
a fixed rotational speed with 5,000 rpm for 30 s with
positive photoresist (AZ5214). After the photoresist was
deposited on top of the p-InP surface, the p-InP wafer was
baked at 110 °C for 60 s. This step caused to clean
unusually the solvent on top of the p-InP surface.
Depending on the viscosity of the photoresist, a certain
thickness of film remains on the substrate. Then the sample
was dried with N2. After that UV light was used to cure the
resist into the desired structural pattern using a photo mask
for 90 s. The photoresist was then developed for 60 s, with
exposed regions dissolving in the solvent. Finally photoresist was removed for 3 min by acetone and dried with
N2.The Schottky contacts were formed by photolithography process onto the front surface through a photo mask of
Au dots diameters ranging from 20 to 200 lm (the diode
area for 200 lm was found to be 3.14 9 10-4 cm2). All
evaporation process was carried out in a turbo molecular
fitted vacuum coating unit at about 10-6 mbar.
3. Results and discussion
3.1. Analysis of current–voltage (I–V) characteristics
Figure 1 shows the experimental forward bias I–V characteristics of 100 lm (D1) and 200 lm (D2) diameter
Au/p-InP Schottky contacts. The forward bias current–
voltage characteristics are exponential at low bias voltages.
However, at higher voltages a deviation in (I–V)
Analysis of interface states
characteristic is observed due to series resistance and interfacial layer. It is observed that the properties of Au/p-InP
SBDs are uniform over different diameter contacts for same
diode. The forward bias saturation current densities (I0) are
1.74 9 10-11A and 8.61 9 10-11 A respectively for D1 and
D2 diodes obtained from intercept the linear portion of lnI
versus V plot at V = 0. It can be seen in Fig. 1 that I–V
characteristic of the Au/p-InP SBD shows a good rectifying
behaviour with non-ideal behaviour. The diode parameters
are determined from the forward bias I–V characteristics,
which is usually described within the thermionic emission
theory. If a Schottky diode with a series resistance is considered, it is assumed that the forward bias-thermionic
emission current of the device can be expressed as [1, 9]:
qðV IRS Þ
I ¼ I0 exp
ð1Þ
nkT
where V is applied voltage drop across the junction, q is
electronic charge, k is Boltzmann’s constant
(8.62 9 10-5eV/K), T is absolute temperature in Kelvin, n
is diode ideality factor with measure of conformity of the
diode to pure thermionic emission and I0 is the saturation
current determined by
qUbo
2
I0 ¼ AA T ð2Þ
kT
I0 is obtained from the intercept of lnI versus V plot
(Fig. 1) at V = 0, A is diode area, A* is effective Richards
constant which is 76.8 A/cm2K2 for p-type InP [25] and
Ubo is barrier height. From Eqs. (1) and (2), ideality factor
735
n and barrier height Ubo can be written as below
respectively [1, 9];
n¼
q dV
kT dðln IÞ
ð3Þ
2
kT
AA T
ln
¼
q
Io
ð4Þ
and
Ubo
Diode ideality factor of the diode D1 is better because it is
small. The values of 1.07, 0.84 and 1.08, 0.80 eV for the
ideality factor n and the zero-bias barrier height Ubo of
diodes D1 and D2, have been obtained from the linear
regions of the forward bias I–V plots, respectively. The
effect of series resistance in these linear regions is not
significant.
For an ideal Schottky barrier diode n = 1. However, n
has usually a value greater than unity. But, this study
clearly shows that the values of ideality factor are very
close to unity. This value indicates that the effect of series
resistance in these linear regions is not significant (as
mentioned above), but the series resistance is significant in
the downward curvature, which represents non-linear
region, of the forward bias I–V characteristics. Thus, the
forward bias I–V characteristics are linear on a semi-logarithmic scale at low forward bias voltages but deviate
considerably from linearity due to the effect of series
resistance, the interfacial layer, and the interface states
when the applied voltage is sufficiently large [26]. At high
currents, the observed deviation depends on parameters
such as the interfacial layer thickness, the interface states
density and series resistance, as one would expect [27–30].
Lower are the interface states density and the series resistance, greater is the range over which I–V curve does in
fact yield a straight line [26–31]. As the linear part of the
forward I–V plots is reduced, the accuracy of determination
of barrier height and ideality factor becomes lower. The
ideality factor and series resistance have been evaluated
using a method developed by Cheung et al. [32] in the high
current range where the I–V characteristic is not linear.
Cheung’s functions can be written as follows:
dV
kT
¼ IRS þ n
d(lnI)
q
kT
I
HðIÞ ¼ V n
ln
;
q
AA T 2
ð5Þ
ð6Þ
and
HðIÞ ¼ IRS þ nUb
Fig. 1 The current and ideality factor versus voltage characteristics
of the Au/p-InP Schottky barrier diodes at room temperature for D1
and D2 diodes, respectively. The voltage dependences of the ideality
factors of both the diodes are also shown
ð7Þ
Figures 2 and 3 show the plots of dV/dln(I) versus I and
H(I) versus I, respectively. Eq. (5) should give a straight
line for data in the downward-curvature region of forward
736
bias I–V characteristics. In Fig. 2, the slope and y-axis
intercept of a plot of dV/d(ln I) versus I plot give RS and
nkT/q, for both D1 and D2, respectively. The values of
ideality factor and series resistance obtained from Eq. (5)
are 2.66–2.71 and 32.85–29.50 X, for D1 and D2, respectively. It is clearly seen that the values of ideality factor
resulting from the series resistance and interface effects,
are greater than the values of 1.07 and 1.08 obtained from
the linear region of the I–V characteristics, for D1 and D2
SBDs, respectively. Reason for this difference can be
attributed to the existence of effects such as series resistance and bias dependence of Schottky barrier height Ub
according to the voltage drop across the interfacial layer
and interface states with bias in this concave region of the
I–V plot [1, 9, 33, 34].
In the same way, the barrier height and series resistance
values have been calculated from Fig. 3 and Eq.(7) (from
plot of H(I)-I) using obtained barrier height value and
found to be 0.562–0.542 eV and 33.96–30.52 X, for D1
and D2 Schottky barrier diodes, respectively. It can be seen
that the value of RS obtained from H(I)–I plots is in
agreement with that obtained from dV/d(ln I)–I plot. That
is, the RS values obtained from the Cheung functions are in
agreement with each other due to consistency of Cheung
functions. Furthermore, due to potential drop across interfacial layer, zero bias barrier height is lower than that
expected in an ideal diode and similarly the potential
across the interfacial layer varies with bias, because of the
electrical field present in the semiconductor and the change
in the interface [35, 36].
In order to compare effective Schottky barrier heights of
Au/p-InP SBDs, Norde method [37] is also employed
because high series resistance can hinder accurate evolution of barrier height from the standard ln (I)-V plot. In this
D Korucu et al.
Fig. 3 Experimental value of H(I) versus I curves of D1 and D2
diodes
method, a function F(V) is plotted against voltage. The
function F(V) is given by;
V kT
I ðV Þ
F ðV Þ ¼ ln
ð8Þ
c
q
AA T 2
where c is an arbitrary parameter, greater than n and I(V) is
the current obtained from I–V curve and other parameters
are described above. Therefore, the effective barrier height
and series resistance can be determined by
hc niV
kT
o
Ubo ¼ F ðV0 Þ þ
ð9Þ
n
q
c
where F(V0) is the minimum value of F(V), V0 is the
corresponding voltage. Figure 4 shows the F(V)–V plots of
the Au/p-InP Schottky barrier diodes for both D1 and D2
SBDs. From Norde’s functions, the series resistance (RS)
value can be determined as:
RS ¼
Fig. 2 Experimental value of dV/dln(I) versus I curves of D1 and D2
diodes
cn
I
kT
q
ð10Þ
From F(V)–V plots, values of barrier height and series
resistance (RS) have been determined as 1.094 eV; 77.47 X
for D1 diode and 1.044 eV; 71.88 X for D2 diode,
respectively. In general, calculations show that the values
of barrier heights and series resistance obtained from
Norde’s method are higher than these obtained from the
Cheung methods. Because, Cheung functions are only
applied to nonlinear region (high voltage region) of semilog forward bias I–V characteristics whereas, Norde’s
functions are applied to the full forward bias I–V characteristics of the junctions [36, 37].
The downward curvature in I–V characteristics at high
forward bias values is attributed to a continuum of surface
states. In this region, the ideality factor is controlled by
Analysis of interface states
737
respond to AC signal. In Fig. 5, the C–V characteristic in
idealized SBDs case shows an increase in capacitance with
increasing forward voltage. If measurements are carried out
at sufficiently high frequencies, charge at the interface
states cannot follow an ac signal. This will occur when the
time constant is too long to permit the charge to move in
and out of the states in response to an applied signal. The
C-2–V characteristic illustrated in Fig. 6 is linear in
between -4.2 and 0.8 V at 500 kHz. The depletion layer
capacitance of the diode can be expressed as [1, 9];
1
2 ð Vd þ V Þ
¼
2
C
qes e0 NA A2
Fig. 4 Experimental value of F(V) versus I curves of D1 and D2
diodes
interface states. Therefore, the I–V data of diodes D1 and
D2 shown in Fig. 1 fit well to Eqs. (11) and (12)
qV
11
I ¼ 1:74x10 exp
ð11Þ
nkT
qV
11
ð12Þ
I ¼ 8:61x10 exp
nkT
respectively, with the n values given in Table 1, where
1.74 9 10-11 A and 8.61 9 10-11 A are the saturation
currents of diodes D1 and D2, respectively. The magnitude
of saturation current of D1 is less than the saturation current of diode D2. The reduction in saturation current in D1
device compared to D2 diode caused by the interfacial
layer is due to a combination of an increase in barrier
height (0.84 eV vs. 0.80 eV) and a considerable decrease
in the value of Richards constant (A*). A number of theories [30] have been proposed for explaining the reduction
of saturation current by considering the factors governing
barrier height modification and transport controlled
including surface states, fixed charges, traps, tunnelling or
hopping conduction through the insulator and asymmetrical tunnelling probabilities for majority and minority carrier [30].
3.2. Analysis of capacitance–voltage (C–V)
characteristics
Capacitance–voltage (C–V) characteristic is one of the
fundamental properties of Schottky contacts. The reverse
bias capacitance measurements are made at a high frequency (500 kHz), so that the interface states are unable to
ð13Þ
where A is the area of the diode, V is the magnitude of
the reverse bias voltage, Vd is diffusion potential at zero
bias and is determined from the extrapolation of the C-2
versus V plot to the V-axis, es is the dielectric constant of
the InP (= 12.5eo), eo is the dielectric constant of vacuum
(= 8.85 9 10-14 F/cm), q is the electronic charge and NA is
the carrier concentration. The diffusion potential or built-in
potential is usually measured by extrapolating C-2–V plot
to the V-axis. The barrier height, UCV, from C–V measurement is defined by;
kT
NV
UCV ¼ Vi þ
þ kT ln
DUb ¼ Va þ EF DUb
q
NA
ð14Þ
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
where DUb ¼ qEm =4pes e0 is the image force that alone
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
causes barrier lowering, Em ¼ 2qNA VD =es eo is the maximum electric field, Vi is the intercept point of V axis of C-2
versus V curve and EF is the potential difference between
Fermi level and top of the valance band in neutral region of
p-InP and can be calculated knowing the carrier concentration NA and the effective density of states in valence
band. The doping concentration and zero-bias barrier for
diode D1 are 2.86 9 1016 cm-3 and 1.52 eV and for diode
D2 are 3.82 9 1017 cm-3 and 1.125 eV. The /b (C–V)
value obtained from C–V measurement is higher than that
of /b value obtained I–V measurements, as expected. The
discrepancy between /b (C–V) and /b (I–V) can be due to
existence of excess capacitance and Schottky barrier height
inhomogeneities [24]. Direct current across the interface is
exponentially dependent on barrier height and the current is
sensitive to barrier distribution at the interface. Through,
the capacitance is insensitive to potential fluctuations on a
length scale of less than the space charge width that the
capacitance–voltage method averages over the whole area.
Furthermore, as explained in [1, 29, 31], this difference is
explained due to an interface layer or to trap states in
the substrate, effect of image force and barrier
inhomogeneities.
738
D Korucu et al.
Table 1 Interface states energy distribution obtained from the forward bias I–V characteristics at room temperature; Ubo (C–V) = 1.52 eV for
D1 (for 100 lm) and Ubo (C–V) = 1.125 eV for D2 (for 100 lm) Schottky barrier diodes
D1
D2
12
Voltage (V)
n
Ue (eV)
ESS–EV (eV)
NSS 9 1013 (eV-1m-2)
8.808
0.12
1.11
0.805
0.685
1.434
7.287
0.14
1.10
0.806
0.666
1.290
0.687
0.668
6.631
6.298
0.16
0.18
1.09
1.08
0.807
0.808
0.647
0.628
1.179
1.105
0.849
0.649
6.190
0.20
1.08
0.808
0.608
1.052
1.06
0.850
0.630
6.098
0.22
1.08
0.810
0.590
1.029
1.06
0.851
0.611
6.089
0.24
1.07
0.811
0.571
9.972
0.26
1.06
0.852
0.592
6.023
0.26
1.07
0.812
0.552
9.700
0.28
1.06
0.853
0.573
6.029
0.28
1.07
0.813
0.533
9.674
0.30
1.06
0.854
0.554
6.057
0.30
1.07
0.814
0.514
9.595
0.32
1.06
0.856
0.536
6.130
0.32
1.07
0.815
0.495
9.588
0.34
1.06
0.857
0.517
6.196
0.34
1.07
0.817
0.477
9.734
0.36
1.06
0.859
0.499
6.342
0.36
1.08
0.819
0.459
1.004
0.38
1.07
0.860
0.480
6.542
0.38
1.08
0.822
0.442
1.062
0.40
1.07
0.863
0.463
6.833
0.40
1.09
0.825
0.425
1.162
0.42
1.07
0.865
0.445
7.266
0.42
1.10
0.831
0.411
1.313
Voltage (V)
n
Ue (eV)
ESS–EV (eV)
NSS 9 10
0.12
1.09
0.847
0.727
0.14
1.07
0.847
0.707
0.16
0.18
1.07
1.06
0.847
0.848
0.20
1.06
0.22
0.24
-1
-2
(eV m )
Fig. 6 Plotting C-2 versus V of the D1 and D2 diodes
Fig. 5 Capacitance voltage characteristics at 500 kHz of the D1 and
D2 diodes
3.3. Analysis of interface state densities (NSS)
The most important characteristic of the MS, MIS and
MOS interfaces is the nature of potential barrier between
Fermi level in the metal and the majority carrier’s band
edge of the semi-conductor at that interface. There is
always a deviation of the ideality factor at high currents
which depends on parameters such as interfacial layer
thickness, interface density and series resistance. Thus, for
calculating BH and other characteristic parameters, the
interface states play an important role at semiconductor
rectifying contacts. For a real Schottky diode having
interface states in equilibrium with the semiconductor, the
ideality factor (n) becomes greater than unity as proposed
by Card and Rhodercik [38] and is given by;
d es
nð V Þ ¼ 1 þ
þ q:NSS
ð15Þ
ei WD
where WD is space charge width, Nss is density of interface
states; es and ei are permittivity of the semiconductor and
interfacial layer, respectively. Evaluation of the interface
state energy distribution and relative interfacial layer
thickness can be performed using the formula derived by
Card and Rhoderick [38] and Kolnik and Ozvold [39, 40].
Analysis of interface states
739
In the case where all of the interface states are in
equilibrium with the semiconductor when the diode is
forward biased, in the reverse direction the change of the
interface state charge is negligible. In p-type
semiconductor, the energy of the interface states, Ess with
respect to the bottom of the conduction band at the surface
of the semiconductor is given by [1, 9, 27, 39–42];
ESS EV ¼ qðUe V Þ
ð16Þ
where
1
Ue ¼ Ubo þ 1 n
V
ð17Þ
Eqs. (15)–(17), along with the I–V characteristics can be
used for determination of interface states density as a
function of interface states energy ESS. Substituting the
values of the voltage dependence of n from Table 1 in
Eq. (15) and using es = 12.5eo [43], ei = 3.5eo [1, 9],
d = 1.87 Å (from reverse bias C–V characteristics),
WD = 2,604 Å (from zero bias capacitance of C–V measurement) for diode D1 and d = 1.31 Å (from reverse bias
C–V characteristics), WD = 692 Å (from zero bias capacitance of C–V measurement) for diode D2, the values of
NSS as a function of voltage (V) have been obtained and are
given in Table 1. The resulting dependence of NSS is
converted to a function of ESS using Eq. (16). NSS versus
ESS–EV is also shown in Fig. 7. In the forward bias case,
the increase in the effective barrier height (Ue) of both the
diodes with bias can be understood as follows: when the
diode is forward biased, quasi-Fermi level for the majority
carriers rises on the semiconductor side. Thus, most of the
holes will be injected directly into the metal forming a
thermionic emission current, while some of them are
trapped by the interface states. This charge capture process
results in an increase in the effective barrier height, thereby
reducing the diode current [26, 30, 31, 44].
It can be seen from Fig. 7 that the shape of the density
distribution of interface states is in the range of ESS
-0.314–ESS -0.726 eV and exponential increase in interface states density exists from midgap towards the bottom
of valance band. We think that these situations are due to
increase in series resistances, and the number of photogenerated charges at interface of the diode. Furthermore,
this rise is less significant for diode D1 compared to diode
D2. At any specific energy, the interface states density of
diode D1 is less than that of diode D2. This case can be
attributed to the fact that diode D1 has a thicker oxide layer
(1.87 Å) than diode D2 (1.31 Å). The obtained results
show that values of interface states densities and series
resistance are very important parameters which cause a
deviation from the ideality.
Fig. 7 Density of interface states as a function of ESS–EV of D1 and
D2 diodes
4. Conclusions
In this work, we have fabricated Au/p-type InP Schottky
barrier diodes and investigated its electrical properties by
means of current–voltage and capacitance–voltage measurements at room temperature. The forward I–V characteristics of the D1 and D2 diodes have been analyzed in
terms of the thermionic emission model. Ideality factors
obtained from I–V measurements are near 1 and series
resistances are small. The barrier height values obtained
from the C–V measurements are higher than these derived
from the I–V measurements as expected. The barrier height
and series resistance obtained from Norde’s function
compared with those from Cheung functions. The nonideal forward bias I–V behaviour observed in the D1 and
D2 Schottky diodes are attributed to a change in the metal–
semiconductor barrier height due to the interface states and
the interfacial layer. While the interface state density (NSS)
calculated for D1 diode account series resistance (RS) has
increased exponentially with bias from 8.81 9 1012
cm-2eV-1 in (ESS-0.726) eV to 9.43 9 1013 cm-2eV-1 in
(ESS-0.314) eV of p-Si, the NSS obtained for D2 account,
the series resistance has increased exponentially with bias
from of 2.41 9 1013 to 1.55 9 1014 cm-2eV-1 in the same
interval. The obtained results show that the interface states
at a native insulator layer play an important role in the
value of the barrier height, ideality factor, series resistance
of studied diode.
Acknowledgments This work is supported by the Turkish Scientific
and Technological Research Council of Turkey (TUBITAK). The
authors also thank to TUBITAK and Hakkari University.
740
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