Joint Impact of Random Variations and RTN on
Dynamic Writeability in 28nm Bulk and FDSOI
SRAM
Brian Zimmer1 , Olivier Thomas1,2 , Seng Oon Toh1,3 , Taylor Vincent1 , Krste Asanović1 , and Borivoje Nikolić1
Dept. of Electrical Engineering and Computer Sciences, University of California, Berkeley 94720, USA
2
3
CEA/LETI-MINATEC, Grenoble, France
ARM, Ltd., Cambridge, United Kingdom
Abstract—Improving SRAM minimum operating voltage
(Vmin ) in scaled process nodes requires characterization of
different failure mechanisms. Persistent errors caused by random
variations and intermittent errors caused by random telegraph
noise (RTN) both contribute to bitcell failure. Random Vth shift
was measured for 32,000 in-situ SRAM cells in both 28nm
bulk and FDSOI processes due to both random variations and
RTN, and dynamic writeability was measured by two different
write modes that accentuate different RTN behaviour. Measured
distribution parameters of both random variation and RTN
were used to calibrate an accelerated Monte Carlo simulation
that predicts a Vmin difference due to RTN. Measurements
show that while FDSOI technology reduces random variation by
approximately 27% compared to bulk, similar RTN amplitudes
slightly increase bitcell susceptibility to failures caused by RTN.
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I.
I NTRODUCTION
Accurate characterization of cell failures at SRAM Vmin
requires Monte Carlo simulation of devices with calibrated
variation models, and simulation predicts that cells with a
parametric shift beyond an Nx6-dimensional failure contour
will have persistent failures, where each of the N dimensions
represents a varying quantity in the cell. Additionally, random
telegraph noise (RTN) can cause intermittent failures of usually
functional cells, and it has been postulated that scaling will
make RTN a more significant source of error [1]. However,
the joint effect of RTN and random variation on SRAM
failure is still not well understood. This work investigates the
validity of the failure contour, and explores the interaction
between persistent and intermittent causes of SRAM bitcell
failures. Measurements are taken from cells within an SRAM
array, not padded-out cells, which enables more sample points
and increases certainty that the results will be applicable for
production SRAM arrays.
II.
C HARACTERIZATION S ETUP
The study is applied to an array of 32k 0.120µm2 bitcells
in a pre-production HKMG 28nm process [2]. Both bulk
and FDSOI wafers were manufactured using the same mask
set to provide a unique opportunity for comparison between
FDSOI and bulk. Bulk and FDSOI have different gate stacks
to adjust Vth . Figure 1 shows the chip photograph, physical organization, and characterization architecture. A programmable
BIST enables dynamic measurements, and separated supplies,
combined with a bitline mux, enable static IV measurements
similar to [3].
III.
M EASUREMENT OF R ANDOM VARIATIONS
Threshold voltage variation is measured for every transistor
in the SRAM array by using a modification of the direct bit
R/W
din
dout
clk FPGA test
harness
Control
I/O
BLTF BLFF
BLTS BLFS
(b) Characterization system architecture.
Fig. 1: 28nm characterization testchip details.
transistor access scheme (DBTA) [3]. The exact measurement
setup is depicted in Figure 2. Multiplexed bitlines and separated wordline and cell voltages enable IV measurements of
every cell in the array.
Figure 3 shows the Gaussian distribution of Vth for the
pull-up, pass-gate, and pull-down transistors of 32,000 cells.
FDSOI devices have approximately 27%, 26%, and 28%
lower standard deviation of Vth than bulk devices for the
pull-up, pass-gate, and pull-down respectively. Because IV
measurements are not performed on isolated devices, a transient simulation is performed to provide confidence that the
Vth measurement of a single transistor is not affected by
other transistors in the cell. The simulation netlist represents
the actual Vth measurement scheme and uses cell Vth shifts
annotated from actual measured data, and Figure 4 plots the
distribution of simulated measurement error of the DBTA
scheme.
IV.
M EASUREMENT OF R ANDOM T ELEGRAPH N OISE
RTN was measured using the alternating bias technique
[4]. Figure 5 provides procedure details, and shows example
waveforms of the alternating bias technique versus a traditional
RTN measurement. Traditional schemes can find trap emission
and capture time constants as a function of gate voltage, but
sweep 1.1 to 0.45
1.28
Vsg
sweep 0.95
to 0.40
1.28
0.1
1.0
sweep 0.9 to 0.4
1.0
Vgs
0.125
Vds
=0.05
1.0
Vds=0.05
1.0
Vgs
Measure I
On-chip
+
Measure I
Off-chip
+
On-chip
(a) Left pull-up.
On-chip
Off-chip
+
+
+
(b) Left pass-gate.
Off-chip
Measure I
+
(c) Left pull-down.
FDSOI
Vth (a.u.)
BULK
0.2
0.1
BULK
0.1
0.3
BULK
0.1
Measure
Vth
FDSOI
−2 0
2
Quantities
4
Memorize
operating
point
(OP)
1.0
0.7
Rel. Freq.
Turn off
device
Apply OP
Apply OP
Measure
Id vs. t
Measure
Id vs. t
Repeat 4 times
FDSOI
0.4
4
FDSOI
1.0 Bulk
1
1
was was was was was was was was
off on off on off on off on
0.5
0.5
0.7
FDSOI
0.4
0.7
1.0
−4 −2 0
2
Vth (a.u.)
Quantities
(c) Pull-down transistors.
0
4
Fig. 3: Histogram and normal QQ plots of measured Vth
distribution for 32k cells from both FDSOI and bulk chips.
0.5
0.4
0.3
0.2
0.1
0.0
−0.01
Turn on
device
Bulk
0.7
1.0
−4 −2 0
2
Vth (a.u.)
Quantities
(b) Pass-gate transistors.
0.2
0.0
0.4
Alternating bias algorithm
Bulk
FDSOI
0.2
0.0
0.4
0.7
∆ ID (a. u.)
0.3
1.0
0.4
0.7
1.0
−4
Vth (a.u.)
(a) Pull-up transistors.
Vth (a.u.)
0.0
0.4
Vth (a.u.)
Rel. Freq.
0.3
}
Rel. Freq.
Rel. Freq.
Fig. 2: Scheme used to measure Vth of each transistor in the SRAM array.
Pull-up
Pass-gate
0.00
0.01 −0.01 0.00
0.01 −0.01
V thmeas − V thsim
1
seconds
2
3
Alternating Bias
0
0
5
10 15 20 25
seconds
Traditional
Fig. 5: Alternating bias versus traditional RTN measurement
scheme.
the threshold voltage follow a lognormal distribution with a
long tail. Both pull-down and pass-gate NMOS devices show
similar RTN amplitudes, but for the pull-up PMOS devices,
RTN amplitude is slightly higher in FDSOI than in bulk.
Pull-down
0.00
0
0.01
Fig. 4: Vth measurement difference between measured Vth and
simulated scheme using transistor Vth shifts from measurement.
require sweeping the gate voltage and long measurement times.
The alternating bias technique speeds up the procedure by
alternately turning on and off the gate before measurement,
which attempts to force either emission or capture before the
testing period. While this technique emphasizes worst-case
RTN effects, it closely emulates the real operating conditions
of a cell, where devices are either turned on or off immediately
before an access. The measured amplitude distribution in
Figure 6 shows RTN-induced changes in drain current around
V.
S IMULATION - BASED WRITEABILITY ANALYSIS
Monte-Carlo-based measurements can be used to predict
the joint effect of random variation and RTN on writeability. To
accelerate Monte Carlo analysis of rare events, an importancesampling based simulation methodology is used [5]. Vth shift
for each device is equal to the sum of random variation
sampled from a normal distribution and RTN sampled from a
log-normal distribution. The parameters of these distributions
are taken from measured results.
Using the notation in Figure 7, failures to write-1 are
caused by weak PDR, PUL, PGL, and PGR combined with
strong PDL and PUR. RTN is assumed to only decrease Vth , so
the best-case RTN effect can be estimated by applying an RTNinduced negative Vth shift to PDR, PUL, PGL, and PGR while
masking RTN in PDL and PUR. Conversely, the worst case
FDSOI (fit)
FDSOI
BULK
Pass gate
0.9999
0.99
0.9
0.5
0.1
0.01
0.0001
Delta Id (log,a.u.)
Pull up
Probability
0.9999
0.99
0.9
0.5
0.1
0.01
0.0001
Probability
Probability
Pull down
BULK (fit)
0.9999
0.99
0.9
0.5
0.1
0.01
0.0001
Delta Id (log,a.u.)
Delta Id (log,a.u.)
Fig. 6: Lognormal probability plot of RTN-induced current differences at cell Vth using the alternating bias technique.
PGL
PDL
PUR
1
Vth shift (σ)
PUL
0
PGR
PDR
(storing '1')
Fig. 7: Transistor naming convention.
Probability of bitcell failure
100
10−1
10−2
10−3
10−4
10−5
10−6
10−7
10−8
0.5
Write A=1
Weaker
Stronger
PDR
PGL
PGR
PUL
PUR
Fig. 9: Vth shift vector for cells failing to write 1. Arrows
indicate worsening ability to write A=1.
Best RTN (Bulk)
Worst RTN (Bulk)
that worsens writeability for each device. Only writeability
failures are analyzed, and cells that are unstable at target Vdd
are filtered (to avoid simultaneous measurement of a cell’s
ability to write A without flipping back to Ā during a halfselect).
Best RTN (FDSOI)
Worst RTN (FDSOI)
0.6
0.7
0.8
0.9
Vdd (a.u.)
1.0
1.1
Fig. 8: Simulation of bitcell write failure probability for best
and worst case RTN using importance sampling methodology.
RTN effect can be estimated by applying RTN effects to PDL
and PUR while masking the other devices. This measure will
overestimate RTN effects, because RTN in multiple devices
can help and hurt a cell at the same time. While RTN-induced
current shift is only measured at cell Vth , this strategy assumes
that current differences at other voltages are caused by the
resulting threshold voltage shift of the device. Figure 8 plots
the resulting probability of bitcell failure versus supply voltage
from this study. While the decreased random variation standard
deviation in FDSOI is the primary influence on Vmin , RTN
causes a small but measurable difference in bitcell Vmin .
VI.
4
3
2
1
0
−1
−2
−3
−4
PDL
M EASUREMENT- BASED WRITEABILITY ANALYSIS
Measurement results confirm that writeability failures are
caused by Vth shifts induced by both random variations and
RTN. Writeability is measured by initializing a value in a
cell at a safe Vdd, writing the opposite value at the test
Vdd, then checking for a correct write at a safe Vdd. The
ability to write both values is measured for the entire array at
decreasing voltages. Figure 9 shows the Vth shifts of the first
12 failing cells with arrows indicating the Vth shift direction
The effect of RTN on dynamic writeability can be measured by applying two different write schemes with opposite
resting values that expose different RTN behaviour, as shown
in Figure 10 [6]. The dynamic write patterns are exactly the
same, so without RTN Vmin should be exactly the same. However, different resting values force different trap occupancy
immediately before the writeability test, which exposes the
effect of RTN on writeability. The difference in Vmin between
the single write (SW) mode and write-after-write (WAW) mode
will be referred to as Vdif f . This effect can cause problems
for production BIST tests at low voltage, because failures
at a specific voltage depend on trap occupancy. Therefore,
understanding Vdif f is required to accurately margin BIST
measurements of Vmin .
Figure 12 shows how RTN causes a Vmin difference
between the two write modes for writing a 1 to a specific
bitcell. Random-variation-induced Vth shift weakens the cell.
Alternating-bias RTN measurements show that when the PDL
is left off, it will have a higher current than when it is left on.
For the WAW mode, Figure 11 shows that the bitcell holds a
1 for a long period and the PDL is off, so RTN will cause
higher current and therefore lower Vth , which makes failure
in the WAW mode more likely than the SW mode.
The distribution of Vdif f values for the first 25 failing
cells in bulk and FDSOI is shown in Figure 13. Larger
Vmin differences in FDSOI suggest that while RTN ∆ID
amplitude is similar between FDSOI and bulk, the lower
standard deviation of the random variation in FDSOI increases
RTN’s impact on cell failures.
_
Init A
Taccess
_
Write A
Write A
Write after
Write (WAW) Init A
_
Write A
Write A
Single
Write (SW)
Taccess
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.00
Fig. 10: BIST waveforms of two different writeability tests
that expose RTN, where Tstress = 1s and Taccess = 300ns
with a 50% duty cycle.
ON
ON
OFF
OFF
1
0
ON
1
OFF
OFF
0.06
102
FDSOI
(No RTN)
(With RTN)
Chip: b7
b5
b2
0.75
Vdd (a.u.)
(With RTN)
101
0.90
100
0.60
Chip: f9
f7
f4
0.75
Vdd (a.u.)
0.90
Fig. 14: Difference in Vmin for six different chips.
OFF
0
1
0.05
(No RTN)
100
0.60
ON
ON
ON
1
ON
OFF
0
0.02 0.03 0.04
Vdiff (a.u.)
BULK
101
WAW: A=1
SW: A=1
OFF
0
Fail Bit Count
SW: A=0
0.01
Fig. 13: Distribution of Vmin difference between write modes.
102
WAW: A=0
OFF
BULK
FDSOI
Rel. Freq.
Tstress
VII.
ON
Fig. 11: Transistor stress state for different write modes and
values.
The effect of Vdif f on overall chip Vmin can be evaluated
by counting the number of cells that fail at each voltage for
both SW and WAW (no RTN effect) versus the number that fail
for either SW or WAW (including RTN). Figure 14 plots the
Vmin difference due to RTN for six different chips normalized
to the same voltage. Note that the effect of RTN is suppressed
for the entire array because the cells with the largest RTN
effect are not necessarily the cells that limit array Vmin .
C ONCLUSION
Measurement of transistor threshold voltage in 32,000 bitcells shows that FDSOI technology reduces threshold variation
due to random variations by 27% compared to bulk. The
alternating bias technique reveals similar threshold variation
due to RTN in bulk and FDSOI for NMOS devices, and slightly
increased RTN amplitude in FDSOI for PMOS devices. Dynamic measurement of writeability in both FDSOI and bulk
shows that the decreased random variation in FDSOI enables
an approximately 7% reduction in Vmin , but also exacerbates
the effect of RTN on minimum operating voltage failures,
suggesting that even as intrinsic channel devices reduce the
relative amount of random variation, RTN will emerge as an
obstacle to future voltage scaling and increase voltage margins
for BIST results.
ACKNOWLEDGEMENTS
∆ID (a.u.)
3.5
3.0
3
2
1
0
−1
−2
−3
Vth shift (σ)
Pfail
1.0
0.8
0.6
0.4 Write
0.2 A=1
0.0
0.700
0.725
Vdd (a.u.)
SW
WAW
0.750
SW
WAW
R EFERENCES
PDL PDR PGL PGR PUL PUR
×10−7
stress:
off
This work was partly funded by BWRC, ASPIRE, DARPA
PERFECT Award Number HR0011-12-2-0016, Intel ARO,
NVIDIA Fellowship, and fabrication donation by STMicroelectronics.
[1]
[2]
stress:
on
stress:
off
pul
pur
pgl
pgr
pdl
pdr
stress:
on
2.5
2.0
[3]
[4]
1.5
1.0
0.0
[5]
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Time (s)
[6]
Fig. 12: Example measured effect of RTN on Vdif f for a
specific bitcell.
H. Miki et al., “Statistical measurement of random telegraph noise and
its impact in scaled-down high-κ/metal-gate MOSFETs,” in IEDM, 2012,
pp. 19.1.1–19.1.4.
N. Planes et al., “28nm FDSOI technology platform for high-speed lowvoltage digital applications,” in VLSIT, 2012, pp. 133–134.
X. Deng et al., “Characterization of bit transistors in a functional SRAM,”
in VLSIC, 2008, pp. 44–45.
S. O. Toh, Y. Tsukamoto, Z. G. Guo, L. Jones, T.-J. King Liu, and
B. Nikolic, “Impact of random telegraph signals on Vmin in 45nm
SRAM,” in IEDM, 2009, pp. 1–4.
B. Zimmer et al., “SRAM Assist Techniques for Operation in a Wide
Voltage Range in 28-nm CMOS,” Circuits and Systems II: Express Briefs,
IEEE Transactions on, vol. 59, no. 12, pp. 853–857, 2012.
S. O. Toh, Z. Guo, T.-J. King Liu, and B. Nikolic, “Characterization of
dynamic SRAM stability in 45nm CMOS,” JSSC, vol. 46, no. 11, pp.
2702–2712, 2011.