LVDS I/Os
1 Features
2 General Description
•
•
Process: TSMC 0.18 µm
Up to 250 Mb/s (250 MHz clock) switching rate
•
Driver outputs in high impedance with powerdown
•
Connection enabled independently
•
Two modes:
Wipro-NewLogic’s LVDS interface (driver & receiver)
is based on the IEEE protocol.
The line driver and receiver are designed to support
data rates in excess of 250 Mb/s (250 MHz clock).
Two modes of operation are available: high and low
current modes.
High current mode is intended to cover the case
wherein physical connection between the RF chip
and the BB chip is made by a twisted pair (1 meter
max.). The RF chip and BB chip are located on
different boards. It conforms to the LVDS standard.
Low current mode is intended to cover the case
wherein the RF chip and the BB chip are located on
the same PCB. In this case, the drivers’ currents are
reduced by 2. The interface is therefore like a
“degraded LVDS”. The maximum distance on PCB
could be as high as 100 mm and distance skew
between the clock and other signal connections as
high as 50 mm.
LVDS uses a constant current mode driver.
Transmission line is terminated by an external load
resistor (which value is between 90 and 110 Ω).
When the driver is disconnected (tri-state mode or
powered off), the receiver output is maintained to low
voltage (fail-safe mode), preventing from switching
due to the noise on the line.
•
High current mode: +/-400 mV differential
swing (4 mA per connection)
•
Low current mode: +/-200 mV differential
swing (2 mA per connection)
•
+/-100 mV receiver threshold
•
Fail safe mode: the receiver output is maintained
to low voltage when inputs are undriven (open or
shorted)
•
PCB lines up to 100 mm long in low current
mode
•
Twisted pair connection up to 1 m long, using
CAT5e cable
•
3.3 V supply +/-10% and 1.8 V supply +/-10%
3 Block Diagram
Rint+
Tout+
Tin
Rload
Tx
Tout
Rint-
1/5
Rx
Rout
4 Electrical Specification
4.1
Absolute Maximum Ratings
Parameter
Temp range
4.2
4.3
Min
-30ºC
Typ
Max
+85ºC
Supply Voltages
Parameter
Vdd _12
Vdd _27
Min
1.08V
3.0V
Typ
1.2V
3.3V
Max
1.32V
3.6V
Parameter
Load
Clock
Clk Jitter
Min
90Ω
Typ
100Ω
240MHz
Max
110Ω
250MHz
80ps
Clock & Load
5 Layout Description
2/5
6 Line Driver Specifications - high current mode
6.1
DC Characteristics
Parameter
Differential output
voltage
Common mode voltage
Pin
Min.
Typ.
Max.
Unit
Conditions
VOD
+/-340
+/- 425
+/-510
mV
Loaded, RL = 100 Ω
VCM
1.125
1.2
1.275
V
Output voltage high
VOH
1.412
1.530
Output voltage low
VOL
0.870
Input voltage high
VIH
0.7×vdd
Input voltage low
VIL
Input capacitance
Output current
Output current
Cin
Ignd
Idiff
1.0
0.3×vdd
TBD
40
12
V
Single ended, RL=100 Ω
V
Single ended, RL=100 Ω
V
CMOS 1.2V 0.09µm
V
CMOS 1.2V 0.09µm
pF
mA
mA
Driver outputs shorted to ground
Driver outputs shorted together
2.5
µA
mA
Enable < 0.55V
2
5.5
6.8
mA
One driver, RL =100 Ω, 250MHz
Typ.
Max.
Unit
tPHLD
1
1.5
ns
Conditions
RLOAD=100Ω, CLOAD=0.2pF,
5mm PCB tracks
Differential delay low to
high
tPLHD
1
1.5
ns
RLOAD=100Ω, CLOAD=0.2pF,
5mm PCB tracks
Differential skew tPHLDtPLHD
tdiffskew
200
ps
RLOAD=100Ω, CLOAD=0.2pF,
5mm PCB tracks
Channel to channel
skew
tch2chskew
150
ps
RLOAD=100Ω, CLOAD=0.2pF,
5mm PCB tracks
Rise time (-200 to
+200mV)
tTLH
0.3
0.6
ns
RLOAD=100Ω, CLOAD=0.2pF,
5mm PCB tracks
Fall Time (-200 to
+200mV)
tTHL
0.3
0.6
ns
RLOAD=100Ω, CLOAD=0.2pF,
5mm PCB tracks
µs
ns
ns
Output Tri-State current
IOZ
Bias current (txbias)
Ibias
Driver current
Ireceiver
6.2
-10
+10
AC Characteristics
Parameter
Differential delay high
to low
Pin
Min.
Bias settling time
tBIAS
2
Tri-state disable time
Tri-state enable time
tOFF
tON
10
10
Txbias enable time
Driver disable time
Driver enable time
7 Line Driver Specifications - low current mode
7.1
DC Characteristics
Parameter
Differential output
voltage
Common mode voltage
Pin
Min.
Typ.
Max.
Unit
Conditions
VOD
+/-170
+/- 212
+/-255
mV
Loaded, RL = 100 Ω
VCM
1.125
1.2
1.275
V
Output voltage high
VOH
1.3
1.41
V
Single ended, RL=100 Ω
Output voltage low
VOL
1.0
V
Single ended, RL=100 Ω
Input voltage high
VIH
0.7×vdd
V
CMOS 1.2V 0.09µm
Input voltage low
VIL
V
CMOS 1.2V 0.09µm
Input capacitance
Output current
Output current
Cin
Ignd
Idiff
1.1
0.3×vdd
TBD
40
12
pF
mA
mA
Driver outputs shorted to ground
Driver outputs shorted together
Output Tri-State current
IOZ
Ibias
1.5
2.0
µA
mA
Enable < 0.55V
Bias current (txbias)
Driver current
Ireceiver
3.1
4
mA
One driver, RL =100 Ω, 250MHz
-10
+10
3/5
7.2
AC Characteristics
Parameter
Differential delay high
to low
Pin
Min.
Typ.
Max.
Unit
tPHLD
1
1.5
ns
Differential delay low to
high
tPLHD
1
1.5
ns
RLOAD=100Ω, CLOAD=0.2pF,
5mm PCB tracks
Differential skew tPHLDtPLHD
tdiffskew
200
ps
RLOAD=100Ω, CLOAD=0.2pF,
5mm PCB tracks
Channel to channel
skew
tch2chskew
150
ps
RLOAD=100Ω, CLOAD=0.2pF,
5mm PCB tracks
Rise time (-200 to
+200mV)
tTLH
0.3
0.6
ns
RLOAD=100Ω, CLOAD=0.2pF,
5mm PCB tracks
Fall Time (-200 to
+200mV)
tTHL
0.3
0.6
ns
RLOAD=100Ω, CLOAD=0.2pF,
5mm PCB tracks
µs
ns
ns
Bias settling time
tBIAS
2
Tri-state disable time
Tri-state enable time
tOFF
tON
10
10
Conditions
RLOAD=100Ω, CLOAD=0.2pF,
5mm PCB tracks
Txbias enable time
Driver disable time
Driver enable time
8 Line Receiver Specifications
8.1
DC Characteristics
Parameter
Differential input high
threshold
Differential input low
threshold
Common mode voltage
range
Input differential
hysteresis
Pin
Min.
Typ.
VTH
VTH
-100
VCM
0.9
Vhyst
25
Output Voltage High
VOH
0.9×vdd
Output Voltage Low
VOL
Input current
IOZ
Bias current (rxbias)
Receiver current
Differential input high
threshold
Differential input low
threshold
Common mode voltage
range
Ibias
Ireceiver
1.2
0.9
mV
Conditions
Common mode voltage
VCM=1.2V
Common mode voltage
VCM=1.2V
V
mV
V
CMOS 1.2V 0.09µm
0.1×vdd
V
CMOS 1.2V 0.09µm
+10
1.5
2.0
µA
mA
mA
+100
mV
VTH
VCM
+100
1.3
1.1
1.5
-100
Unit
mV
-10
VTH
Max.
mV
1.2
1.3
4/5
V
One receiver, 250MHz
Common mode voltage
VCM=1.2V
Common mode voltage
VCM=1.2V
8.2
AC Characteristics
Parameter
Differential delay high
to low
Differential delay low to
high
Differential skew tPHLDtPLHD
Channel to channel
skew
Rise time (25% to
75%)
Fall Time (25% to
75%)
Typ.
Max.
Unit
Conditions
tPHLD
Pin
Min.
1
1.5
ns
Load 0.1pF
tPLHD
1
1.5
ns
Load 0.1pF
tdiffskew
200
ps
Load 0.1pF
tch2chskew
150
ps
Load 0.1pF
tTLH
0.2
ns
Load 0.1pF
tTHL
0.2
ns
Load 0.1pF
Skew at Rx input
tskew
0.9
ns
Due to Driver differential skew and
transmission medium skew
Bias settling time
tBIAS
2
Disable time
tOFF
10
µs
ns
Rxbias enable time
Driver disable time
Contact
For more details about our products and
services, please visit us at www.newlogic.com
or www.wipro.com or contact us at:
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(a Wipro Company)
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Japan
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USA
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consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
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