74LVQ374
Low Voltage Octal D Flip-Flop with TRI-STATEÉ Outputs
General Description
Features
The LVQ374 is a high-speed, low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and
TRI-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all
flip-flops.
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Ideal for low power/low noise 3.3V applications
Implements patented Quiet Series EMI reduction
circuitry
Available in SOIC JEDEC, SOIC EIAJ and QSOP
packages
Guaranteed simultaneous switching noise level and dynamic threshold performance
Improved latch-up immunity
Guaranteed incident wave switching into 75X
4 kV minimum ESD immunity
Buffered positive edge-triggered clock
TRI-STATE outputs drive bus lines or buffer memory
address registers
MIL-STD-883 54ACQ Products are available for Military/Aerospace Applications
Logic Symbols
Connection Diagram
Pin Assignment for
SOIC and QSOP
IEEE/IEC
TL/F/11360–1
TL/F/11360 – 3
TL/F/11360 – 2
Pin Names
Description
D0 – D7
CP
OE
O 0 – O7
Data Inputs
Clock Pulse Input
TRI-STATE Output Enable Input
TRI-STATE Outputs
SOIC JEDEC
Order Number
SOIC EIAJ
SOIC JEDEC
74LVQ374SC
74LVQ374SJ
74LVQ374QSC
74LVQ374SCX 74LVQ374SJX 74LVQ374QSCX
See NS Package Number
M20B
M20D
MQA20
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C1996 National Semiconductor Corporation
TL/F/11360
RRD-B30M17/Printed in U. S. A.
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74LVQ374 Low Voltage Octal D Flip-Flop with TRI-STATE Outputs
October 1995
Functional Description
Truth Table
The LVQ374 consists of eight edge-triggered flip-flops with
individual D-type inputs and TRI-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With
the Output Enable (OE) LOW, the contents of the eight flipflops are available at the outputs. When the OE is HIGH, the
outputs go to the high impedance state. Operation of the
OE input does not affect the state of the flip-flops.
Inputs
Outputs
Dn
CP
OE
On
H
L
X
L
L
X
L
L
H
H
L
Z
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Z e High Impedance
L e LOW-to-HIGH Transition
Logic Diagram
TL/F/11360 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings (Note)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI e b0.5V
VI e VCC a 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO e b0.5V
VO e VCC a 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
(ICC or IGND)
Storage Temperature (TSTG)
DC Latch-Up Source or
Sink Current
Supply Voltage (VCC)
LVQ
Input Voltage (VI)
b 0.5V to a 7.0V
2.0V to 3.6V
0V to VCC
0V to VCC
Output Voltage (VO)
Operating Temperature (TA)
74LVQ
b 20 mA
a 20 mA
b 0.5V to VCC a 0.5V
b 40§ C to a 85§ C
Minimum Input Edge Rate (DV/Dt)
VIN from 0.8V to 2.0V
VCC @ 3.0V
b 20 mA
a 20 mA
125 mV/ns
b 0.5V to VCC a 0.5V
g 50 mA
g 400 mA
b 65§ C to a 150§ C
g 300 mA
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation .
DC Electrical Characteristics
Symbol
Parameter
VCC
(V)
74LVQ374
74LVQ374
TA e a 25§ C
TA e
b 40§ C to a 85§ C
Typ
Units
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
3.0
1.5
2.0
2.0
V
VOUT e 0.1V
or VCC b 0.1V
VIL
Maximum Low Level
Input Voltage
3.0
1.5
0.8
0.8
V
VOUT e 0.1V
or VCC b 0.1V
VOH
Minimum High Level
Output Voltage
3.0
2.99
2.9
2.9
V
IOUT e b50 mA
2.58
2.48
V
*VIN e VIL or VIH
IOH e b12 mA
0.1
0.1
V
IOUT e 50 mA
3.0
0.36
0.44
V
*VIN e VIL or VIH
IOL e 12 mA
3.6
g 0.1
g 1.0
mA
3.0
VOL
IIN
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
0.002
VI e VCC, GND
*All outputs loaded; thresholds on input associated with output under test.
3
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DC Electrical Characteristics
Symbol
Parameter
VCC
(V)
(Continued)
74LVQ374
74LVQ374
TA e a 25§ C
TA e
b 40§ C to a 85§ C
Typ
IOLD
² Minimum Dynamic
Output Current
IOHD
ICC
Maximum Quiescent
Supply Current
IOZ
Maximum TRI-STATE
Leakage Current
Units
Conditions
Guaranteed Limits
3.6
36
mA
VOLD e 0.8V Max
(Note 1)
3.6
b 25
mA
VOHD e 2.0V Min
(Note 1)
3.6
4.0
40.0
mA
3.6
g 0.25
g 2.5
mA
VOLP
Quiet Output
Maximum Dynamic VOL
3.3
0.5
0.8
V
VOLV
Quiet Output
Minimum Dynamic VOL
3.3
b 0.3
b 0.8
V
VIHD
Maximum High Level
Dynamic Input Voltage
3.3
1.7
2.0
V
VILD
Maximum Low Level
Dynamic Input Voltage
3.3
1.6
0.8
V
VIN e VCC or GND
VI(OE) e VIL, VIH
VI e VCC, GND
VO e VCC, GND
(Notes 2, 3)
(Notes 2, 3)
(Notes 2, 4)
(Notes 2, 4)
² Maximum test duration 2.0 ms, one output loaded at a time.
Note 1: Incident wave switching on transmission lines with impedances as low as 75X for commercial temperature range is guaranteed for 74LVQ.
Note 2: Worst case package.
Note 3: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND.
Note 4: Max number of Data Inputs (n) switching. (n b 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold
(VIHD), f e 1 MHz.
AC Electrical Characteristics
Symbol
Parameter
VCC
(V)
Min
74LVQ374
74LVQ374
TA e a 25§ C
CL e 50 pF
TA e b40§ C
to a 85§ C
CL e 50 pF
Typ
Max
Min
Units
Max
fmax
Maximum Clock Frequency
2.7
3.3 g 0.3
55
75
50
70
tPLH,
tPHL
Propagation Delay
CP to On
2.7
3.3 g 0.3
3.0
3.0
11.4
9.5
18.3
13.0
3.0
3.0
19.0
13.5
tPZL,
tPZH
Output Enable Time
2.7
3.3 g 0.3
3.0
3.0
11.4
9.5
18.3
13.0
3.0
3.0
19.0
13.5
ns
tPHZ,
tPLZ
Output Disable Time
2.7
3.3 g 0.3
1.0
1.0
11.4
9.5
20.4
14.5
1.0
1.0
21.0
15.0
ns
tOSHL,
tOSLH
Output to Output Skew*
CP to On
2.7
3.3 g 0.3
1.0
1.0
1.5
1.5
MHz
1.5
1.5
ns
ns
*Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification
applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design.
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4
AC Operating Requirements
74LVQ374
74LVQ374
TA e a 25§ C
CL e 50 pF
TA e b40§ C
to a 85§ C
CL e 50 pF
Symbol
Parameter
VCC
(V)
tS
Setup Time, HIGH or LOW
Dn to CP
2.7
3.3 g 0.3
0
0
4.0
3.0
4.5
3.0
ns
tH
Hold Time, HIGH or LOW
Dn to CP
2.7
3.3 g 0.3
0
0
1.5
1.5
1.5
1.5
ns
tW
CP Pulse Width,
HIGH or LOW
2.7
3.3 g 0.3
2.4
2.0
5.0
4.0
6.0
4.0
ns
Typ
Units
Guaranteed Minimum
Capacitance
Parameter
Typ
Units
Conditions
CIN
Symbol
Input Capacitance
4.5
pF
VCC e Open
CPD
(Note 1)
Power Dissipation
Capacitance
39
pF
VCC e 3.3V
Note 1: CPD is measured at 10 MHz.
74LVQ374 Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74LVQ
374
Temperature Range Family
74LVQ e Commercial
S
C
X
Special Variations
‘‘X’’ e Tape and Reel
‘‘ ’’ e Rail/Tube
Device Type
Package Code
S e (0.300× Wide) Molded Small Outline Package, JEDEC
SJ e (0.300× Wide) Molded Small Outline Package, EIAJ
QS e Shrink Small Outline Package, JEDEC
(also known as QSOP)
5
Temperature Range
C e Commercial (b40§ C to a 85§ C)
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead (0.300× Wide) Molded Small Outline Integrated Circuit, JEDEC
Order Number 74LVQ374SC or 74LVQ374SCX
NS Package Number M20B
20-Lead (0.300× Wide) Molded Small Outline Package, EIAJ
Order Number 74LVQ374SJ or 74LVQ374SJX
NS Package Number M20D
7
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74LVQ374 Low Voltage Octal D Flip-Flop with TRI-STATE Outputs
Physical Dimensions inches (Continued)
20-Lead (0.150× Wide) Molded Shrink Small Outline Package, JEDEC
(also known as QSOP)
Order Number 74LVQ374QSC or 74LVQ374QSCX
NS Package Number MQA20
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