PID Controller Design
for Arijit’s Proposed Biomedical Front-End
Satish Patil
Electrical Engineering, IIT Bombay
May 7, 2015
1
Requirement of PID controller
This report presents a design of Proportional-Derivative-Integral (PID) controller design for
EMI-immune architecture for the analog front end of biomedical signal [ECG (electrocardiogram), EEG (electroencephalogram) and EMG (electromyogram)] acquisition systems. The
proposed front end continuously measures variation of the mismatch between impedance of
the electrode-skin interface in the two electrodes, in real time even during acquisition of the
bio-electrical signal, and compensates for the same using a PID controller in the feedback
loop. The proposed front end effectively rejects the common-mode coupled EMI signals,
improves common mode rejection ratio (CMRR), reduces mismatch induced signal deterioration and in real time eliminates the effect of variation of sensor or electrode impedance
mismatches on the acquired signal. The role of PID controller in this design is important
as it uses output of low pass filter (which is effectively mismatch or induced EMI) as an
error signal to adjust the gain of the variable gain amplifier (VGA), which in turn controls
the differential current to compensate for the mismatch induced distortion. Effectively when
this loop stabilizes it continuously cancels out mismatch between skin-electrode and reject
any common mode signal.
2
PID Controller
The relation between input and output of PID controller is as given by following equation.
here, Kp , Ti and Td are PID control parameters.
1
Vout (s)
= Kp + Td s +
Vin (s)
Ti s
The purpose of individual control parameter is as mentioned below:
• Proportional : increases speed.
• Derivative : adds zero in transfer function so increases stability
1
(1)
Figure 1.1: EMI-immune, motion artifact compensated analog front-end for biomedical signal
acquisition (proposed by Arijit Karmakar)
Figure 2.1: Ideal voltage mode PID controller [Ref: Nagrath, I. J. Control systems engineering. New Age International, 2006.]
2
• Integral : adds pole at origin hence steady state error reduces.
• PID : combines all of the above three
The transfer function of OPAMP based PID controller can be written as,
hR R
R8
R8 R6 C2 s i
2 8
+
+
Vout = Vin
R1 R3 R5 R4 C1 s
R7
From above equation, PID control parameters can be extracted as,
R2 R8
Kp =
R1 R3
R5 R4 C1
Ti =
R8
R8 R6 C2
Td =
R7
2.1
(2)
(3a)
(3b)
(3c)
Practical Integrator and Differentiator
The ideal differentiator is inherently unstable in practice due to the presence of some high
frequency noise in every electronic system. An ideal differentiator would amplify this small
noise. To circumvent this problem, it is traditional to include a series resistor at the input and
a parallel capacitor across the feedback resistor, converting the differentiator to an integrator
at high frequencies for filtering. The transfer function of practical integrator is given by,
Vout
R2 /R3
=
Vin
1 + R2 C1 s
The cut off frequency is given by,
1
fLP F =
(4)
2πR2 C1
This frequency must be higher than operating signal frequency. In this design I considered
fLP F = 0.1Hz
In case of ideal integrator there is no path for current flow from inverting terminal to
output for extremely low (or DC) frequencies. Due some offset present between +ve and
-ve input terminals, OPAMP produces very large output which is equals to input times
open loop gain. in order to address this issue, a resistor connected in parallel with feedback
capacitor. The circuit of practical integrator and differentiator are shown in figure 2.2.
Rf
C2 s
Vout
=
×
Vin
(1 + Rf Cf s) (1 + R1 C2 s)
The cut off frequency is given by,
1
1
fHP F =
and fLP F =
2πR1 C2
2πRf Cf
(5)
where fHP F must be very less than and fLP F must be very greater that frequency of operation. In this design I considered fHP F = 10KHz and fLP F = 10KHz.
3
Figure 2.2: practical circuits of integrator and differentiator
2.2
Required Values of Kp , Ti and Td
From Arijit’s analysis, the requirement of PID control parameters are : Kp = 25, Ti = 1/8500
and Td = 0.001. Considering these requirements, values of passive components calculated
and tabulated in following table 2 NOTE: values are given according to figure 4.1
3
OPAMP Design
From OPAMP schematic shown in figure 2.1, the input to output gain equations can be
written as,
1
)
Av1 = gm1 (ro1 ||ro3 ||
gm5
where impedance seen by drain of M1 is appeared as multiplication factor of gm1 . Voltage
gain of second stage is,
Av2 = gm7 (ro7 ||ro10 )
We designed circuit such a way that maximum gain (ideally 60) is achieved by stage 2.
similarly gain of buffer stage is,
1
Av3 = gm13 (
)
gm12
From above equations, voltage gain of overall system is written as,
Av = gm1 (ro1 ||ro3 ||
1
gm5
) × gm7 (ro7 ||ro10 ) × gm13 (
4
1
gm12
)
(6)
Figure 3.1: Two-stage operational amplifier circuit schematic with buffered stage
While designing, gain of first stage is set to 10, while 60 and 4 are gain of second and third
stages respectively. So,
Av = 10 × 60 × 4 = 2400
3.1
Design flow:
From the schematic diagram shown in figure 2.1, we can see that circuit is symmetric.
This feature will be helpful in achieving low common mode gain and hence in turn high
common mode rejection ration (CMRR). As output resistance of M1 is totally decided by
gm 5 because this low resistance will come in parallel with ro1 and ro3 . hence we keep minimum
transconductance of M5. M3 is used as current source. As three mosfets are stacked we set
bias voltage of M11 to be 0.6 by setting bias current (Ibias ) of at 0.7mA. So aspect ratio of
M11 can be calculated as,
W 2ID
2 × 0.7m
=
=
= 259.26
L 11 µn Cox (VGS − VT )2
240µ(0.6 − 0.45)2
W ⇒
= 259.26
L 11
From this we can ensure that M1 and M3 are operated in saturation region. Because of
symmetry M1 and M2 will carry Ibias /2 that is 0.35mA each. Current flow in NMOS and
PMOS can be written as,
W
(VGS − VT )2
2L
W
ID = µp Cox (VSG − |VT |)2
2L
ID = µn Cox
5
(7a)
(7b)
As 0.9v common mode always will be present at both inputs of differential amplifier,
VG =0.9v. Using condition of saturation region which ensures saturation region operation as
VDS ≥ VGS − VT ⇒ VGD ≤ VT
As 0.6v is connected as gate of M13, minimum voltage at drain of M13 which will ensure
saturation region operation is 0.6-VT = 0.15v. So
VGS1,2 ≥ 0.75v
Considering boundary condition, we can find aspect ratio of M1 and M2 as
W L
=
1,2
2ID
2 × 0.35m
=
= 32.41
2
µn Cox (VGS − VT )
240µ(.75 − 0.45)2
⇒
W L
= 32.41
1,2
M5 and M6 are used only to provide low value of gm and to mirror very small i.e. 0.1% of
current flowing through M1, which will be mirrored into output stage. In order to fix current
through M3 and M4 we connected bias voltage Vb1 and connected to gate of M3 and M4.
The value of this bias voltage is chosen to be 1v. By knowing current and overdrive voltage
we can find aspect ratio from equation 3(b). hence, aspect ration of M3 can be found by,
W L
=
3,4
2ID
2 × 0.35m
=
= 60.15
2
µp Cox (VSG − |VT |)
93µ(1.0 − 0.45)2
⇒
W L
= 60.15
3,4
We keep same aspect ratio for M3 and M4. As explained in above paragraph, only 0.1% of
current flowing through M1 is mirrored into M5, IDM 5 =0.35µA.
Expected voltage gain of second stage is 60. As we chose transconductance in mA/V range,
we have to increase output impedance hence decrease output current. Current is already
decreased using mirroring action. Relation between output impedance and bias current is
given as
1
(8)
ro =
λID
considering λ = 0.2 for PMOS and ID = 0.35µ, output resistance can be found as,
ro7 =
1
= 14.286M Ω
0.2 × 0.35µ
Considering equal output resistance of M10 same as that of M7, effective output impedance
of stage 2 would be
Routstage2 = 7.143M Ω
6
As we set gain of stage 2 to 60, by knowing gain and output resistance, we can find transconductance using gain formula as,
gm =
60
Av
=
⇒ 8.4µA/V
Rout
7.143M Ω
(9)
The relation between overdrive voltage, bias current and transconductance we have
gm =
2ID
2ID
⇒ VGS − VT =
(VGS − VT )
gm
(10)
Using same relation for VGS of M7 and M8 is sound to be 0.533 volts. Aspect ratio of M7
and M8 can be found by using current equation as follows:
W L
=
7,8
1
(VSG
2
ID
− |VT |)2
Substituting values in above equations we get
⇒
W L
= 1.0926
7,8
As mentioned in above section aspect ratios of M7, M8 and M5, M6 are kept same in order
to achieve less common mode gain. Hence,
⇒
W L
= 1.0926
5,6
In order to match resistances of series connected NMOS and PMOS, we keep aspect ratio of
M9 and M10 as one third of M7 and M8.
W 1W ⇒
=
L 9,10 3 L 7,8
While designing third stage we must keep in mind that this is buffer stage and high gain can
not be achieved by this stage. Moreover drain voltage must be set to 0.9v i.e. Vdd /2 so that
nest stage can directly be coupled. Gain of this stage is,
Av3 = gm13 (
1
gm12
) and Rout ≈
1
gm12
As gain of this stage is fixed to 2, this means transconductance of M13 should be double
than that of M12.
gm13 = 2 × gm12
considering gm12 = 0.5mA/V and by knowing VGS = 0.9v we can find aspect ratio of M12 as
gm12 = µp Cox
W
(VGS − VT )2
L
7
W L
=
0.5m
= 21.94
93µ(0.9 − 0.45)2
hence,
W = 21.94
L 12
Aspect ratio of M13 should be 1/3 of aspect ratio of M12 in order to match resistances.
W L
3.2
= 7.31
13
Transistor Sizing
As per described in section 3.1, aspect ratios, theoretical and actual transistor sizes are
summarized in following table.
device
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
3.3
aspect
ratio
32.41
32.41
60.15
60.15
1.0926
1.0926
1.0926
1.0926
1.0
1.0
259.26
21.94
7.31
W/L(µm/µm)
calculated
11.67/0.36
11.67/0.36
21.65/0.36
21.65/0.36
0.393/0.36
0.393/0.36
0.393/0.36
0.393/0.36
0.36/0.36
0.36/0.36
46.67/0.18
15.79/0.72
5.26/0.72
W/L(µm/µm)
actual
12/0.36
12/0.36
43/0.36
43/0.36
1.5/0.36
1.5/0.36
1.5/0.36
1.5/0.36
0.5/0.36
0.5/0.36
60/0.18
7.11/0.72
40/0.72
Simulation Results
The above designed opamp is simulated using UMC180 design kit with 1.8 volt supply
voltage.
3.3.1
Gain and Phase Margin
AC Analysis is performed to estimate open loop gain of OPAMP and Phase Margin. the
results are attached below. In order to achieve better phase margin compensation capacitor
of 1pF is added from output node to gate of M13. From figure 3.2, following information is
extracted:
8
Figure 3.2: Open loop gain and phase plot of OPAMP showing low frequency gain of 67.86dB
and phase margin = 66.2 degree
9
• Open loop gain = 67.86dB
• Phase margin = -113.8+180 = 66.2 degree
• unity gain frequency (fT ) = 48.43 MHz
• -3dB frequency ≈ 20.148KHz
3.3.2
CMRR
AC Analysis is performed to estimate CMRR of OPAMP. the results are attached below:
From common mode gain plot shown in figure, CMRR can be found as,
Figure 3.3: Common mode gain and phase plot of OPAMP showing low frequency common
mode gain of 4.859dB
CM RR = 20 × log
A d
= 72.719dB
ACM
10
3.3.3
Output Resistance (Rout )
AC Analysis is performed to estimate output resistance of OPAMP. AC current source of
1mA is connected at output node. Output impedance is ratio of voltage measured at output
node to current injected into output node. Small signal input voltage is disconnected while
performing Output resistance simulation the results are attached below:
Figure 3.4: Output impedance of OPAMP
3.3.4
Power consumption
transient analysis is performed to estimate power consumption. It is observed that total
current in Vdd switches between -0.7mA to -1.05mA. So we can consider average current of
0.9mA. hence Average power consumptionof OPAMP designed is
P ower = Iavg × Vdd = 0.9mA × 1.8 = 1.72mW
4
PID Simulations
The final circuit of PID controller using practical integrator and capacitor is shown in the
figure 4.1. Generally, PID controller is kept in series with plant/system and global unity gain
feedback is provided. Here no feedback is implemented in order to test circuit operation. As
front end will have global feedback loop and PID controller will be connected in feedback
path. The values of each component are also presented in table 2.
11
Figure 4.1: practical voltage mode PID controller
Table 1: component values for required PID controller
component
value
R1
1k
R2
25k
R3
1k
R4
1k
C1
1nF
Rf
159.2M
R5
100k
C2
10nF
R9
1.5924k
R6
100k
Cf
159.24p
R7
1k
R8
1k
R
1k
12
4.1
Sine input transition
When sine input transition (input amplitude 40mv peak-peak, frequency 1000Hz) is given,
response of PID controller is recorded and as shown in figure 4.3. From figure it is clear that
response of ideal PID controller (which is implemented using ideal OPAMPs) and designed
controller is exactly same.
Figure 4.2: Sine response of PID controller when sine input excitation is applied (kp = 50,
ki = 1, kd = 10−3 )
4.2
Pulse input transition
When pulse input transition (input amplitude 40mv peak-peak, frequency 500Hz) is given,
response of PID controller is recorded and as shown in figure 4.3. Pulse input details are as
follows:
• voltage 1: 10µV
• voltage 2: −10µV
• pulse width: 4ms
• period: 8ms
• rise time: 100ps
• fall time: 100ps
13
• DC offset : 900mv
Figure 4.3: Pulse response of PID controller when pulse input excitation is applied (kp = 25,
ki = 10, kd = 10−3 )
4.3
Maximum peak overshoot
By observing pulse response of PID controller, damping has occured at rising and falling edge
of pulse input. The behaviour is shown in figures 4.4 and 4.5 respectively. The Maximum
peak overshoot is calculated using following relation:
% Max. Peak overshoot =
max. value - final value
× 100
final value
(11)
In this case % max. peak overshoot can be found as,
% Max. Peak overshoot =
4.4
4299µV
× 100 ⇒ 1.76%
244mv
Settling time
Generally in control systems, settling time is time required to reach input within certain
tolerance band. Usually it is considered 2% or 5% of final value. Settling time measured
is different for lo-high transition and high-low transition. It is recorded as settling time for
designed PID controller is around 7µs.
14
Figure 4.4: Pulse response of PID controller when sine input excitation is applied (kp = 25,
ki = 103 , kd = 10−3 )
Figure 4.5: Pulse response of PID controller showing settling time and maximum peak
overshoot (kp = 25, ki = 10, kd = 10−3 )
15
5
5.1
System details
Transfer function of system from mismatch to input of PID
As in Fig. 1, the differential voltage Vpn across the output nodes can derived by applying
KCL at nodes Vp and Vn . If there is no mismatch in the components of the proposed front
end (Fig. 4), the output of the unit measuring electrode-skin impedance mismatch, i.e. the
gain of the VGA would be zero. Then the differential output voltage Vpn is given by Eq.
(12).
Zin
× Vsig
(12)
vpn =
Zin + R + Rx
If there is a mismatch (∆R) between the electrode-skin impedance, the differential output
voltage Vpn would be given by Eq. (13) (considering Gsh((R + Rx )||Zin ) 1)
Vpn
Zin
∆R − 2Gv Rx (R + Rx )
Iinj
=
×
× Vref +
− Vcmemi)
R + Rx R + ∆R + Rx + Zin (1 + Gv Rx )
Gsh
R + Rx
Zin (1 + 2Gv Rx )
+
×
× Vsig
R + ∆R + Rx R + ∆R + Rx + Zin (1 + Gv Rx )
(13)
Here Gv = Av ×Gm can be derived as a function of mismatch (∆R) and angular frequency
(ωi ) of the injected current Iinj . The signal proportional to Iinj is extracted using BPF
(Hbp (s)) and is given by Eq. (14)
Vbp (jωi ) =
∆R − 2Gv Rx (R + Rx )
Zin
×
Gsh (R + Rx ) R + ∆R + Rx + Zin (1 + Gv Rx )
× |Hbd (jωi )|.|Iinj | × sin(ωi t + 6 Hbp (jωi ))
(14)
It is then mixed with a sinusoidal voltage Vmix with angular frequency same as that of Iinj
but with a phase difference of φ . If the gain of the mixer is k then the output of the mixer
is given by Eq. (15):
Vmixer =
kZin
∆R − 2Gv Rx (R + Rx )
× |Hbp (jωi )|
×
2Gsh (R + Rx ) R + ∆R + Rx + Zin (1 + Gv Rx )
× |Iinj | × |Vmix | × (cos(φ − 6 Hbp (jωi )) − cos(2ωi t + φ + 6 Hbp (jωi )))
(15)
The low pass filter (Hlp (s)) passes only the low frequency component, and it is specified by
Eq.(16).
Vlp =
kZin
∆R − 2Gv Rx (R + Rx )
×
× |Hbp (jωi )|
2Gsh (R + Rx ) R + ∆R + Rx + Zin (1 + Gv Rx )
× |Hlp (jωi )| × |Iinj | × |Vmix | × (cos(φ − 6 Hbp (jωi )))
(16)
Hlp (jωi ) acts as an error signal to the PID controller, which adjusts the gain (Av ) of
VGA. Now since Gv = Av × Gm , Gv can be expressed as a function of ∆R and the angular
frequency ωi of the injected current Iinj . Gv is given by Eq. (17).
16
Gv = Gm
dVlp (jωi )
+ ki
kp Vlp (jωi ) + kd
dt
Z
Vlp (jωi )dt
(17)
where kp , kd and ki are proportional, differential and integral constants respectively (Eq.
()). Now as mismatch (∆R) changes, the error as specified by Eq. () i.e. (∆R − 2Gv Rx (R +
Rx ))) becomes nonzero and the PID controller adjusts the gain of the VGA such that the
error goes to zero. Then all the common mode signals corresponding to Vref , Iinj and Vcm(emi)
are eliminated and can not affect the actual bio-potential signal Vsig .
5.2
Testbench
figure 4.6 and 4.7 shows mismatch between electrode-skin impedance and output voltage of
all the blocks connected in feedback loop. It is been confirmed that input applied to PID
controller is very low frequency signal with f3dB = 20Hz. So similar test-bench is created
in order to observe input-output waveforms of designed PID block. It is been observed that
phase shift occurred in actual and ideal (block level) simulation is different and hence exact
cancellation is not observed. In order to achieve exact cancellation of mismatch, tuning of
PID controller is very important.
Figure 5.1: waveforms of resistance mismatch as a function of time and differential output
voltage vpn
17
Figure 5.2: waveforms of intermediate nodes of system
References
1. J.-M. Redoute and M. Steyaert, ”An instrumentation amplifier input circuit with a
high immunity to emi,” in International Symposium on Electromagnetic Compatibility
- EMC Europe, 2008, pp. 1-6, Sept 2008.
2. F. Michel and M. Steyaert, ”Differential input topologies with immunity to electromagnetic interference,” in Proceedings of the ESSCIRC, 2011, pp. 203-206, Sept 2011.
3. E. Compagne, S. Maulet, and S. Genevey, ”An analog front-end for remote sensor
applications with high input common-mode rejection including a 16bit sigma-delta
adc in 0.35 µm 3.3 V cmos process,” in Proceeding of the 30th European, Solid-State
Circuits Conference, ESSCIRC 2004,pp. 459-462, Sept 2004.
4. Nagrath, I. J. Control systems engineering. New Age International, 2006.
5. Surakampontorn, Wanlop, et al. ”Accurate CMOS-based current conveyors.” Instrumentation and Measurement, IEEE Transactions on 40.4 (1991): 699-702.
6. Yuce, Erkan, and Shahram Minaei. ”New CCII-based versatile structure for realizing
PID controller and instrumentation amplifier.” Microelectronics Journal 41.5 (2010):
311-316.
7. Yuce, Erkan, et al. ”CCII-based PID controllers employing grounded passive components.” AEU-International Journal of Electronics and Communications 60.5 (2006):
18
399-403.
8. Minaei, Shahram, et al. ”Simple realizations of current-mode and voltage-mode PID,
PI and PD controllers.” (2005).
19