LTC2274
16-Bit, 105Msps Serial
Output ADC
FEATURES
DESCRIPTION
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The LTC®2274 is a 105Msps, 16-bit A/D converter with
a high speed serial interface. It is designed for digitizing
high frequency, wide dynamic range signals with an input
bandwidth of 700MHz. The input range of the ADC can
be optimized using the PGA front end. The output data is
serialized according to the JEDEC Serial Interface for Data
Converters specification (JESD204).
High Speed Serial Interface (JESD204)
Sample Rate: 105Msps
77.7dBFS Noise Floor
100dB SFDR
SFDR >82dB at 250MHz (1.5VP-P Input Range)
PGA Front End (2.25VP-P or 1.5VP-P Input Range)
700MHz Full Power Bandwidth S/H
Optional Internal Dither
Single 3.3V Supply
Power Dissipation: 1300mW
Clock Duty Cycle Stabilizer
Pin Compatible Family
105Msps: LTC2274
80Msps: LTC2273
65Msps: LTC2272
40-Pin 6mm × 6mm QFN Package
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The LTC2274 is perfect for demanding applications where
it is desirable to isolate the sensitive analog circuits from
the noisy digital logic. The AC performance includes a
77.7dB Noise Floor and 100dB spurious free dynamic range
(SFDR). Ultra low internal jitter of 80fs RMS allows undersampling of high input frequencies with excellent noise
performance. Maximum DC specs include ±4.5LSB INL
and ±1LSB DNL (no missing codes) over temperature.
The encode clock inputs, ENC+ and ENC–, may be driven
differentially or single-ended with a sine wave, PECL,
LVDS, TTL or CMOS inputs. A clock duty cycle stabilizer
allows high performance at full speed with a wide range
of clock duty cycles.
APPLICATIONS
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Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Imaging Systems
ATE
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L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
3.3V
SENSE
VCM
1.25V
COMMON MODE
BIAS VOLTAGE
FAM
128k Point FFT, fIN = 4.93MHz,
–1dBFS, PGA = 0
SYNC+
INTERNAL ADC
REFERENCE
GENERATOR
SYNC–
8B/10B
ENCODER
OVDD
ASIC OR FPGA
1.2V TO 3.3V
2.2μF
16
50Ω
0.1μF
20
AIN +
CMLOUT+
+
ANALOG
INPUT
AIN –
16-BIT
PIPELINED
ADC CORE
S/H
AMP
–
AMPLITUDE (dBFS)
50Ω
+
SERIAL
RECEIVER
SERIALIZER
CORRECTION
LOGIC
–
CMLOUT–
CLOCK
CLOCK/DUTY
CYCLE
CONTROL
ENC+
ENC– PGA DITH MSBINV SHDN
SCRAMBLER/
PATTERN
GENERATOR
VDD
20X
PLL
GND
3.3V
0.1μF
0.1μF
2274 TA01
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
10
20
30
40
FREQUENCY (MHz)
50
2274 TA01b
PAT1 PAT0 SCRAM SRR1 SRR0
2274fb
1
LTC2274
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
OVDD = VDD (Notes 1, 2)
FAM
PAT0
PAT1
SCRAM
PGA
MSBINV
GND
SENSE
GND
Supply Voltage (VDD) ................................... –0.3V to 4V
Analog Input Voltage (Note 3) .......–0.3V to (VDD + 0.3V)
Digital Input Voltage......................–0.3V to (VDD + 0.3V)
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Power Dissipation .............................................2000mW
Operating Temperature Range
LTC2274C ................................................ 0°C to 70°C
LTC2274I.............................................. –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
Digital Output Supply Voltage (OVDD) .......... –0.3V to 4V
VCM
TOP VIEW
40 39 38 37 36 35 34 33 32 31
VDD 1
30 GND
VDD 2
29 SYNC–
GND 3
28 SYNC+
AIN+ 4
27 GND
AIN– 5
26 GND
41
GND 6
25 OVDD
GND 7
24 CMLOUT+
GND 8
23 CMLOUT–
ENC+ 9
22 OVDD
ENC– 10
21 GND
SHDN
SHDN
SRR1
SRR0
ISMODE
DITH
GND
VDD
VDD
GND
11 12 13 14 15 16 17 18 19 20
UJ PACKAGE
40-LEAD (6mm s 6mm) PLASTIC QFN
TJMAX = 150°C, θJA = 22°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2274CUJ#PBF
LTC2274CUJ#TRPBF
LTC2274UJ
40-Lead (6mm × 6mm) Plastic QFN
0°C to 70°C
LTC2274IUJ#PBF
LTC2274IUJ#TRPBF
LTC2274UJ
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 85°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2274CUJ
LTC2274CUJ#TR
LTC2274UJ
40-Lead (6mm × 6mm) Plastic QFN
0°C to 70°C
LTC2274IUJ
LTC2274IUJ#TR
LTC2274UJ
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
CONDITIONS
Integral Linearity Error
Differential Analog Input (Note 5) TA = 25°C
MIN
TYP
MAX
±1.2
±4
UNITS
LSB
Integral Linearity Error
Differential Analog Input (Note 5)
l
±1.5
±4.5
LSB
Differential Linearity Error
Differential Analog Input
l
±0.3
±1
LSB
Offset Error
(Note 6)
l
±1
±8.5
mV
Offset Drift
±10
Gain Error
External Reference
Full-Scale Drift
Internal Reference
External Reference
Transition Noise
l
±0.2
μV/°C
±1.5
%FS
±30
±15
ppm/°C
ppm/°C
3
LSBRMS
2274fb
2
LTC2274
ANALOG INPUT
The l denotes denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
VIN
Analog Input Range (AIN+ – AIN–)
CONDITIONS
3.135V ≤ VDD ≤ 3.465V
l
MIN
VIN, CM
Analog Input Common Mode
Differential Input (Note 7)
l
1
IIN
Analog Input Leakage Current
0V ≤ AIN+, AIN– ≤ VDD (Note 10)
l
ISENSE
SENSE Input Leakage Current
0V ≤ SENSE ≤ VDD (Note 11)
CIN
Analog Input Capacitance
Sample Mode ENC+ < ENC–
Hold Mode ENC+ > ENC–
tAP
TYP
MAX
UNITS
1.5 or 2.25
1.25
VP-P
1.5
V
–1
1
μA
–3
3
μA
6.7
1.8
pF
pF
Sample-and-Hold
Acquisition Delay Time
1
ns
tJITTER
Sample-and-Hold
Acquisition Delay Time Jitter
80
fsRMS
CMRR
Analog Input
Common Mode Rejection Ratio
1V < (AIN+ = AIN–) <1.5V
80
dB
BW-3dB
Full Power Bandwidth
RS ≤ 25Ω
700
MHz
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
SNR
Signal-to-Noise Ratio
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
MIN
UNITS
dBFS
dBFS
77.5
77.2
75.3
dBFS
dBFS
dBFS
77.2
75.1
dBFS
dBFS
76.3
74.5
74.2
dBFS
dBFS
dBFS
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
75.9
74.3
dBFS
dBFS
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
100
100
dBc
dBc
95
95
100
dBc
dBc
dBc
86
94
dBc
dBc
85
90
89
dBc
dBc
dBc
80
85
dBc
dBc
l
76.5
76.2
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1), TA = 25°C
140MHz Input (1.5V Range, PGA = 1)
Spurious Free Dynamic Range
2nd or 3rd Harmonic
MAX
77.6
75.4
15MHz Input (2.25V Range, PGA = 0), TA = 25°C
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
SFDR
TYP
15MHz Input (2.25V Range, PGA = 0), TA = 25°C
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
l
l
73.8
73.4
85
84
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1), TA = 25°C
140MHz Input (1.5V Range, PGA = 1)
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
l
81
80
2274fb
3
LTC2274
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS unless otherwise noted. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
SFDR
Spurious Free Dynamic Range 4th
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
Harmonic or Higher
MIN
100
100
dBc
dBc
100
100
dBc
dBc
95
100
dBc
dBc
90
95
dBc
dBc
77.5
75.3
dBFS
dBFS
77.4
77
75.2
dBFS
dBFS
dBFS
76.7
74.2
dBFS
dBFS
75.3
74.3
74
dBFS
dBFS
dBFS
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
73.4
73.4
dBFS
dBFS
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
105
105
dBFS
dBFS
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
105
105
dBFS
dBFS
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
105
105
dBFS
dBFS
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
100
100
dBFS
dBFS
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
100
100
dBFS
dBFS
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
115
115
dBFS
dBFS
115
115
dBFS
dBFS
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
115
115
dBFS
dBFS
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
110
110
dBFS
dBFS
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
105
105
dBFS
dBFS
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
l
90
l
85
170MHz Input (2.25V Range, PGA = 0)
170MHz Input (1.5V Range, PGA = 1)
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
15MHz Input (2.25V Range, PGA = 0), TA = 25°C
15MHz Input (2.25V Range, PGA = 0
15MHz Input (1.5V Range, PGA = 1)
l
76.3
75.9
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
140MHz Input (2.25V Range, PGA = 0), TA = 25°C
140MHz Input (1.5V Range, PGA = 1)
140MHz Input (1.5V Range, PGA = 1)
SFDR
SFDR
Spurious Free Dynamic Range
at –25dBFS Dither “OFF”
Spurious Free Dynamic Range
at –25dBFS Dither “ON”
UNITS
dBc
dBc
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
Signal-to-Noise
Plus Distortion Ratio
MAX
100
100
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
S/(N+D)
TYP
15MHz Input (2.25V Range, PGA = 0)
15MHz Input (1.5V Range, PGA = 1)
l
l
73.6
73.2
97
2274fb
4
LTC2274
COMMON MODE BIAS CHARACTERISTICS
The l denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCM Output Voltage
IOUT = 0
1.15
1.25
1.35
V
VCM Output Tempco
IOUT = 0
l
40
ppm/°C
VCM Line Regulation
3.135V ≤ VDD ≤ 3.465V
l
1
mV/V
VCM Output Resistance
–1mA ≤ | IOUT | ≤ 1mA
l
2
Ω
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Encode Inputs (ENC+, ENC–)
VID
Differential Input Voltage
(Note 7)
VICM
Common Mode Input Voltage
Internally Set
Externally Set (Note 7)
RIN
Input Resistance
CIN
Input Capacitance
l
0.2
V
1.6
1.4
(See Figure 2)
V
3.0
6
kΩ
3
pF
SYNC Inputs (SYNC+, SYNC–)
VSID
SYNC Differential Input
Voltage
(Note 7)
VSICM
SYNC Common Mode Input
Voltage
Internally Set
Externally Set (Note 7)
l
0.2
V
1.6
1.1
V
2.2
RSIN
SYNC Input Resistance
16.5
kΩ
CSIN
SYNC Input Capacitance
3
pF
Logic Inputs (DITH, PGA, MSBINV, SCRAM, FAM, SHDN, SRR1, SRR0, ISMODE, PAT1, PAT0)
VIH
High Level Input Voltage
VDD = 3.3V
l
VIL
Low Level Input Voltage
VDD = 3.3V
l
VIN = 0V to VDD
l
IIN
Input Current
CIN
Input Capacitance
2
V
0.8
V
±20
μA
1.5
pF
High-Speed Serial Outputs (CMLOUT+, CMLOUT–)
VOH
Output High Level
Directly-Coupled 50Ω to OVDD
Directly-Coupled 100Ω Differential
AC-Coupled
OVDD
OVDD – 0.2
OVDD – 0.2
V
V
V
VOL
Output Low Level
Directly-Coupled 50Ω to OVDD
Directly-Coupled 100Ω Differential
AC-Coupled
OVDD – 0.4
OVDD – 0.6
OVDD – 0.6
V
V
V
VOCM
Output Common Mode
Voltage
Directly-Coupled 50Ω to OVDD
Directly-Coupled 100Ω Differential
AC-Coupled
OVDD – 0.2
OVDD – 0.4
OVDD – 0.4
V
V
V
ROUT
Output Resistance
Single-Ended Differential
l
35
50
100
65
Ω
Ω
2274fb
5
LTC2274
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER
CONDITIONS
l
VDD
Analog Supply Voltage
PSHDN
Shutdown Power
SHDN Pins = VDD
OVDD
Output Supply Range
CMLOUT Directly-Coupled 50Ω to OVDD (Note 7)
CMLOUT Directly-Coupled 100Ω Differential (Note 7)
CMLOUT AC-Coupled (Note 7)
l
l
l
IVDD
Analog Supply Current
DC Input
l
IOVDD
Output Supply Current
CMLOUT Directly-Coupled, 50Ω to 0VDD
CMLOUT Directly-Coupled 100Ω Differential
CMLOUT AC-Coupled
PDIS
Power Dissipation
DC Input
MIN
TYP
MAX
UNITS
3.135
3.3
3.465
V
5
1.2
1.4
1.4
394
mW
VDD
VDD
VDD
V
V
V
450
mA
8
16
16
l
1300
mA
mA
mA
1485
mW
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
l
(Note 9)
TYP
20
MAX
UNITS
105
MHz
fS
Sampling Frequency
tCONV
Conversion Period
tL
ENC Clock Low Time
(Note 7)
l
3.1
4.762
25
ns
tH
ENC Clock High Time
(Note 7)
l
3.1
4.762
25
ns
tAP
Sample-and-Hold Aperture Delay
tBIT, UI
Period of a Serial Bit
tJIT
Total Jitter of CMLOUT± (P-P)
tR, tF
Differential Rise and Fall Time of CMLOUT± (20% to 80%) RTERM = 50Ω, CL = 2pF
(Note 7)
l
50
tSU
SYNC to ENC Clock Setup Time
(Note 7)
l
2
tHD
ENC Clock to SYNC Hold Time
(Note 7)
l
2.5
tCS
ENC Clock to SYNC Delay
(Note 7)
l
tHD
LATP
Pipeline Latency
9
Cycles
LATSC
Latency from SYNC Active to COMMA Out
3
Cycles
LATSD
Latency from SYNC Release to DATA Out
2
Cycles
1/fS
BER = 1E–12 (Note 7)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND (unless otherwise
noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3.3V, fSAMPLE = 105MHz differential ENC+/ENC– = 2VP-P sine
wave with 1.6V common mode, input range = 2.25VP-P with differential
drive (PGA = 0), unless otherwise specified.
Note 5: Integral nonlinearity is defined as the deviation of a code from
a “best fit straight line” to the transfer curve. The deviation is measured
from the center of the quantization band.
s
0.7
ns
tCONV/20
s
l
0.35
110
UI
ps
ns
ns
tCONV – tSU
ns
Note 6: Offset error is the offset voltage measured from –1/2LSB when the
output code flickers between 0000 0000 0000 0000 and 1111 1111 1111
1111 in 2’s complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3.3V, fSAMPLE = 105MHz input range = 2.25VP-P with
differential drive.
Note 9: Recommended operating conditions.
Note 10: The dynamic current of the switched capacitors analog inputs
can be large compared to the leakage current and will vary with the sample
rate.
Note 11: Leakage current will have higher transient current at power up.
Keep drive resistance at or below 1k.
2274fb
6
LTC2274
TIMING DIAGRAMS
tAP
ANALOG INPUT
N+9
N+2
N+1
N
N + 10
N+8
tCONV
ENC+
tH
tL
INTERNAL
PARALLEL DATA
N–6
N–5
N–4
N+3
N+4
INTERNAL
8B/10B DATA
N–9
N–8
N–7
N
N+1
LATP
tBIT
CMLOUT+/CMLOUT–
N – 10
N–9
N–8
N–1
N
2274 TD01
Analog Input to Serial Data Out Timing
tCONV
ANALOG INPUT
N+3
N
N–1
N+2
N+1
tHD
N+4
N+5
tSU
ENC+
tCS(MIN)
SYNC+
LATSC
tCS(MAX)
CMLOUT+/CMLOUT–
N – 10
N–9
N–7
N–8
K28.5 (x2)
K28.5 (x2)
2274 TD02
SYNC+ Falling Edge to Comma (K28.5) Timing
tCONV
ANALOG INPUT
N+3
N
N–1
N+2
N+1
tHD
N+4
tSU
ENC+
tCS(MIN)
SYNC+
LATSD
tCS(MAX)
CMLOUT+/CMLOUT–
K28.5 (x2)
K28.5 (x2)
K28.5 (x2)
N–7
N–6
2274 TD03
SYNC+ Rising Edge to Data Timing
2274fb
7
LTC2274
TYPICAL PERFORMANCE CHARACTERISTICS
unless otherwise noted.
Integral Non-Linearity (INL)
vs Output Code
Differential Non-Linearity (DNL)
vs Output Code
10000
1.5
0.8
9000
0.6
8000
0.4
7000
0.2
6000
DNL ERROR (LSB)
0.0
–0.5
–1.5
–2.0
0
16384
32768
49152
OUTPUT CODE
0.0
4000
–0.4
3000
–0.6
2000
–0.8
1000
–1.0
65536
0
16384
32768
49152
OUTPUT CODE
2274 G01
10
20
30
40
FREQUENCY (MHz)
50
0
10
20
30
40
FREQUENCY (MHz)
50
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
140
130
130
120
120
110
110
SFDR (dBc AND dBFS)
140
80
70
60
90
80
70
60
50
40
40
0
2274 G07
20
30
40
FREQUENCY (MHz)
50
64k Point 2-Tone FFT,
fIN = 14.2MHz and 15.8MHz,
–7dBFS, PGA = 0
100
50
30
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
10
2274 G06
SFDR vs Input Level, fIN =
15MHz, PGA = 0, Dither “On”
90
0
2274 G05
SFDR vs Input Level, fIN =
15MHz, PGA = 0, Dither “Off”
32807
64k Point FFT, fIN = 14.8MHz,
–10dBFS, PGA = 0
AMPLITUDE (dBFS)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
2274 G04
100
32787
32797
OUTPUT CODE
2274 G03
64k Point FFT, fIN = 14.8MHz,
–1dBFS, PGA = 0
AMPLITUDE (dBFS)
0
0
32777
65536
2274 G02
128k Point FFT, fIN = 4.93MHz,
–1dBFS, PGA = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
5000
–0.2
AMPLITUDE (dBFS)
INL ERROR (LSB)
0.5
COUNT
1.0
–1.0
AMPLITUDE (dBFS)
AC Grounded Input Histogram
2.0
1.0
SFDR (dBc AND dBFS)
VDD = 3.3V, OVDD = 1.5V, TA = 25°C, FS = 105Msps,
30
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
2274 G08
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
10
20
30
40
FREQUENCY (MHz)
50
2274 G09
2274fb
8
LTC2274
TYPICAL PERFORMANCE CHARACTERISTICS
unless otherwise noted.
0
10
20
30
40
FREQUENCY (MHz)
50
AMPLITUDE (dBFS)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
10
20
30
40
FREQUENCY (MHz)
2274 G10
10
20
30
40
FREQUENCY (MHz)
50
0
10
20
30
40
FREQUENCY (MHz)
140
140
130
130
120
120
110
110
SFDR (dBc AND dBFS)
SFDR (dBc AND dBFS)
50
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
70
60
90
80
70
60
50
40
40
30
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
2274 G16
0
10
20
30
40
FREQUENCY (MHz)
50
64k Point FFT, fIN = 170.2MHz,
–1dBFS, PGA = 1
100
50
50
2274 G15
SFDR vs Input Level,
fIN = 140MHz, PGA = 1,
Dither “On”
80
20
30
40
FREQUENCY (MHz)
2274 G14
SFDR vs Input Level,
fIN = 140MHz, PGA = 1,
Dither “Off”
90
10
64k Point FFT, fIN = 140.2MHz,
–1dBFS, PGA = 1
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
2274 G13
100
0
2274 G12
128k Point FFT, fIN = 70.1MHz,
–20dBFS, PGA = 0, Dither “On”
AMPLITUDE (dBFS)
0
50
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
2274 G11
128k Point FFT, fIN = 70.1MHz,
–20dBFS, PGA = 0, Dither “Off”
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
64k FFT, fIN = 70.1MHz, –1dBFS,
PGA = 1
AMPLITUDE (dBFS)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
64k FFT, fIN = 70.1MHz, –1dBFS,
PGA = 0
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
64k Point 2-Tone FFT,
fIN = 14.2MHz and 15.8MHz,
–15dBFS, PGA = 0
VDD = 3.3V, OVDD = 1.5V, TA = 25°C, FS = 105Msps,
30
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
2274 G17
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
10
20
30
40
FREQUENCY (MHz)
50
2274 G18
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9
LTC2274
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 3.3V, OVDD = 1.5V, TA = 25°C, FS = 105Msps,
unless otherwise noted.
SNR vs Input Frequency
105
78
100
76
PGA = 0
95
74
90
SNR (dBFS)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
SFDR (HD2 and HD3) vs
Input Frequency
SFDR (dBc)
AMPLITUDE (dBFS)
64k Point FFT, fIN = 250.2MHz,
–1dBFS, PGA = 1
PGA = 1
85
80
PGA = 0
66
70
10
20
30
40
FREQUENCY (MHz)
65
50
64
0
100
200
300
400
INPUT FREQUENCY (MHz)
500
2274 G19
100
200
300
400
INPUT FREQUENCY (MHz)
2274 G21
110
105
105
SFDR
SFDR
SNR AND SFDR (dBFS)
100
95
LIMIT
90
85
SNR
80
100
95
LOWER LIMIT
UPPER LIMIT
90
85
80
SNR
75
75
20
40
60
80
100
SAMPLE RATE (Msps)
70
2.8
120
3.0
3.2
SUPPLY VOLTAGE (V)
SFDR vs Analog Input
Common Mode Voltage, 5MHz
and 70MHz, –1dBFS
IVDD vs Sample Rate, 5MHz Sine,
–1dBFS
110
105
5MHz
100
95
IVDD (mA)
90
85
80
3.4
2274 G23
2274 G22
SFDR (dBc)
500
SNR and SFDR vs Supply Voltage
(VDD), fIN = 5.2MHz
110
70
0
2274 G20
SNR and SFDR vs Sample Rate,
fIN = 5.1MHz
SNR (dBFS) AND SFDR (dBC)
PGA = 1
70
68
75
0
72
70MHz
75
70
65
60
0.50 0.75 1.00 1.25 1.50 1.75 2.00
ANALOG INPUT COMMON MODE VOLTAGE (V)
2274 G02
420
410
400
390
380
370
360
350
340
330
320
310
300
290
0
40
80
SAMPLE RATE (Msps)
120
2274 G25
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10
LTC2274
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 3.3V, OVDD = 1.5V, TA = 25°C, FS = 105Msps,
unless otherwise noted.
CMLOUT Dual-Dirac BER
Bathtub Curve, 1.2Gbps
1.0E+00
1.0E+00
1.0E–02
1.0E–02
BIT ERROR RATE (BER)
BIT ERROR RATE (BER)
CMLOUT Dual-Dirac BER
Bathtub Curve, 400Mbps
1.0E–04
1.0E–06
1.0E–08
1.0E–10
1.0E–12
1.0E–14
1.0E–04
1.0E–06
1.0E–08
1.0E–10
1.0E–12
0
0.2
0.4
0.6
0.8
UNIT INTERVAL (UI)
1.0
1.0E–14
0
0.2
0.4
0.6
0.8
UNIT INTERVAL (UI)
2274 G26
1.0
2274 G27
CMLOUT Dual-Dirac BER
Bathtub Curve, 2.1Gbps
CMLOUT Eye Diagram 400Mbps
1.0E+00
BIT ERROR RATE (BER)
1.0E–02
1.0E–04
100mV/DIV
1.0E–06
1.0E–08
1.0E–10
416.7ps/DIV
2274 G29
1.0E–12
1.0E–14
0
0.2
0.4
0.6
0.8
UNIT INTERVAL (UI)
1.0
2274 G28
CMLOUT Eye Diagram 1.2Gbps
100mV/DIV
CMLOUT Eye Diagram 2.1Gbps
100mV/DIV
138.9ps/DIV
2274 G30
79.4ps/DIV
2274 G31
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11
LTC2274
PIN FUNCTIONS
VDD (Pins 1, 2, 12, 13 ): Analog 3.3V Supply. Bypass to
GND with 0.1μF ceramic chip capacitors.
GND (Pins 3, 6, 7, 8, 11, 14, 21, 26, 27, 30, 37, 40):
ADC Power Ground.
AIN+ (Pin 4): Positive Differential Analog Input.
AIN
– (Pin 5): Negative Differential Analog Input.
ENC+
(Pin 9): Positive Differential Encode Input. The
sampled analog input is held on the rising edge of ENC+.
This pin is internally biased to 1.6V through a 6.2kΩ resistor.
Output data can be latched on the falling edge of ENC+.
ENC– (Pin 10): Negative Differential Encode Input. The
sampled analog input is held on the falling edge of ENC-.
This pin is internally biased to 1.6V through a 6.2kΩ
resistor. Bypass to ground with a 0.1uF capacitor for a
single-ended Encode signal.
DITH (Pin 15): Internal Dither Enable Pin. DITH = low
disables internal dither. DITH = high enables internal dither.
Refer to Internal Dither section of this data sheet for details
on dither operation.
ISMODE (Pin 16): Idle Synchronization mode. When ISMODE is not asserted, synchronization is performed with
a series of COMMAS (K28.5). When ISMODE is asserted,
a special Idle SYNC mode is enabled where synchronization is performed by sending a COMMA (K28.5) followed
by the appropriate data code-group (D5.6 or D16.2) for
establishing a negative running disparity for the first data
code-group after synchronization.
SRR0 (Pin 17): Sample Rate Range Select Bit0. Used with
the SRR1 pin to select the sample rate operating range.
SRR1 (Pin 18): Sample Rate Range Select Bit1. Used with
the SRR0 pin to select the sample rate operating range.
SHDN (Pins 19, 20): Shutdown Pins. A high level on both
pins will shut down the chip.
OVDD (Pins 22, 25): Positive Supply for the Output Drivers.
This supply range is 1.2V to VDD for directly coupled CML
outputs, or 1.4V to OVDD for AC-coupled or differentially
terminated CML outputs. Bypass to ground with 0.1μF
ceramic chip capacitor.
CMLOUT– (Pin 23): Negative High-Speed CML Output.
CMLOUT+ (Pin 24): Positive High-Speed CML Output.
SYNC+ (Pin 28): Sync Request Positive Input (Active
Low for Compatibility with JESD204). A low level on this
pin for at least two sample clock cycles will initiate frame
synchronization.
SYNC– (Pin 29): Sync Request Negative Input. A high
level on this pin for at least two sample clock cycles will
initiate frame synchronization. For single-ended operation,
bypass to ground with a 0.1μF capacitor and use SYNC+
as the SYNC point.
FAM (Pin 31): Frame Alignment Monitor Enable. A high
level enables the substitution of predetermined data at the
end of the frame with a K28.7 symbol for frame alignment
monitoring.
PAT0 (Pin 32): Pattern Select Bit0. Use with PAT1 to select
a test pattern for the serial interface.
PAT1 (Pin 33): Pattern Select Bit1. Use with PAT0 to select
a test pattern for the serial interface.
SCRAM (Pin 34): Enable Data Scrambling. A high level on
this pin will apply the polynomial 1 + x14 + x15 in scrambling each ADC data sample. The scrambling takes place
before the 8B/10B encoding.
PGA (Pin 35): Programmable Gain Amplifier Control
Pin. Low selects a front-end gain of 1, input range of
2.25VP-P . High selects a front-end gain of 1.5, input range
of 1.5VP-P .
MSBINV (Pin 36): Invert the MSB. A high level will invert
the MSB to enable the 2’s complement format.
2274fb
12
LTC2274
PIN FUNCTIONS
SENSE (Pin 38): Reference Mode Select and External
Reference Input. Tie SENSE to VDD to select the internal
2.5V bandgap reference. An external reference of 2.5V or
1.25V may be used; both reference values will set a full
scale ADC range of 2.25V (PGA = 0).
VCM (Pin 39): 1.25V Output. Optimum voltage for input
common mode. Must be bypassed to ground with a
minimum of 2.2μF. Ceramic chip capacitors are recommended.
GND (Exposed Pad) (Pin 41): ADC Power Ground. The
Exposed Pad on the bottom of the package needs to be
soldered to ground.
BLOCK DIAGRAM
FAM
PIPELINED ADC STAGES
SYNC+
+
AIN+
S/H
AND PGA
FIRST
STAGE
SECOND
STAGE
THIRD
STAGE
FOURTH
STAGE
8B/10B
ENCODER
FIFTH
STAGE
SYNC–
–
AIN–
16
DITHER SIGNAL
GENERATOR
20
CORRECTION
LOGIC
OVDD
REFERENCE
CONTROL
SERIALIZER
CMLOUT–
ADC
REFERENCE
SENSE
0.5x
VCM
CMLOUT+
20X CLK
1x OR 2x
2.5V
REFERENCE
CLOCK DRIVER
WITH DUTY CYCLE
CONTROL
ENC+
ENC–
SCRAMBLER/
PATTERN
GENERATOR
CONTROL LOGIC
PGA
DITH
MSBINV
SHDN
PAT1
PAT0
VDD
PLL
SCRAM
SRR1
SRR0
GND
22743 BD
Figure 1. Functional Block Diagram
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13
LTC2274
DEFINITIONS
DYNAMIC PERFORMANCE TERMS
Spurious Free Dynamic Range (SFDR)
Signal-to-Noise Plus Distortion Ratio
The ratio of the RMS input signal amplitude to the RMS
value of the peak spurious spectral component expressed
in dBc. SFDR may also be calculated relative to full scale
and expressed in dBFS.
The signal-to-noise plus distortion ratio [S/(N+D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited to frequencies above DC to below half the sampling
frequency.
Signal-to-Noise Ratio
Full Power Bandwidth
The full power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is reduced
by 3dB for a full scale input signal.
The signal-to-noise (SNR) is the ratio between the RMS
amplitude of the fundamental input frequency and the RMS
amplitude of all other frequency components, except the
first five harmonics.
The time from when a rising ENC+ equals the ENC– voltage
to the instant that the input signal is held by the sampleand-hold circuit.
Total Harmonic Distortion
Aperture Delay Jitter
Total harmonic distortion is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
The variation in the aperture delay time from conversion
to conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
THD = –20Log (√(V22 + V32 + V42 + ... VN2)/V1)
Aperture Delay Time
SNRJITTER = –20log (2π • fIN • tJITTER)
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second
through nth harmonics.
SERIAL INTERFACE TERMS
Intermodulation Distortion
A data encoding method designed to make an 8-bit data
word (octet) more suitable for serial transmission. The
resulting 10-bit word (code-group) has two fundamental
strengths: 1) The receiver does not require a high-speed
clock to capture the data. This is because the output
code-groups are run-length limited, ensuring that there
are enough transitions in the bit stream for the receiver
to lock onto the data and recover the high-speed clock.
2) AC coupling is permitted because the code-groups are
generated in a way that ensures the data stream is DC
balanced (see Running Disparity).
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function
can create distortion products at the sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 3rd order IMD terms include (2fa + fb),
(fa + 2fb), (2fa - fb) and (fa - 2fb). The 3rd order IMD is
defined as the ratio of the RMS value of either input tone
to the RMS value of the largest 3rd order IMD product.
8B/10B Encoding
A table of the 256 possible input octets with the resulting
10-bit code-groups is documented in IEEE Std 802.3-2002
part3 Table 36-1. The name associated with each of the
256 data code-groups is formatted Dx.y, with x ranging
from 0 to 31 and y ranging from 0 to 7. Table 36-2 of
2274fb
14
LTC2274
DEFINITIONS
the standard defines an additional set of 12 special codegroups for non-data characters such as commas. Special
code-group names begin with K instead of D. A complete
8B/10B description is found in Clause 36.2 of IEEE Std
802.3-2002 part3.
when the average number of 1’s and 0’s are equal, eliminating the undesirable effects of DC wander on the receive
side of the coupling capacitor. When 8B/10B coding is
used, DC balance is achieved by following disparity rules
(see Running Disparity).
Current Mode Logic (CML)
De-Scrambler
A technique used to implement differential high-speed logic.
CML employs differential pairs (usually n-type) to steer
current into resistive loads. It is possible to implement any
logic function using CML. The output swing and offset is
dependant on the bias current, the load resistance, and
termination resistance.
A logic block that restores scrambled data to its prescrambled state. A self aligning de-scrambler is based on
the same pseudo random bit sequence as the scrambler,
so it requires no alignment signals. In this product family
the scrambler is based on the 1 + x14 + x15 polynomial,
and the self aligning process results in an initial loss of
one ADC sample.
This product family uses CML drivers to transmit highspeed serial data to the outside world. The output driver
bias current is typically 16mA, generating a signal swing
potential of 400mVP-P (800mVP-P diff.) across the combined internal and external termination resistance of 25Ω
on each output.
Frame
A group of octets or code-groups that make up one
complete word. For this product family, a frame consists
of two complete octets or code-groups, and constitutes
one ADC sample.
Code-Group
The 10-bit output from an 8B/10B encoder or the 10-bit
input to the 8B/10B decoder.
Comma
A special 8B/10B code-group containing the binary sequence “0011111” or “1100000”. Commas are used for
frame alignment and synchronization because a comma
sequence cannot be generated by any combination of
normal code-groups (unless a bit error occurs). There are
three special code-groups that contain a comma, K28.1,
K28.5, and K28.7.
For brevity, each of these three special code-groups are
often called a comma, but in the strictest sense it is the
first 7 bits of these code-groups that are designated a
comma.
DC Balanced Signal
A specially conditioned signal that may be AC coupled with
minimal degradation to the signal. DC balance is achieved
Frame Alignment Monitoring (FAM)
After initial frame synchronization has been established,
frame alignment monitoring enables the receiver to verify
that code-group alignment is maintained without the loss
of data. This is done by substituting a K28.7 comma for the
last code-group of the frame when certain conditions are
met. The receiver uses this comma as a position marker
within the frame for alignment verification. After decoding
the data, the receiver replaces the K28.7 comma with the
original data.
Idle Frame Synchronization Mode (ISMODE)
A special synchronization mode where idle ordered sets
are used to establish initial frame synchronization instead
of K28.5 commas.
An Idle Ordered Set is defined in the IEEE Std 802.3-2002
part3, Clause 36.2.4.12. In general, it is a K28.5 comma
followed by either a D5.6 or a D16.2. If the running disparity after the transmission of the K28.5 comma is positive,
2274fb
15
LTC2274
DEFINITIONS
a D16.2 will be transmitted after the comma, otherwise
a D5.6 will be transmitted. The result is that the ending
disparity of an idle ordered set will always be negative.
running disparity is calculated to determine which of the
two code-groups should be transmitted to maintain DC
balance.
Initial Frame Synchronization
The disparity of a code-group is analyzed in two segments
called sub-blocks. Sub-block1 consists of the first six bits
of a code-group and sub-block2 consists of the last four
bits of a code-group. When a sub-block is more heavily
weighted with 1’s the running disparity is positive, and when
it is more heavily weighted with 0’s the running disparity
is negative. When the number of 1’s and 0’s are equal in a
sub-block, the running disparity remains unchanged.
The process of communicating frame synchronization
information to the receiver upon the request of the receiver.
For JESD204 compliance, K28.5 commas are transmitted
as the preamble. Once the preamble has been detected
the receiver terminates the synchronization request, and
the preamble transmission continues until the end of the
frame. The receiver designates the first normal data word
after the preamble to be the start of the data frame.
Octet
The 8-bit input to an 8B/10B encoder, or the 8-bit output
from an 8B/10B decoder.
Run-Length Limited (RLL)
The act of limiting the number of consecutive 1’s or 0’s
in a data stream by encoding the data prior to serial
transmission.
This process guarantees that there will be an adequate
number of transitions in the serial data for the receiver
to lock onto with a phase-locked loop and recover the
high-speed clock.
Running Disparity
In order to maintain DC balance there are two possible
8B/10B output code-groups for each input octet. The
The polarity of the current running disparity determines
which code-group should be transmitted to maintain DC
balance. For a complete description of disparity rules, refer
to IEEE Std 802.3-2002 part3, Clause 36.2.4.4.
Pseudo Random Bit Sequence (PRBS)
A data sequence having a random nature over a finite
interval. The most commonly used PRBS test patterns
may be described by a polynomial in the form of 1 + xm +
xn and have a random nature for the length of up to 2n – 1
bits, where n indicates the order of the PRBS polynomial
and m plays a role in maximizing the length of the random
sequence.
Scrambler
A logic block that applies a pseudo random bit sequence
to the input octets to minimize the tonal content of the
high-speed serial bit stream.
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16
LTC2274
APPLICATIONS INFORMATION
CONVERTER OPERATION
The core of the LTC2274 is a CMOS pipelined multi-step
converter with a front-end PGA. As shown in Figure 1, the
converter has five pipelined ADC stages. A sampled analog
input will result in a digitized value nine clock cycles later
(see the Timing Diagram section). The analog input (AIN+,
AIN–) is differential for improved common mode noise immunity and to maximize the input range. Additionally, the
differential input drive will reduce even order harmonics
of the sample and hold circuit. The encode clock input
(ENC+, ENC–) is also differential for improved common
mode noise immunity.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC, and an error residue amplifier. The
function of each stage is to produce a digital representation
of its input voltage along with the resulting analog error
residue. The ADC of each stage provides the quantization,
and the residue is produced by taking the difference between
the input voltage and the output of the reconstruction DAC.
The residue is amplified by the residue amplifier and passed
on to the next stage. The successive stages of the pipeline
operate on alternating phases of the clock so that when
odd stages are outputting their residue, the even stages
are acquiring that residue and vice versa.
The pipelined ADC of the LTC2274 has two phases of
operation determined by the state of the differential
ENC+/ENC– input pins. For brevity, the text will refer to
ENC+ greater than ENC– as ENC high and ENC+ less than
ENC– as ENC low.
When ENC is low, the analog input is sampled differentially
onto the input sample-and-hold capacitors, inside the “S/H
& PGA” block of Figure 1. On the rising edge of ENC, the
voltage on the sample capacitors is held. While ENC is
high, the held input voltage is buffered by the S/H amplifier
which drives the first pipelined ADC stage. The first stage
acquires the output of the S/H amplifier during the high
phase of ENC. On the falling edge of ENC, the first stage
produces its residue which is acquired by the second stage.
The process continues to the end of the pipeline.
Each ADC stage following the first has additional error
correction range to accommodate flash and amplifier offset
errors. Results from all of the ADC stages are digitally
delayed such that the results can be properly combined
in the correction logic before being encoded, serialized,
and sent to the output buffer.
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17
LTC2274
APPLICATIONS INFORMATION
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Input Drive Impedance
Sample/Hold Operation
As with all high performance, high speed ADCs the dynamic performance of the LTC2274 can be influenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and input reactance
can influence SFDR. At the falling edge of ENC the
sample-and-hold circuit will connect the 4.9pF sampling
capacitor to the input pin and start the sampling period.
The sampling period ends when ENC rises, holding the
sampled input on the sampling capacitor. Ideally, the
input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2FENCODE); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
Figure 2 shows an equivalent circuit for the LTC2274 CMOS
differential sample and hold. The differential analog inputs
are sampled directly onto sampling capacitors (CSAMPLE)
through NMOS transistors. The capacitors shown attached
to each input (CPARASITIC) are the summation of all other
capacitance associated with each input.
During the sample phase when ENC is low, the NMOS
transistors connect the analog inputs to the sampling
capacitors and they charge to, and track, the differential
input voltage. On the rising edge of ENC, the sampled
input voltage is held on the sampling capacitors. During
the hold phase when ENC is high, the sampling capacitors
are disconnected from the input and the held voltage is
passed to the ADC core for processing. As ENC transitions
for high to low, the inputs are reconnected to the sampling
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportional to the change in voltage between samples will
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such
as the change seen with input frequencies near Nyquist,
then a larger charging glitch will be seen.
For the best performance it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
LTC2274
VDD
AIN+
Common Mode Bias
The ADC sample-and-hold circuit requires differential drive
to achieve specified performance. Each input should swing
±0.5625V for the 2.25V range (PGA = 0) or ±0.375V for
the 1.5V range (PGA = 1), around a common mode voltage of 1.25V. The VCM output pin (Pin 39) is designed to
provide the common mode bias level. VCM can be tied
directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
driver circuit. The VCM pin must be bypassed to ground
close to the ADC with 2.2μF or greater.
RON
20Ω
RPARASITIC
3Ω
CSAMPLE
4.9pF
CPARASITIC
1.8pF
VDD
RPARASITIC
3Ω
RON
20Ω
AIN–
CSAMPLE
4.9pF
CPARASITIC
1.8pF
VDD
1.6V
6k
ENC+
ENC–
6k
1.6V
2274 F02
Figure 2. Equivalent Input Circuit
2274fb
18
LTC2274
APPLICATIONS INFORMATION
INPUT DRIVE CIRCUITS
Input Filtering
A first order RC lowpass filter at the input of the ADC can
serve two functions: limit the noise from input circuitry and
provide isolation from ADC S/H switching. The LTC2274
has a very broadband S/H circuit, DC to 700MHz; it can
be used in a wide range of applications; therefore, it is not
possible to provide a single recommended RC filter.
Figures 3, 4a and 4b show three examples of input RC
filtering at three ranges of input frequencies. In general
it is desirable to make the capacitors as large as can be
tolerated—this will help suppress random noise as well
as noise coupled from the digital circuitry. The LTC2274
does not require any input filter to achieve data sheet
specifications; however, no filtering will put more stringent
noise requirements on the input drive circuitry.
the input bandwidth and increase high frequency distortion. A disadvantage of using a transformer is the loss of
low frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
Center-tapped transformers provide a convenient means
of DC biasing the secondary; however, they often show
poor balance at high input frequencies, resulting in large
2nd order harmonics.
Figure 4a shows transformer coupling using a transmission line balun transformer. This type of transformer has
much better high frequency response and balance than
flux coupled center tap transformers. Coupling capacitors
are added at the ground and input primary terminals to
allow the secondary terminals to be biased at 1.25V. Figure
4b shows the same circuit with components suitable for
higher input frequencies.
VCM
Transformer Coupled Circuits
2.2μF
Figure 3 shows the LTC2274 being driven by an RF transformer with a center-tapped secondary. The secondary
center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used; however,
as the turns ratio increases so does the impedance seen by
the ADC. Source impedance greater than 50Ω can reduce
VCM
0.1μF
5Ω AIN+
10Ω
ANALOG
INPUT
25Ω
0.1μF
25Ω
10Ω
T1
1:1
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2μF
4.7pF
5Ω AIN–
4.7pF
8.2pF
VCM
LTC2274
35Ω
2.2μF
8.2pF
0.1μF
0.1μF
35Ω
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2μF
2274 F04a
5Ω AIN+
10Ω
T1
10Ω
LTC2274
4.7pF
Figure 4a. Using a Transmission Line Balun Transformer.
Recommended for Input Frequencies from 100MHz to 250MHz
2.2μF
50Ω
0.1μF
5Ω
25Ω
8.2pF
Figure 3. Single-Ended to Differential Conversion
Using a Transformer. Recommended for Input
Frequencies from 5MHz to 150MHz
5Ω
ANALOG
INPUT
AIN–
2274 F03
0.1μF
T1
1:1
0.1μF
25Ω
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2μF
AIN+
LTC2274
2.2pF
5Ω
2.2pF
AIN–
2274 F04b
Figure 4b. Using a Transmission Line Balun Transformer.
Recommended for Input Frequencies from 250MHz to 500MHz
2274fb
19
LTC2274
APPLICATIONS INFORMATION
Direct Coupled Circuits
Figure 5 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides
low frequency input response; however, the limited gain
bandwidth of any op amp or closed-loop amplifier will degrade the ADC SFDR at high input frequencies. Additionally,
wideband op amps or differential amplifiers tend to have
high noise. As a result, the SNR will be degraded unless
the noise bandwidth is limited prior to the ADC input.
Reference Operation
Figure 6 shows the LTC2274 reference circuitry consisting
of a 2.5V bandgap reference, a programmable gain amplifier and control circuit. The LTC2274 has three modes of
reference operation: Internal Reference, 1.25V external
reference or 2.5V external reference. To use the internal
reference, tie the SENSE pin to VDD. To use an external
reference, simply apply either a 1.25V or 2.5V reference
voltage to the SENSE input pin. Both 1.25V and 2.5V applied
to SENSE will result in a full scale range of 2.25VP-P (PGA
= 0). A 1.25V output VCM is provided for a common mode
bias for input drive circuitry. An external bypass capacitor is
required for the VCM output. This provides a high frequency
low impedance path to ground for internal and external
circuitry. This is also the compensation capacitor for the
reference; it will not be stable without this capacitor. The
minimum value required for stability is 2.2μF.
The internal programmable gain amplifier provides the
internal reference voltage for the ADC. This amplifier has
very stringent settling requirements and is not accessible
for external use.
The SENSE pin can be driven ±5% around the nominal 2.5V
or 1.25V external reference inputs. This adjustment range
can be used to trim the ADC gain error or other system
gain errors. When selecting the internal reference, the
SENSE pin should be tied to VDD as close to the converter
as possible. If the sense pin is driven externally it should
be bypassed to ground as close to the device as possible
with 1μF (or larger) ceramic capacitor.
PGA Pin
The PGA pin selects between two gain settings for
the ADC front-end. PGA = 0 selects an input range of
2.25VP-P; PGA = 1 selects an input range of 1.5VP-P. The
2.25V input range has the best SNR; however, the distortion will be higher for input frequencies above 100MHz.
For applications with high input frequencies, the low
input range will have improved distortion; however, the
SNR will be 2.4dB worse. See the Typical Performance
Characteristics section of this datasheet.
LTC2274
RANGE
SELECT
AND GAIN
CONTROL
VCM
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
ANALOG
INPUT
+
CM
–
2.2μF
LTC2274
12pF
+
–
AIN+
25Ω
AIN–
25Ω
AMPLIFIER = LTC6600-20,
LTC1993, ETC.
12pF
TIE TO VDD TO USE
INTERNAL 2.5V
REFERENCE
OR INPUT FOR
EXTERNAL 2.5V
REFERENCE
OR INPUT FOR
EXTERNAL 1.25V
REFERENCE
SENSE
1x OR 2x
2.5V
BANDGAP
REFERENCE
2274 F05
VCM
Figure 5. DC Coupled Input with Differential Amplifier
INTERNAL
ADC
REFERENCE
BUFFER
1.25V
2.2μF
2274 F06
Figure 6. Reference Circuit
2274fb
20
LTC2274
APPLICATIONS INFORMATION
LTC2274
VDD
TO INTERNAL
ADC CLOCK
DRIVERS
VDD
VCM
1.25V
6k
ENC+
2.2μF
2, 3
3.3V
LTC6652-2.5
1μF
1.6V
6
4, 5, 7, 8
LTC2274
SENSE
VDD
1.6V
6k
2.2μF
ENC–
2274 F07
2274 F08a
Figure 7. A 2.25V Range ADC with
an External 2.5V Reference
0.1μF
Figure 8a. Equivalent Encode Input Circuit
ENC+
T1
50Ω
100Ω
LTC2274
8.2pF
0.1μF
ENC+
VTHRESHOLD = 1.6V
50Ω
1.6V ENC–
0.1μF
ENC–
LTC2274
0.1μF
2274 F09
2274 F08b
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 8b. Transformer Driven Encode
Figure 9. Single-Ended ENC Drive,
Not Recommended for Low Jitter
3.3V
MC100LVELT22
3.3V
130Ω
Q0
130Ω
ENC+
D0
ENC–
Q0
83Ω
LTC2274
83Ω
2274 F10
Figure 10. ENC Drive Using a CMOS to PECL Translator
2274fb
21
LTC2274
APPLICATIONS INFORMATION
Driving the Encode Inputs
The noise performance of the LTC2274 can depend on
the encode signal quality as much as for the analog input.
The encode inputs are intended to be driven differentially,
primarily for noise immunity from common mode noise
sources. Each input is biased through a 6k resistor to a
1.6V bias. The bias resistors set the DC operating point
for transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.
Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequencies), take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude possible. If using transformer coupling, use a higher turns ratio to increase the
amplitude.
3. If the ADC is clocked with a fixed frequency sinusoidal
signal, filter the encode signal to reduce wideband
noise.
4. Balance the capacitance and series resistance at both
encode inputs such that any coupled noise will appear
at both inputs as common mode noise.
The encode inputs have a common mode range of 1.2V
to VDD. Each input may be driven from ground to VDD for
single-ended drive.
Maximum and Minimum Conversion Rates
The maximum conversion rate is 105Msps for the
LTC2274.
The lower limit of the LTC2274 sample rate is determined
by the PLL minimum operating frequency of 20Msps.
For the ADC to operate properly, the internal CLK signal
should have a 50% duty cycle. A duty cycle stabilizer circuit has been implemented on chip to facilitate non-50%
ENC duty cycles.
Data Format
The MSBINV pin selects the ADC data format. A low level
selects offset binary format (code 0 corresponds to –FS, and
code 65535 corresponds to +FS). A high level on MSBINV
selects 2’s complement format (code –32768 corresponds
to –FS and code 32767 corresponds to +FS.
Shutdown
A high level on both SHDN pins will shutdown the ADC
and the serial interface and place the chip in a low current state.
Internal Dither
The LTC2274 is a 16-bit ADC with a very linear transfer
function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones.
Small errors in the transfer function are usually a result
of ADC element mismatches. An optional internal dither
mode can be enabled to randomize the input location on
the ADC transfer curve, resulting in improved SFDR for
low signal levels.
As shown in Figure 11, the output of the sample-and-hold
amplifier is summed with the output of a dither DAC. The
dither DAC is driven by a long sequence pseudo-random
number generator; the random number fed to the dither
DAC is also subtracted digitally from the ADC result. If the
dither DAC is precisely calibrated to the ADC, very little
of the dither signal will be seen at the output. The dither
signal that does leak through will appear as white noise.
The dither DAC is calibrated to result in less than 0.5dB
elevation in the noise floor of the ADC, as compared to
the noise floor with dither off.
2274fb
22
LTC2274
APPLICATIONS INFORMATION
LTC2274
AIN+
ANALOG
INPUT
AIN–
CMLOUT+
16-BIT
PIPELINED
ADC CORE
S/H
AMP
CLOCK/DUTY
CYCLE
CONTROL
DIGITAL
SUMMATION
8b10b
ENCODER
SERIALIZER
CMLOUT–
MULTIBIT DEEP
PSEUDO-RANDOM
NUMBER
GENERATOR
PRECISION
DAC
2274 F11
ENC +
ENC –
DITH
DITHER ENABLE
HIGH = DITHER ON
LOW = DITHER OFF
Figure 11. Functional Equivalent Block Diagram of Internal Dither Circuit
SERIALIZED DATA FRAME
Figure 12 illustrates the generation of one complete 8B/10B
frame. The 8 most significant bits of the ADC are assigned
to the first half of the frame, and the remaining 8 bits
to the second half of the frame. Next, the two resulting
octets are optionally scrambled and encoded into their
corresponding 8B/10B code. Finally, the two 10-bit code
groups are serialized and transmitted beginning with Bit
0 of code group 1.
Prior to serialization, the ADC data is encoded into the
8B/10B format, which is DC balanced, and run-length
limited. The receiver is required to lock onto the data
and recover the clock with the use of a PLL. The 8B/10B
format requires that the ADC data be broken up into 8-bit
blocks (octets), which is encoded into 10-bit code groups
applying the 8B/10B rules (refer to IEEE Std 802.3-2002
Part 3, for a complete 8B/10B description).
MSB
ADC OUTPUT WORD
BIT
15
BIT
14
BIT
13
BIT
12
BIT
11
BIT
10
BIT
9
BIT
8
BIT
7
LSB
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
BIT
0
H
G
F
E
D
C
B
A
H
G
F
E
D
C
B
A
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
BIT
0
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
BIT
0
FIRST OCTET
OCTET
ASSIGNMENT
SECOND OCTET
H
G
F
E
D
C
B
A
H
G
F
E
D
C
B
A
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
BIT
0
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
BIT
0
FIRST SCRAMBLED OCTET
OPTIONAL
SCRAMBLER
SECOND SCRAMBLED OCTET
a
b
c
d
e
i
f
g
h
j
a
b
c
d
e
i
f
g
h
j
BIT
0
BIT
1
BIT
2
BIT
3
BIT
4
BIT
5
BIT
6
BIT
7
BIT
8
BIT
9
BIT
0
BIT
1
BIT
2
BIT
3
BIT
4
BIT
5
BIT
6
BIT
7
BIT
8
BIT
9
8B/10B CODE GROUP 1
8B/10B
ENCODER
8B/10B CODE GROUP 2
ONE FRAME
BIT 0 OF CODE GROUP 1 IS TRANSMITTED FIRST
SERIAL OUT
2274 F12
Figure 12. Evolution of One Transmitted Frame (Compare to IEEE Std 802.3-2002 Part 3, Figure 36-3)
2274fb
23
LTC2274
APPLICATIONS INFORMATION
tAP
ANALOG INPUT
N+9
N+2
N+1
N
N + 10
N+8
tCONV
ENC+
tH
tL
INTERNAL
PARALLEL DATA
N–6
N–5
N–4
N+3
N+4
INTERNAL
8B/10B DATA
N–9
N–8
N–7
N
N+1
LATP
tBIT
SERIAL DATA OUT
N – 10
N–9
N–8
N–1
N
2274 F13
Figure 13. Timing Relationship of Analog Sample to Serial Data Out
Initial Frame Synchronization
In the absence of a frame clock, it is necessary to determine the start of each frame through a synchronization
process. To establish frame synchronization, Figures 14
and 15 illustrate the following sequence:
• The receiver issues a synchronization request via the
synchronization interface.
• If the synchronization request is active for more than
one ENC clock cycle, the LTC2274 will transmit a
synchronization preamble. When the ISMODE pin is
low the transmitted preamble will consist of consecutive K28.5 comma symbols in conformance with the
JESD204 specification. When the ISMODE pin is high,
a series of idle ordered sets will be transmitted. The
idle ordered sets consist of a K28.5 comma followed by
either D5.6 or D16.2 as defined in IEEE Std 802.3-2002
part3, Clause 36.2.4.12.
• The receiver searches for the expected preamble and
waits for the correct reception of an adequate number
of preamble characters.
• The receiver deactivates the synchronization request.
• Upon detecting the deactivation of the synchronization request, the LTC2274 continues to transmit the
synchronization preamble until the end of the frame.
• At the start of the next frame, the LTC2274 will begin
transmitting data characters.
• The receiver designates the first data character received
after the preamble transmission to be the start of the
frame. The first octet of the frame contains the most
significant byte of the ADC’s output word.
2274fb
24
LTC2274
APPLICATIONS INFORMATION
tCONV
ANALOG INPUT
N+3
N
N–1
N+2
N+1
tHD
N+4
N+5
tSU
ENC+
tCS(MIN)
SYNC+
LATSC
tCS(MAX)
SERIAL DATA OUT
N – 10
N–9
N–7
N–8
K28.5 (x2)
K28.5 (x2)
2274 F14a
Figure 14a. SYNC+ Low Transition to Comma Output Timing (ISMODE is Low)
tCONV
ANALOG INPUT
N+3
N
N–1
N+2
N+1
tHD
N+4
tSU
ENC+
tCS(MIN)
SYNC+
LATSD
tCS(MAX)
SERIAL DATA OUT
K28.5 (x2)
K28.5 (x2)
K28.5 (x2)
N–7
N–6
2274 F14b
Figure 14b. SYNC+ High Transition to Data Output Timing (ISMODE is Low)
2274fb
25
LTC2274
APPLICATIONS INFORMATION
START
WAIT FOR NEXT
FRAME CLOCK
NO
SYNC
REQUEST?
DATA TRANSMISSION
FLOW (SEE FIGURE 18)
YES
NO
YES
IS ISMODE
ENABLED?
NO
TRANSMIT K28.5
AS CODE GROUP 1
NEGATIVE
DISPARITY?
YES
TRANSMIT K28.5
AS CODE GROUP 2
(DISPARITY NOT OK)
(DISPARITY IS OK)
TRANSMIT K28.5
AS CODE GROUP 1
TRANSMIT K28.5
AS CODE GROUP 1
(NEGATIVE DISPARITY)
(POSITIVE DISPARITY)
TRANSMIT D5.6
AS CODE GROUP 2
TRANSMIT D16.2
AS CODE GROUP 2
(NEGATIVE DISPARITY)
(NEGATIVE DISPARITY)
2274 F15
Figure 15. Initial Synchronization Flow Diagram
Scrambling
To avoid spectral interference from the serial data output,
an optional data scrambler is added between the ADC
data and the 8B/10B encoder to randomize the spectrum
of the serial link. The scrambler is enabled by setting the
SCRAM pin to a high logic level. The polynomial used for
the scrambler is 1 + x14 + x15, which is a pseudo-random
pattern repeating itself every 215–1. Figure 16 illustrates
the LTC2274 implementation of this polynomial in parallel
form.
The scrambled data is converted into two valid 8B/10B
code groups, constituting a complete frame. The 8B/10B
code groups are then serialized and transmitted.
The receiver is required to deserialize the data, decode
the code-groups into octets and descramble them back
to the original octets using the self-aligning descrambler
shown in Figure 17. This descrambler is shown in 16-bit
parallel form, which is an efficient implementation of the
(1 + x14 + x15) polynomial, operating at the frame clock
rate (ADC sample rate).
2274fb
26
LTC2274
APPLICATIONS INFORMATION
SAMPLE_CLK
D0
SS0
Q
D
FF
C
D1
SS1
Q
FF
D
C
SS2
D2
Q
FF
D
C
D3
SECOND
OCTET
SS3
Q
D
FF
C
D4
SS4
Q
FF
D
C
D5
SS5
Q
D
FF
C
Q
D
FF
C
D6
SS6
D7
FROM
ADC
SS7
Q
FF
SF0
Q
FF
D
C
D9
SF1
Q
FF
D
C
D10
SF2
Q
D
FF
C
Q
D
FF
C
Q
D
FF
C
D11
SF3
D12
FIRST
SCRAMBLED
OCTET
SF4
D13
SF5
Q
FF
D
C
D13
SF6
Q
D15
MSB
TO 8B/10B
ENCODER
D
C
D8
FIRST
OCTET
SECOND
SCRAMBLED
OCTET
FF
D
C
SF7
MSB
2274 F16
Figure 16. LTC2274 16-Bit 1 + x14 + x15 Parallel Scrambler
2274fb
27
LTC2274
APPLICATIONS INFORMATION
FRAME_CLK
LSB
D0
SS0
D
Q
FF
C
D1
SS1
D
Q
FF
C
D2
SS2
D
Q
FF
C
D3
SECOND
SCRAMBLED
OCTET
SS3
D
Q
FF
C
D4
SS4
D
Q
FF
C
D5
SS5
D
Q
FF
C
D6
SS6
D
Q
FF
C
D7
SS7
FROM
8B/10B
DECODER
D
Q
FF
C
DESCRAMBLED
ADC DATA
D8
SF0
D
Q
FF
C
D9
SF1
D
Q
FF
C
D10
SF2
D
Q
FF
C
D11
FIRST
SCRAMBLED
OCTET
SF3
D
Q
FF
C
D12
SF4
D
Q
FF
C
D13
SF5
D
Q
FF
C
D14
SF6
D
Q
FF
C
SF7
MSB
D15
MSB
2274 F17
Figure 17. Required 16-Bit 1 + x14 + x15 Parallel Descrambler
2274fb
28
LTC2274
APPLICATIONS INFORMATION
Frame Alignment Monitoring
After the initial synchronization has been established, it may
be desirable to periodically verify that frame alignment is
being maintained. The receiver may issue a synchronization request at any time, but data will be lost during the
resynchronization interval.
To verify frame alignment without the loss of data, frame
alignment monitoring is enabled by setting the FAM pin
to a high level. In this mode, predetermined data in the
second code group of the frame is substituted with the
control character K28.7. The receiver is required to detect
the K28.7 character and replace it with the original data. In
this way, the second code group may be discerned from
the first, and the receiver is able to periodically verify the
frame alignment without the loss of data (refer to Table 1
and the flow diagram of Figure 18). There are two frame
alignment monitoring modes summarized in Table 1.
FAM mode 1 is implemented when FAM is high, and
SCRAM is low:
• When the data in the second code group of the current
frame equals the data in the second code group of the
previous frame, the LTC2274 will replace the second
code group with the control character K28.7 before
serialization. However, if a K28.7 symbol was already
transmitted in the previous frame, the actual code group
will be transmitted.
• Upon receiving a K28.7 symbol, the receiver is required
to replace it with the data decoded at the same position
of the previous frame.
FAM mode 2 is implemented when FAM is high and
SCRAM is high:
• When the data in the second code group of the current
frame equals D28.7, the LTC2274 will replace this data
with K28.7 before serialization.
• Upon receiving a K28.7 symbol, the receiver is required
to replace it with D28.7.
With FAM enabled the receiver is required to search for
the presence of K28.7 symbols in the data stream. If two
successive K28.7 symbols are detected at the same position other than the assumed end of frame, the receiver will
realign its frame boundary to the new position.
Table 1. Frame Alignment Monitoring Modes
SCRAM PIN
DDSYNC PIN
FAM Mode 1
Low
High
The second code group is replaced with K28.7 if
it is equal to the 2nd Code Group of the previous
frame
FAM Mode 2
High
High
The second code group is replaced with K28.7 if
it is equal to D28.7
X
Low
No K28.7 substitutions will take place
FAM OFF
ACTION
2274fb
29
LTC2274
APPLICATIONS INFORMATION
START
SCRAMBLE ADC DATA
IF SCRAM IS ENABLED
GENERATE 8B/10B
CODE-GROUPS 1 AND 2
NO
YES
IS FAM
ENABLED?
(FRAME ALIGNMENT MONITORING IS ENABLED)
TRANSMIT
CODE GROUP 1
TRANSMIT
CODE GROUP 1
NO
TRANSMIT
CODE GROUP 2
NO
IS CODE
GROUP 2 =
CODE GROUP 2
OF LAST
FRAME?
YES
IS SCRAM
ENABLED?
(DATA SCRAMBLING IS ENABLED)
NO
YES
TRANSMIT
CODE GROUP 2
IS CODE
GROUP 2 =
D28.7?
TRANSMIT
CODE GROUP 2
NO
WAS K28.7
TRANSMITTED
IN LAST
FRAME?
TRANSMIT K28.7
AS CODE GROUP 2
YES
TRANSMIT K28.7
AS CODE GROUP 2
YES
TRANSMIT
CODE GROUP 2
END
2274 F18
Figure 18. Data Transmission Flow Diagram
PLL Operation
Serial Test Patterns
The PLL has been designed to accommodate a wide range
of sample rates. The SRR0 and SRR1 pins are used to
configure the PLL for the intended sample rate range.
Table 2 summarizes the sample clock ranges available
to the user.
To facilitate testing of the serial interface, three test patterns
are selectable via pins PAT0 and PAT1. The available test
patterns are described in Table 3. A K28.5 comma may be
used as a fourth test pattern by requesting synchronization
through the SYNC+/SYNC– pins.
Table 2. Sample Rate Ranges
Table 3. Test Patterns
SRR1
SRR0
SAMPLE RATE RANGE
PAT1
PAT0
TEST PATTERNS
0
x
20Msps < FS ≤ 35Msps
0
0
ADC Data
1
0
30Msps < FS ≤ 65Msps
0
1
1
1
60Msps < FS ≤ 105Msps
1010101010 Pattern
(8B/10B Code Group D21.5)
1
0
1+ x9 + x11 Pseudo Random Pattern
1
1
1+ x14 + x15 Pseudo Random Pattern
2274fb
30
LTC2274
APPLICATIONS INFORMATION
High Speed CML Outputs
Grounding and Bypassing
The CML outputs must be terminated for proper operation. The OVDD supply voltage and the termination voltage
determine the common mode output level of the CML
outputs. For proper operation of the CML driver, the output
common mode voltage should be greater than 1V.
The LTC2274 require a printed circuit board with a
clean unbroken ground plane; a multilayer board with an
internal ground plane is recommended. The pinout of the
LTC2274 has been optimized for a flowthrough layout so
that the interaction between inputs and digital outputs is
minimized. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track
or underneath the ADC.
The directly-coupled termination mode of Figure 19a is
recommended when the receiver termination voltage is
within the range of 1.2V to 3.3V. When the CML outputs
are directly-coupled to the 50Ω termination resistors, the
OVDD supply voltage serves as the receiver termination
voltage, and the output common mode voltage will be
approximately 200mV lower than OVDD.
The directly-coupled differential termination of Figure 19b
may be used in the absence of a receiver termination voltage
within the required range. In this case, the common mode
voltage is shifted down to approximately 400mV below
OVDD, requiring an OVDD in the range of 1.4V to 3.3V.
If the serial receiver’s common mode input requirements
are not compatible with the directly-coupled termination
modes, the DC balanced 8B/10B encoded data will permit
the addition of DC blocking capacitors as shown in Figure
19c. In this AC-coupled mode, the termination voltage is
determined by the receiver’s requirements. The coupling
capacitors should be selected appropriately for the intended
operating bit-rate, usually between 1nF to 10nF. In the ACcoupled mode, the output common mode voltage will be
approximately 400mV below OVDD, so the OVDD supply
voltage should be in the range of 1.4V to 3.3V.
High quality ceramic bypass capacitors should be used
at the VDD, VCM, and OVDD pins. Bypass capacitors must
be located as close to the pins as possible. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
The LTC2274 differential inputs should run parallel and
close to each other. The input traces should be as short
as possible to minimize capacitance and to minimize
noise pickup.
Heat Transfer
Most of the heat generated by the LTC2274 is transferred
from the die through the bottom-side exposed pad. For
good electrical and thermal performance, the exposed
pad must be soldered to a large grounded pad on the PC
board. It is critical that the exposed pad and all ground
pins are connected to a ground plane of sufficient area
with as many vias as possible.
2274fb
31
LTC2274
APPLICATIONS INFORMATION
SERIAL CML DRIVER
SERIAL CML RECEIVER
1.2V TO 3.3V
OVDD
50Ω
50Ω
CMLOUT+
50Ω
TRANSMISSION LINE
50Ω
50Ω
CMLOUT–
DATA+
50Ω
TRANSMISSION LINE
DATA–
16mA
GND
2274 F19a
Figure 19a. CML Termination, Directly-Coupled Mode (Preferred)
SERIAL CML DRIVER
SERIAL CML RECEIVER
OVDD
50Ω
50Ω
CMLOUT+
1.4V TO 3.3V
50Ω
TRANSMISSION LINE
100Ω
CMLOUT–
DATA+
50Ω
TRANSMISSION LINE
DATA–
16mA
GND
2274 F19b
Figure 19b. CML Termination, Directly-Coupled Differential Mode
2274fb
32
LTC2274
APPLICATIONS INFORMATION
SERIAL CML DRIVER
SERIAL CML RECEIVER
1.4V TO 3.3V
VTERM
OVDD
50Ω
50Ω
CMLOUT+
50Ω
TRANSMISSION LINE
50Ω
50Ω
0.01μF
CMLOUT–
DATA+
0.01μF
50Ω
TRANSMISSION LINE
DATA–
16mA
GND
2274 F19c
Figure 19c. CML Termination, AC-Coupled Mode
2274fb
33
LTC2274
TYPICAL APPLICATIONS
Silkscreen Top
Top Side
2274fb
34
LTC2274
TYPICAL APPLICATIONS
Inner Layer 2
Inner Layer 3
2274fb
35
LTC2274
TYPICAL APPLICATIONS
Inner Layer 4
Inner Layer 5
2274fb
36
LTC2274
TYPICAL APPLICATIONS
Bottom Side
Silkscreen Bottom
2274fb
37
J5
ENCODE
J2
SIG IN
5
6
J8
CLKOUT
C3*
R19*
C5
0.1μF
L1*
R36
10k
NC
ASSEMBLY TYPE
DC1151A-C
DC1151A-D
DC1151A-E
DC1151A-F
DC1151A-G
DC1151A-H
U1
LTC2274CU
LTC2274CU
LTC2273CU
LTC2273CU
LTC2272CU
LTC2272CU
4
3
•3
4•
R56
0Ω
GND
SENSE
VDD
5
4
C6
0.1μF
•3
4•
R52
68.1Ω
1
2
5
1
2
3
3.3V
R8
4.99Ω
R7
4.99Ω
ADC
SAMPLE RATE
105Msps
105Msps
80Msps
80Msps
65Msps
65Msps
R35
49.9Ω
C30
0.1μF
C11
0.1μF
1
3
2
R6
100Ω
R17
10Ω
R16
10Ω
C1*
R1
10Ω
OVDD
4
L1
56nH
18nH
56nH
18nH
56nH
18nH
PGA
R2
10Ω
5
4
ENC–
ENC
+
SENSE
VCM
3
R5, R19
86.6Ω
43.2Ω
86.6Ω
43.2Ω
86.6Ω
43.2Ω
R14
33.2Ω
C8
8.2pF
10
9
38
39
PGA
AIN–
AIN
+
1
C12 3.3V
0.1μF
35
R15
OPTIONAL
VCM
C2, C3
8.2pF
3.9pF
8.2pF
3.9pF
8.2pF
3.9pF
2
R10
4.99Ω
82pF
R9
4.99Ω
C16
202μF
R4
68.1Ω
C18
10μF
0805
R11
100Ω
OVDD
R3
68.1Ω
R31
4.32k
R22
1000Ω
C1
4.7pF
1.8pF
4.7pF
1.8pF
4.7pF
1.8pF
R33
10k
R32
10k
2.5V
C19
0.01μF
ADC
3.3V
T1
MABAES0060
6
5
T2
MABA-007159-000000
C20
0.01μF
13
BYP
2
3
3.3V
CML
DATA RATE
1.5GHz TO 2.5GHz
1.5GHz TO 2.5GHz
1.5GHz TO 2.5GHz
1.5GHz TO 2.5GHz
0.6GHz TO 1.5GHz
0.6GHz TO 1.5GHz
TP4
GND
TP3
EXT REF
C9
0.1μF
C10
0.1μF
R51
68.1Ω
1
2
T3*
7
5
NC
NC
NC
NC
SENSE
OUT
OUT
13
LT1763CDE
SHDN
IN
IN
R34
34Ω
12
9
4
1
8
11
10
U3
TLK2501
TLK2501
TLK2501
TLK2501
TLK1501
TLK1501
C4
0.1μF
R55
OPTIONAL
2
1
PORT2
SBTC-2-10L+
PORT1
C2*
R5*
R18
1000Ω
SUM
*VERSION TABLE
TP2
GND
C17
4.7μF
0805
L3
FERRITE BEAD
BLM1866470SN1D
GND
TP1
EX_3.3V
GND
GP
GP
•
EX_3.3V
GND
GND
7
•
NC
GND
12
2
12
13
7
8
T3
MABA-007159
WBC1-1LB
MABA-007159
WBC1-1LB
MABA-007159
WBC1-1LB
6
11
C15
0.01μF
U1
LTC2274CUJ
C13
0.1μF
C26
0.1μF
L4
FERRITE BEAD
BLM1866470SN1D
VDD
GND
6
VDD
GND
BYP
VDD
GND
NC
VDD
GND
9
37 40
22 25
OVDD
3.3V
21 26
INPUT FREQUENCY
1MHz TO 70MHz
70MHz TO 140MHz
1MHz TO 70MHz
70MHz TO 140MHz
1MHz TO 70MHz
70MHz TO 140MHz
14
GND
C34
0.01μF
GND
NC
GND
NC
OVDD
OGND
4
OVDD
OGND
SHDN
27
FAMON
SCRAM
MSBINV
PAT1
PAT0
DITH
ISMODE
PLL0
PLL1
PDADC
PDSER
SYNC+
SYNC–
CMLOUT–
CMLOUT+
C14
0.01μF
OGND
1
30
OGND
5
41
GND
SENSE
31
34
36
33
32
15
16
17
18
19
20
28
29
23
24
FAM
SCRAM
MSBINV
PAT1
PAT0
DITH
ISMODE
PLL0
PLL1
PDADC
PDSER
8
1
OFF
C27B
1nF
DITH
8
S2
2
7
ISMODE
R11
10k
3
6
4
5
C27A
1nF
1
3
6
DITH
4
5
C21
0.01μF
3
R44
1k
C22
0.01μF
S4
2
7
GND
5
3
6
4
5
61
60
59
58
57
56
55
54
53
52
3.3V
C36
0.01μF
PGA
PAT1
PAT0
SCRAM
FAM
PDSER
51 50
R23C
33Ω
R23D
33Ω
GNDA
DOUTTXP
DOUTTXN
GNDA
VDDA
RREF
VDDA
DINRXP
DINRXN
63
4
5
6
C23
0.01μF
2
3
4
Y
VCC
C
2
4
B
GND
A
3
2
1
R24B
33Ω
R24C
33Ω
NC7SZ332PSX
1
C28
0.01μF
64
C25
0.01μF NC7SP17P5X
R32
10Ω
3.3V
INT_SYNC
62
R53
1k
49 48 47 46
R24A
33Ω
INT_SYNC
PDADC
GNDA
R23B
33Ω
SW1
MAIN
SYNC
EVQPPDA25
VCC
NC7SVU04P5X
1
OFF
8
14
12
10
8
6
4
2
HEADER
OPTIONAL
13
11
9
7
5
3
1
L2
FERRITE BEAD
BLM1866470SN1D
R12
49.9k
R21
825Ω
MSBINV
SYNC
OPTIONAL
S3
2
7
PLL0
PLL1
ISMODE
2.5V
R20
200Ω
R13
49.9k
8
OFF
C26A
1nF
J7
CMLOUT+
C32
0.01μF
C26B
1nF
SYNC
R54
OPTIONAL
J6
CMLOUT–
PLL0
2.5V
PLL1
C33
10μF
0805
PDADC
2
PDSER
3
FAM
TXD0
OUT
MSBINV
PBUS0
RXD0
PBUS2
RXD2
VDD
20
P7
3
NC
OUT
SCRAM
VDD
TXD3
PBUS1
RXD1
TXD1
PBUS3
RXD3
TXD4
8
5
R43
10k
6
17
13
7
PLL1
14
12
18
R25B
33Ω
R25C
33Ω
43 42 41
8
9
10
C25
0.01μF
*U3
11
ISMODE
PFC8574TS
16
R25A
33Ω
R24D
33Ω
19
45 44
PBUS5
RXD5
GND
LT1763CDE-2.5
PAT0
TXD2
PBUS4
RXD4
TXD5
P6
NC
RX_ER
P5
NC
GND
GTX_CLK
PBUS6
RXD6
TXD6
P4
NC
TXD7
P3
PLL0
RX_CLK
15
5
3.3V
A0
A1
A2
SCL
SDA
INT
6
7
9
2
4
1
R26B
33Ω
R26C
33Ω
40 39 38 37 36
R26A
33Ω
R25D
33Ω
10
DITH
P0
PBUS9
11
RXD9
12
TXD10
PBUS7
RXD7
VDD
VDD
VDD
13
GND
IN
PAT1
14
15
RXD10
TXD11
P1
VSS
PBUS8
RXD8
TXD9
PBUS10
TXD12
16
R27C
33Ω
R26D
33Ω
3.3V
SCL
SDA
PBUS15
17
18
20
21
22
23
24
25
26
27
28
29
30
24LC32A-I/ST
19
TX_EN
LOOPEN
TX_ER
VDD
ENABLE
LCKREFN
PRBSEN
TESTEN
GND
RX_ER/PRBS_PASS
RX_DV/LOS
19
17
8
4
A0
A1
A2
WP
SDA
SCL
3
1
2
R46
10k
2.5V
18
1
2
3
7
5
6
JP2
RUN
SHDN
C37
0.01μF
13
14
12
11
WP
SDA
SCL
C24
0.01μF
10
5
3.3V
A0
A1
A2
SCL
SDA
INT
24LC025-I/ST
R47
OPTIONAL
R45
10k
2.5V
R28
825Ω
15
D1
SYNC ERR
PFC8574TS
16
8
20
3
R27D
33Ω
35 34 33 32 31
PBUS12
RXD12
TXD14
PBUS11
RXD11
PBUS13
RXD13
GND
P2
TXD8
GND
TXD15
PAT0
P7
NC
IN
PGA
TXD13
PBUS14
RXD14
PAT1
P6
NC
VCC
RXD15
PGA
P5
NC
PDADC
P3
PDSER
P2
SCRAM
P0
MSBINV
P4
NC
VSS
VDD
FAM
P1
VSS
11
RX_ER
8
4
3.3V
SCL
SDA
A0
A1
A2
WP
SDA
SCL
1
2
3
7
5
6
5
7
9
6
8
10
75
77
79
81
83
85
87
89
91
93
95
97
99
80
82
84
86
88
90
92
94
96
98
100
R38
4750Ω
C35
0.01μF
R40
4750Ω
R37
4750Ω
73
78
53
54
71
51
52
76
49
50
69
47
48
74
45
46
67
43
44
72
41
42
65
39
40
70
37
38
63
35
36
68
33
34
61
31
32
66
29
30
59
27
28
64
25
26
57
23
24
62
21
22
55
19
20
60
17
18
58
15
16
56
13
14
11
3
4
12
1
2
SCL SDA WP
PBUS8
PBUS9
PBUS10
PBUS11
PBUS12
PBUS13
PBUS14
PBUS15
PBUS0
PBUS1
PBUS2
PBUS3
PBUS4
PBUS5
PBUS6
PBUS7
D2
DATA GOOD
R29
825Ω
6
7
9
2
4
1
VCC
VSS
38
OE2
2A
OE1
1A
2274 TA02
R50
OPTIONAL
3
5
7
1
R39
1000Ω
2.5V
4
6 SDA
NC7WB66K8X
2B
1B
2 SCL
8
R48
OPTIONAL
3.3V
VCC
3.3V
R49
OPTIONAL
TYPICAL APPLICATIONS
GND
10
LTC2274
2274fb
LTC2274
PACKAGE DESCRIPTION
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-1728 Rev Ø)
0.70 p0.05
6.50 p0.05
5.10 p0.05
4.42 p0.05
4.50 p0.05
(4 SIDES)
4.42 p0.05
PACKAGE OUTLINE
0.25 p0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
6.00 p 0.10
(4 SIDES)
0.75 p 0.05
R = 0.10
TYP
R = 0.115
TYP
39 40
0.40 p 0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1 NOTCH
R = 0.45 OR
0.35 s 45o
CHAMFER
4.50 REF
(4-SIDES)
4.42 p0.10
4.42 p0.10
(UJ40) QFN REV Ø 0406
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 p 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
2274fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
39
LTC2274
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1993-2
High Speed Differential Op Amp
800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain
LTC1994
Low Noise, Low Distortion Fully Differential Input/
Output Amplifier/Driver
Low Distortion: –94dBc at 1MHz
LTC2215
16-Bit, 65Msps, Low Noise ADC
700mW, 81.5dB SNR, 100dB SFDR, 64-Pin QFN
LTC2216
16-Bit, 80Msps, Low Noise ADC
970mW, 81.3dB SNR, 100dB SFDR, 64-Pin QFN
LTC2217
16-Bit, 105Msps, Low Noise ADC
1190mW, 81.2dB SNR, 100dB SFDR, 64-Pin QFN
LTC2202
16-Bit, 10Msps, 3.3V ADC, Lowest Noise
140mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN
LTC2203
16-Bit, 25Msps, 3.3V ADC, Lowest Noise
220mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN
LTC2204
16-Bit, 40Msps, 3.3V ADC
480mW, 79dB SNR, 100dB SFDR, 48-Pin QFN
LTC2205
16-Bit, 65Msps, 3.3V ADC
590mW, 79dB SNR, 100dB SFDR, 48-Pin QFN
LTC2206
16-Bit, 80Msps, 3.3V ADC
725mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN
LTC2207
16-Bit, 105Msps, 3.3V ADC
900mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN
LTC2208
16-Bit, 130Msps, 3.3V ADC, LVDS Outputs
1250mW, 77.7dB SNR, 100dB SFDR, 64-Pin QFN
LTC2209
16-Bit, 160Msps, ADC, LVDS Outputs
1.45W, 77.1dB SNR, 100dB SFDR, 64-Pin QFN
LTC2220
12-Bit, 170Msps ADC
890mW, 67.5dB SNR, 9mm × 9mm QFN Package
LTC2220-1
12-Bit, 185Msps, 3.3V ADC, LVDS Outputs
910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN
LTC2224
12-Bit, 135Msps, 3.3V ADC, High IF Sampling
630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN
230mW, 73dB SNR, 5mm × 5mm QFN Package
LTC2249
14-Bit, 80Msps ADC
LTC2250
10-Bit, 105Msps ADC
320mW, 61.6dB SNR, 5mm × 5mm QFN Package
LTC2251
10-Bit, 125Msps ADC
395mW, 61.6dB SNR, 5mm × 5mm QFN Package
LTC2252
12-Bit, 105Msps ADC
320mW, 70.2dB SNR, 5mm × 5mm QFN Package
LTC2253
12-Bit, 125Msps ADC
395mW, 70.2dB SNR, 5mm × 5mm QFN Package
LTC2254
14-Bit, 105Msps ADC
320mW, 72.5dB SNR, 5mm × 5mm QFN Package
LTC2255
14-Bit, 125Msps, 3V ADC, Lowest Power
395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN
LTC2284
14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk
540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN
LTC2299
Dual 14-Bit, 80Msps ADC
230mW, 71.6dB SNR, 5mm x 5mm QFN Package
LTC5512
DC-3GHz High Signal Level
Downconverting Mixer
DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
LTC5515
1.5 GHz to 2.5GHz Direct Conversion Quadrature
Demodulator
High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator
LTC5516
800MHz to 1.5GHz Direct Conversion Quadrature
Demodulator
High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator
LTC5517
40MHz to 900MHz Direct Conversion Quadrature
Demodulator
High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator
LTC5522
600MHz to 2.7GHz High Linearity Downconverting
Mixer
4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz,
NF = 12.5dB, 50Ω Single-Ended RF and LO Ports
LTC5527
400MHz to 3.7GHz High Signal Level
Downconverting Mixer
4.5V to 5.25V Supply, 23.5dBm IIP3 at 1900MHz, ICC = 78mA,
Conversion Gain = 2dB
LTC5579
1.5GHz to 3.8GHz High Linearity Upconverting
Mixer
3.3V Supply, 27.3dBm OIP3 at 2.14GHz, Conversion Gain = 2.6dB at 2.14GHz
LTC6400-20
1.8GHz Low Noise, Low Distortion Differential ADC
Driver for 300MHz IF
Fixed Gain 10V/V, 2.1nV√Hz Total Input Noise, 3mm × 3mm QFN-16 Package
2274fb
40 Linear Technology Corporation
LT 0609 REV B • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
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www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2008