Signal chain basics: Understand spurious
signals in high-speed DACs
Here's how to develop tactics and techniques for troubleshooting this likely problem.
By Robert Keller
Systems and Applications Manager
Texas Instruments
In "Signal chain basics: Understand spurious signals in high-speed ADCs", we discussed approaches for tracking
down spurious signals in high-speed analog-to-digital converter (ADC) systems. In this article, we examine similar
techniques for high-speed digital-to-analog converter (DAC) systems.
There are two types of high-speed DACs: interpolating and non-interpolating (straight). Interpolating DACs,
described in "Signal chain basics: Using the digital features of high-speed DACs", typically contain digital signal
processing features such as interpolation, digital quadrature modulation, and internal phase-locked loops (PLLs).
Straight DACs simply convert digital values to an analog output.
Figure 1 shows a DAC signal chain in a radio application. There are several potential sources of spurious signals
from the DAC, each has distinct characteristics:
1) Digital interface
2) Input clock
3) PLL
4) Power supplies
5) Digital saturation
6) Improper output termination
Figure 1: Typical high-speed DAC signal chain.
DACs are characterized with both a continuous wave (CW) or modulated signal output (commonly a 3G or 4G
communication signal like WCDMA or LTE). Datasheets contain AC specifications listed in a table as well as output
spectral plots. Comparing against the spectral plots offers the most information for debugging system problems, as
each problem type has different frequency characteristics.
To debug a high-speed DAC, first verify error-free data input. Input interface problems are common and cause bit
errors, resulting in wideband noise. In a straight DAC this causes an elevated noise floor following a sin(x)/x
frequency response (figure 2). In an interpolating DAC, the noise spectrum is shaped by the internal digital
interpolation filters. This gives a distinctive output spectrum that matches the filter frequency response (figure 3).
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Figure 2: Output spectrum for a straight DAC with interface errors.
Figure 3: Output spectrum for an interpolating DAC with interface errors.
DACs such as TI’s DAC34SH84 (quad-channel, 16bit, 1.5 GSPS) include several features for easing design, validating
and monitoring the input interface. The DAC includes a programmable skew between clock and data with ~50 ps
increments to reduce input timing requirements. To validate, a test pattern from the digital source can be used to
identify specific error bits. Finally, the interface includes a parity bit for continuous interface monitoring during
operation.
Clock spurs are another common source of problems. Because the DAC sampling process acts like a mixer, spurs on
the clock input result in spurs at the DAC output. The frequency of spurious signals at the DAC output due to clock
spurs move 1:1 with input frequency.
This is easiest to see by generating a tone, recording the spur’s frequency, shifting the tone by a small amount (for
example, 100kHz), then measuring the frequency shift. Switching regulators can cause clock spurs offset from the
tone by a few 100kHz.
Another common clock problem is improperly setting the internal PLL, resulting in either unlocked PLL or elevated
phase noise.
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Nonlinear distortion generates output signal harmonics. Due to the DAC’s sampling nature, harmonics generated at
frequencies above the first Nyquist zone (0 – fSAMPLE/2) fold back into the Nyquist zone at the DAC output. While the
spur’s frequency can be easily calculated, you can identify the harmonic by observing the change between output
and input frequencies. Harmonics change in output frequency by:
Δf OUT = ±N × ΔfIN
where ΔfIN is the change in input frequency, N is the harmonic order, and ΔfOUT is the change in output frequency.
Two common causes of nonlinear distortion are digital saturation and improper output termination. Interpolating
DACs often have signal processing blocks with potential gain, causing signal clipping. Clipping generates a large
number of harmonics (figure 4).
Figure 4: DAC output spectrum with digital saturation.
In high-speed DACs, the output current is converted to voltage by the termination load. The datasheet contains
specifications for output compliance voltage, which is the acceptable voltage range at the DAC output pins.
Exceeding the compliance voltage specification, which can occur if the output-load impedance is too high, increases
distortion. Note that the impedance may be frequency-dependent, if for example it includes an analog filter and the
critical impedance is at the expected operating frequencies.
This is not a complete list of potential problems, but most issues found when debugging high-speed DAC systems
fall into one of these categories. The key is to track down the source by identifying the spurious signals’
characteristics. About the author
Robert Keller is the Systems and Applications Manager for High-Speed Data Converters. He has nine years
experience supporting high-speed products in wireless infrastructure communication, test and measurement, and
military systems. He received a B.A. in Physics and Mathematics from Washington University, St. Louis, and a Ph.D.
in Applied Physics from Stanford University. He has 10 US patents in networking and sensor applications.
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