EV2202 - USBid
advertisement
Part Number EV2202 Revision 1.0 - April 5, 2000 EV2202 EVALUATION BOARD Dual Gigabit Ethernet Transceiver Introduction The S2202 evaluation board provides a flexible platform for verifying the operation of the S2202 Dual Gigabit Ethernet Device. This document provides information on the S2202 evaluation board's contents and layout. It should be used in conjunction with the S2202 product data sheet. Contact your local AMCC field applications engineer or regional sales manager to discuss any questions or concerns you may have. EV2202 Kit Contents S2202 evaluation board EV2202 device specification (This document) Two minicoax cables (To loop back the clock in parallel loopback configuration) Board Description The top view of the S2202 evaluation board is shown in Figure 1. The high-speed differential LVPECL receive signals, (RXxP/N), and transmit signals, (TXxP/N), (where lower case "x" is A and B for each of two channels), are brought in and out on SMA connectors, as shown on the top and left edges of the board. The reference clock is brought in through the SMA connector labeled as REFCLK. Figure 1. S2202 Evaluation Board GND TXBP REFCLK VDD GND Applied Micro Circuits Corp. 6290 Sequence Dr. San Diego, CA 92121 S2202 Evaluation Board RCBP RCBN *ERRC KFLAGB DOUTB7 DOUTB6 DOUTB5 DOUTB4 DOUTB3 DOUTB2 DOUTB1 DOUTB0 EOFB RXAN S2202 AMCC RXBP 1 RXAP RESET LPENA LPENB MODE TMODE RATE CLKSEL SYNC LC BYP CMODE TESTMODE GND RESET FR SW TO DUT FR DIPSWITCH A TDO TCK TMS TDI TRS 1 2 3 4 5 6 7 1 2 3 4 OFF DNB KGENB DINB7 DINB6 DINB5 DINB4 DINB3 DINB2 DINB1 DINB0 TCLKB RCAP RCAN ERRA KFLAGA DOUTA7 DOUTA6 DOUTA5 DOUTA4 DOUTA3 DOUTA2 DOUTA1 DOUTA0 EOFA OFF "1" DOUTB3 DINB2 TCLKB DINB3 DIND0 DIND2 TESTMODE1 RXBN GND AMCC REFCLK(S) DINB7(S) GND TXBN I/P TXAN O/P TXAP DNA KGENA DINA7 DINA6 DINA5 DINA4 DINA3 DINA2 DINA1 DINA0 TCLKA TCLK0 GND "0" *ERRB in the data sheet is labeled as ERRC on the evaluation board. Note: Some pin names in the S2202 data sheet are labeled differently on the evaluation board. See Tables 1, 2 and 3. 1 Revision 1.0 - April 5, 2000 EV2202 – Dual Gigabit Ethernet Transceiver EVALUATION BOARD Electrical Connections Power Connections A terminal post is provided on the top edge of the board for the power and ground connections to the S2202 Dual Gigabit Ethernet Device. The S2202 voltage is specified at +3.3 V +/-5%. Parallel I/O Header Arrays Parallel input and output (I/O) signals are brought in and out on the connector banks on the right edge of the board. There is one connector bank for each channel (A and B). Tables 1 and 2 below show a list and description of the header array signals and SMA connectors for the S2202 evaluation board. Table 1. Header Array Signals Board Signal Name Data Sheet Signal Name Level I/O Description DINx[0:7] KGENx DNx DINx[0:7] DINx[8] DINx[9] TTL I Data In. Transmit Data for channels A and B. Parallel data on this bus is clocked in on the rising edge of TBCx (labeled as TCLKx on the evaluation board) or REFCLK. TCLKx TBCx TTL I Transmit Byte Clock. When TMODE is High, this signal is used to clock data on DINx[0:7], DINx[8] (labeled as KGENx on the evaluation board), and DINx[9] (labeled as DNx on the evaluation board) into the S2202. When TMODE is Low, TBCx (labeled as TCLKx on the evaluation board) is ignored. DOUTx[0:7] KFLAGx ERRx DOUTx[0:7] DOUTx[8] DOUTx[9] TTL O Data Out. Receive Data for channels A and B. Parallel data on this bus is valid on the rising edge of RBC1x (labeled as RCxP on the evaluation board) in full clock mode, and valid on the rising edge of both RBC1x (labeled as RCxP on the evaluation board) and RBC0x (labeled as RCxN on the evaluation board) in half clock mode. RCxP/N RBC1/0x TTL O Receive Byte Clock. Parallel receive data, DOUTx[0:7], DOUTx[8] (labeled as KFLAGx on the evaluation board), DOUTx[9] (labeled as ERRx on the evaluation board), and output COM_DETx (labeled as EOFx on the evaluation board) are valid on the rising edge of RBC1x (labeled as RCxP on the evaluation board) when in full clock mode, and valid on the rising edge of both RBC1x (labeled as RCxP on the evaluation board) and RBC0x (labeled as RCxN on the evaluation board) in half clock mode. EOFx COM_DETx TTL O Comma Detect. A High on COM_DETx (labeled as EOFx on the evaluation board) indicates that a valid K28.5 has been detected and is present on the parallel data outputs DOUTx[0:7], DOUTx[8] (labeled as KFLAGx on the evaluation board) and DOUTx[9] (labeled as ERRx on the evaluation board). TCLKO TCLKO TTL O Transmit Clock Out. TTL output clock at the parallel data rate. This clock is provided for use by upstream circuitry. TDO TDO TTL O Test Data Out. JTAG data output. Can be high impedance under JTAG controller command. TDI TDI TTL I Test Data In. JTAG data input. 2 Revision 1.0 - April 5, 2000 EV2202 – Dual Gigabit Ethernet Transceiver EVALUATION BOARD Table 1. Header Array Signals (Continued) Board Signal Name Data Sheet Signal Name Level I/O Description TMS TMS TTL I Test Mode Select. Enables JTAG testing of device. TCK TCK TTL I Test Clock. JTAG test clock. TRS TRS TTL I Test Reset. Resets JTAG test state machine. FR SW Provided with a jumper to TO DUT to enable the push-button RESET on the evaluation board. TO DUT Provided with a jumper to FR SW to enable the push-button RESET on the evaluation board. FR DIPSWITCH Not used for this device. REFCLK(S) DNB7(S) Not used for this device. DOUTB3 DINB2 DINB3 DIND0 DIND2 Not used for this device. TESTMODE1 TESTMODE1 TTL I Test Mode Control. Provided with a jumper to logic 0 for normal operation. Level I/O Description Table 2. SMA Connectors Board Signal Name Data Sheet Signal Name RXxP/N RXxP/N Diff. LVPECL I Receive Serial Data for channels A and B. RXxP is the positive input, RXxN is the negative input. Internally biased to VDD -1.3 V for AC coupled applications. TXxP/N TXxP/N Diff. LVPECL O Transmit Serial Data for channels A and B. High-speed serial outputs. REFCLK REFCLK TTL I Reference Clock. Clock used for the transmit VCO and frequency check for the clock recovered from the receiver serial data. 3 EV2202 – Dual Gigabit Ethernet Transceiver Revision 1.0 - April 5, 2000 EVALUATION BOARD DIP Switches The S2202 evaluation board is provided with DIP switches at the bottom edge of the board to control the static functions of the on-board device. The DIP switch definitions are outlined in Table 3. Moving the switch to the "ON" position creates a logic 1 (High), moving it away from the "ON" setting creates a logic 0 (Low). Table 3. DIP Switch Definitions Board Signal Name Data Sheet Signal Name Level I/O Description RESET RESET TTL I Not used for this device. Use push-button RESET instead. LPENA LPENA TTL I Loopback Enable for channel A. When Low, input source is the high-speed serial input for each channel. When High, the serial output for each channel is looped back to its input. LPENB LPENB TTL I Loopback Enable for channel B. When Low, input source is the high-speed serial input for each channel. When High, the serial output for each channel is looped back to its input. TTL I Not used for this device. MODE TMODE TMODE TTL I Transfer Mode Control. When TMODE is Low, REFCLK is used to clock data on DINX[0:7], DINx[8] (labeled as KGENx on the evaluation board) and DINx[9] (labeled as DNx on the evaluation board), into the S2202. When TMODE is High, the TBCx (labeled as TCLKx on the evaluation board) inputs are used to clock data into their respective channels. RATE RATE TTL I When Low, the S2202 operates with the serial output rate equal to the VCO frequency. When High, the S2202 operates with the VCO internally divided by 2 for all functions. CLKSEL CLKSEL TTL I REFCLK Select. This signal configures the PLL for the appropriate REFCLK frequency. When CLKSEL = 0, the REFCLK frequency equals the parallel word rate. When CLKSEL = 1, the REFCLK frequency is half the parallel data rate. SYNC TESTMODE2 TTL I Test Mode Control. Keep Low for normal operation. TTL I Not used for this device. LC BYP CMODE CMODE TTL I Clock Mode Control. When Low, the rate of the parallel output clock RBC1/0x (labeled as RCxP/N on the evaluation board) is equal to half the data rate. When High, the rate of the parallel output clock RBC1/0x (labeled as RCxP/N on the evaluation board) is equal to the data rate. TESTMODE TESTMODE TTL I Test Mode Control. Keep Low for normal operation. 4 Revision 1.0 - April 5, 2000 EV2202 – Dual Gigabit Ethernet Transceiver EVALUATION BOARD Parallel Loopback Test Setup Typical tests performed with the S2202 evaluation board are Bit Error Rate (BER) testing and jitter testing. In each case, it is easiest to configure the evaluation board for serial input and output (I/O), looping back the parallel I/O with jumpers. The serial I/O (parallel loopback) configuration is shown in Figure 2 and is described below. DIP switch settings for parallel loopback, where Low = logic 0 and High = logic 1, are: Signal Name: DIP Switch Setting: RESET Do not use this DIP Switch. Use the push button Reset. LPENA Low LPENB Low TMODE High RATE High or Low (determined by the desired serial data rate) CLKSEL High or Low (determined by the desired reference clock rate) SYNC Low CMODE High TESTMODE Low In order to configure the board for parallel loopback, the parallel input data must be clocked into the device with the TBCx (labeled as TCLKx on the evaluation board) input clocks as shown in Figure 2. This clock is provided by looping the RBC1x (labeled as RCxP on the evaluation board) output clock back into the respective TBCx (labeled as TCLKx on the evaluation board) input with one of the minicoax cables that are provided in the EV2202 kit. These cables need only be connected for the channel(s) under test. Figure 2. Parallel Loopback Configuration GND TXBP REFCLK VDD GND Applied Micro Circuits Corp. 6290 Sequence Dr. San Diego, CA 92121 S2202 Evaluation Board RCBP RCBN *ERRC KFLAGB DOUTB7 DOUTB6 DOUTB5 DOUTB4 DOUTB3 DOUTB2 DOUTB1 DOUTB0 EOFB RXAN S2202 AMCC RXBP 1 RXAP RESET LPENA LPENB MODE TMODE RATE CLKSEL SYNC LC BYP CMODE TESTMODE GND RESET FR SW TO DUT FR DIPSWITCH A TDO TCK TMS TDI TRS 1 2 3 4 5 6 7 1 2 3 4 OFF DNB KGENB DINB7 DINB6 DINB5 DINB4 DINB3 DINB2 DINB1 DINB0 TCLKB RCAP RCAN ERRA KFLAGA DOUTA7 DOUTA6 DOUTA5 DOUTA4 DOUTA3 DOUTA2 DOUTA1 DOUTA0 EOFA OFF "1" DOUTB3 DINB2 TCLKB DINB3 DIND0 DIND2 TESTMODE1 RXBN GND AMCC REFCLK(S) DINB7(S) GND TXBN I/P TXAN O/P TXAP DNA KGENA DINA7 DINA6 DINA5 DINA4 DINA3 DINA2 DINA1 DINA0 TCLKA TCLK0 GND "0" *ERRB in the data sheet is labeled as ERRC on the evaluation board. Note: Some pin names in the S2202 data sheet are labeled differently on the evaluation board. See Tables 1, 2 and 3. 5 EV2202 – Dual Gigabit Ethernet Transceiver Revision 1.0 - April 5, 2000 EVALUATION BOARD Schematic and Bill of Materials The S2202 evaluation board schematic is shown in Figure 3. The power and ground connections for the S2202 evaluation board are shown in Figure 4. The bill of materials for the S2202 evaluation board is provided in Tables 4 and 5. Figure 3. S2202 Evaluation Board Schematic 6 EV2202 – Dual Gigabit Ethernet Transceiver Revision 1.0 - April 5, 2000 EVALUATION BOARD Figure 4. S2202 Evaluation Board Power and Ground Connections 7 Revision 1.0 - April 5, 2000 EV2202 – Dual Gigabit Ethernet Transceiver EVALUATION BOARD Table 4. S2202 Evaluation Board Bill of Materials Quantity Component Value Designators 8 0.1 µF 1 0.022 µF 12 1 kΩ R2 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 1 51 Ω R3 13 100 Ω R1 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 2 270 Ω R16 R17 1 HD1 HD7 1 HD1T HD2 1 HD5D HD1 1 HD11D_1 HD4 1 HD12D HD3 2 HD13D HD5 HD6 1 PB 1 S2202 9 SMA 1 SW-DIP4 SW2 1 SW-DIP7 SW1 C1 C2 C3 C4 C5 C6 C7 C8 C9 PB1 U1 SMA1 SMA2 SMA3 SMA4 SMA5 SMA6 SMA7 SMA8 SMA9 Table 5. S2202 Power and Ground Bill of Materials 8 Quantity Component Value Designators 30 0.1 µF C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 8 10 µF C58 C59 C60 C61 C62 C63 C64 C65 27 100 pF C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 6 BLM11A60 1 S2202_PWR U1 1 TB-2 TB1 L1 L2 L3 L4 L5 L6 Revision 1.0 - April 5, 2000 EV2202 – Dual Gigabit Ethernet Transceiver EVALUATION BOARD Ordering Information PREFIX DEVICE EV - Evaluation Board 2202 PACKAGE TB - 156 TBGA XX XXXX XX Prefix Device Package Applied Micro Circuits Corporation 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 — (800) 755-2622 — Fax: (858) 450-9885 http://www.amcc.com AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FO R USE IN LIFE-SUPPO RT APPLICATIO NS, DEVICES OR SYSTEMS OR O THER CRIT ICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright © 2000 Applied Micro Circuits Corporation. 9
