University of Wisconsin - Madison
ECE/Comp Sci 352 Digital Systems Fundamentals
Charles R. Kime
Section 2 – Fall 2001
Logic and Computer Design Fundamentals
Chapter 3 – Combinational
Logic Design – Part 5
Charles Kime & Thomas Kaminski
© 2001 Prentice Hall, Inc
Binary Multiplication
S The binary digit multiplication table is
trivial:
(a × b)
b=0
b =1
a=0
0
0
a=1
0
1
S This is simply the Boolean AND
function.
S Form larger products the same way we
form larger products in base 10.
Logic and Computer Design Fundamentals
© 2001 Prentice Hall, Inc
Chapter 3-Part 5 2
1
Review of Decimal Multiplication
S Perform base 10 multiplication by:
• Computing partial products, and
• Justifying and summing the partial
products.
S To compute partial products:
• Multiply the row of multiplicand digits by
each multiplier digit, one at a time.
S Partial product formation here require
carries to be added – more complex than
binary
Logic and Computer Design Fundamentals
© 2001 Prentice Hall, Inc
Chapter 3-Part 5 3
Example: (237 x 149) Base 10
S Partial products are:
237 × 9, 237 × 4,
and 237 × 1
S Note that the partial product
summation for n digit, base 10
numbers requires adding up
to n digits (with carries). + 2
S Note also n x m digit
3
multiply generates up
to an m+n digit result.
Logic and Computer Design Fundamentals
© 2001 Prentice Hall, Inc
2
3
7
×
1
4
9
2
1
3
3
9
4
8
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3
7
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-
5
3
1
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Chapter 3-Part 5 4
2
Binary Multiplication Algorithm
We compute base 2 multiplication by:
Computing partial products, and
Justifying and summing the partial products. (same as
decimal!)
To compute partial products:
Multiply the row of multiplicand digits by each multiplier
digit, one at a time.
With binary numbers, partial products are very simple!
They are either:
• all zero (if the multiplier digit is zero), or
• the same as the multiplicand (if the multiplier digit is one).
Note: No carries are added in partial product formation!
Logic and Computer Design Fundamentals
© 2001 Prentice Hall, Inc
Chapter 3-Part 5 5
Example: (101 x 011) Base 2
S Partial products are: 101 x 0, 101 x 1,
and 101 x 1
1 0
S Note that the partial product × 0 1
summation for n digit, base
1 0
2 numbers requires adding
1 0 1
up to n digits (with carries)
0 0 0
in a column.
0 0 1 1 1
S Note also n x m digit
multiply generates up to an m + n digit
result (same as decimal).
Logic and Computer Design Fundamentals
© 2001 Prentice Hall, Inc
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1
1
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Chapter 3-Part 5 6
3
Multiplier Boolean Equations
S We can also make an n x m "block" multiplier
and use that to form partial products.
S Example: 2 x 2 The logic equations for each
partial-product binary digit are shown below:
b1
b0
S We need to "add" the columns
X
a
a0
1
to get the product bits P0,
(a0 b1) (a0 b0)
P1, P2, and P3.
+
(a1 b1) (a1 b0)
S Note that some
P2
P1
P0
P3
columns may generate carries.
Logic and Computer Design Fundamentals
© 2001 Prentice Hall, Inc
Chapter 3-Part 5 7
Multiplier Arrays Using Adders
S An implementation of the 2 x 2
multiplier array is
shown (Text Fig. 3-33):
b1
b0
a0
a1
A B
HA
Co S
A B
HA
Co S
P3
Logic and Computer Design Fundamentals
© 2001 Prentice Hall, Inc
P2
P1
P0
Chapter 3-Part 5 8
4
Multiplier Using Wide Adders
S A more "structured" way to develop an n × m
S
S
S
S
multiplier is to sum partial products using adder
trees.
The partial products are formed using an n × m
array of AND gates.
Partial products are summed using m – 1 adders
of width n bits.
Example: 4-bit by 3-bit adder.
Text Figure 3-34 shows a 4 × 3 = 12 element
array of AND gates and 2 4-bit adders
Logic and Computer Design Fundamentals
© 2001 Prentice Hall, Inc
Chapter 3-Part 5 9
Cellular Multiplier Arrays
Another way to imple-
Column Sum from above
b[ k ]
ment multipliers is to Cell [ j , k ]
use an n × m cellular array
a[ j ]
structure of uniform
elements as shown:
pp [ j , k ]
Each element computes
A B
Co Ci
FA S
a single bit product
Carry [ j , k ]
Carry [ j, (k - 1)]
equal to ai·bj, and implements a
Column Sum to below
single bit full adder
Logic and Computer Design Fundamentals
© 2001 Prentice Hall, Inc
Chapter 3-Part 5 10
5
BCD Addition
S A four-bit binary adder, with a correction circuit, can be
used for BCD digit addition.
S For the correction circuit:
• The BCD code is correct if the sum is 9 or less
• The BCD code is incorrect:
S if the adder output is 10, 11,12,13,14,15,
or
S if the 4-bit adder produces a carry out
• We correct the sum by subtracting 10 (usually by the equivalent
addition of 6 modulo 16)
S The Boolean equation with value 1 for doing a correction:
C = K + Z1 Z 3 + Z 2 Z 3
S If C = 1, 0110 is added; else 0000 is added. This can be
done by adding 0 C C 0. Also C is the Output carry.
Logic and Computer Design Fundamentals
© 2001 Prentice Hall, Inc
Chapter 3-Part 5 11
BCD Addition (Continued)
S The resulting circuit (Figure 3-35):
Logic and Computer Design Fundamentals
© 2001 Prentice Hall, Inc
Chapter 3-Part 5 12
6