Next-Generation
Compact Modeling*
Robert W. Dutton and Chang-Hoon Choi
Stanford University
Motivation--Moore's Law scaling has led to ultra-short channel length
devices that, while giving multi-GHz performance, present a host of new
modeling challenges, especially for analog devices in SoC integration.
There are a range of "other" issues that face compact modeling of nanometer scale technology, including parasitic effects related to:
gate leakage,
substrate coupling
thermal limitations
There are also issues of intrinsic device scaling; high-level language (HLL)
specifications for models that facilitate model portability is one example.
*Support from SRC(TI); CIS(Infineon, Philips); MARCO(MSD)
Outline*
• Intrinsic Devices:
– Challenges of MOS Scaling
• Gate Current, QM Effects…
(C.-H. Choi, PhD 2002)
– RF Modeling
• Non-Quasi-Static & Substrate Effects
(J. Jang PhD 2004)
• Thermal Noise (T. Oh, PhD 2004)
– Thermal Modeling
• Self Heating in Nano-Devices (E. Pop)
• RF Power MOS (C. Ito)
• Model Portability
• Summary and Discussion
*PhD Theses and related publications: www-tcad.stanford.edu
Scaling Challenges of CMOS
silicide
side- Poly Gate sidewall
wall
extrinsic SDE o channel h SDE extrinsic
alo
l
implant
ha
drain
source
p-well implant
substrate
Cross-section of a 90nm N-channel MOS transistor, including details of gate,
sidewalls and substrate doping profiles (SDE, channel/well implants, halo doping)
Threshold, Sub-Threshold & Ion/Ioff
Drain Current (A/um)
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
10-13
10-14
Vds=3.0V
L=0.1µm
=50mV
Ion
Ion/Ioff “ratio”
(performance
parameter)
L=1.2µm
L=0.25µm
Ioff
sub-threshold
slope (m)
-0.5
0.0
0.5
1.0
tox=4nm
1.5
2.0
Gate Voltage (V)
Semi-Log plot of Drain Current (Ids) versus Gate Voltage (Vgs) with Drain
Voltage (Vds) as a parameter for three channel length NMOS devices.
Mapping Device Physics to Compact
Models
Gate Effects:
CG, IG, QM
Source
Substrate
Effects:
CA, CSW RS
Gate
intrinsic channel
Intrinsic MOS:
Cox, Vth, µ, νsat
Drain
Bulk
Body Effects:
Vth(Vbs), Sub-Vth
Bulk Currents:
DIBL, BTBT
Intrinsic MOS, Gate, Body/Bulk and Parasitic Substrate Capacitance/Resistance
Effects
Channel Charge and Carrier Mobility!
Ichannel ∝ charge
∝
Cox (Vgs - Vth)
*
carrier velocity
* Elateral
µchannel
εGate
Cox =
xGate
x Depletion (Vgs )
1
1
1
1
=
+
=
+
CG (Vgs ) Cox
εSilicon
Cox CDepletion (Vgs )
1
µchannel
1
= ∑
ith scattering µi
mechanisms
First-order model of how MOS inversion layer channel current (Ichannel) depends of
gate-induced charge and carrier velocity. The physical parameters are CG and µchannel.
€
Scaling of MOS Performance
Relative Device Performance
100
Conventional Bulk CMOS
SOI
<1.2X Bulk
Strained Si/SiGe <1.6X Bulk
Double-Gate
<1.8X Bulk
10
Lithographyenabled progress,
exponential
Device/materialenabled
progress,
incremental
1
| | | | | | | | | | | | |
1984
1988
1992
1996 2000
2004
2008
2012 (Year)
Mobility Degradation for High-k Gate Stacks
•
Various mechanisms responsible
for degradation:
– Remote polar optical phonon
scattering
– Remote charge scattering
– Remote surface roughness
– Phase separation
•
Universal mobility curve
– Effective mob. dep. on effective field;
good for acoustic phonon scatt. and
surface roughness scatt.
– Deviation at low inversion due to
Coulomb scatt. for SiO2
– More severe deviation for high-k
• Aggravated surface roughness
• Stronger Coulombic scatt. at low and
medium inversion
+ Gate Tunneling…
Saito et. al IEDM 2003
Poly-Gate and QM Effects
Ideal C-V (see equation in previous slide)
measured CV
classical model
QM correction model
180
160
poly
depletion
Cg (pF)
140
120
QM effects
100
80
60
40
20
0
-4
-3
-2
-1
0
1
2
3
Vg (V)
Measured and simulated curves of MOS gate capacitance vs. gate voltage for NMOS,
poly-silicon gate, 2nm oxide thickness. Curves compare impact of QM effects
QM Effects on Channel Charge
classical electron distribution
E le c tr o n en e rgy (m e V)
Si surface
electron distribution
for QM model in E0 state
20
E’0
conduction band
E1
0
E0
40
80
120
Distance from surface
(Å)
-20
Surface region of bulk MOS device that shows: well potential created by the conduction
band energy (- * -); discrete energy levels imposed by QM (E0, E1…); electron
distribution associated with E0 level; electron distribution for classical theory (- - -)
QM “Poly Depletion”
e pile-up
QM model
Classic
electrons
n=2x10
20
/cm 3
quantum-well
n~0
n-poly
ox.
P-Si
Electron distributions in the n-type poly-silicon gate of an NMOS transistor, based
on classical theory versus that for a quantum-based (QM) solution for charge. The
peak region shows a “QM depletion” resulting in Vth and C-V shifts
Implications of QM Poly Depletion
(Fully Depleted Double-Gate-SOI)
Poly-gate
Poly-gate
2.8x1020/cm3
2.2x1020/cm3
2.5x1020
1.9x1020
2.2x1020
1.0x1020
1.0x1020
<1.0x1019
<1.0x1019
S
Electron contour for Vd=0V
D
S
D
Electron contour for Vd=1V
2D simulations of QM poly depletion effects for two drain bias conditions.
Results show significant gate depletion (left-side) and lateral effects that
influence drain-induced barrier lowering (right-side)
Threshold and Sub-Threshold Effects
0.01
L=20nm, tox=1nm DG SOI
1E-3
0.45
1E-4
Cg (fF/um)
Ids (A/um)
0.50
0.40
0.35
0.30
0.25
with poly QM effects
without poly QM
0.20
0.15
-1.0
-0.5
0.0
0.5
Vg (V)
1.0
1.5
with poly QM
Vds=1V
0.1V
1E-5
1E-6
1E-7
1E-8
w/o poly QM effects
1E-9
1E-10
-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0
Vgs (V)
C-V and I-V characteristics for a 20nm channel length DG SOI transistor,
comparing QM effects in the poly gate region with idealized (metal-like) gate.
Gate Current (Tunneling) vs. tox
2
)
+
0
Gate Current (A/cm
10
n diode
source
grounded
12.5Å
15Å
10
-2
10
-4
10
-6
18.2Å
Jp
10
-8
-1
-0.5
0
0.5
1
1.5
Gate Bias (V)
Simulated and measured data for gate current in an MOS capacitor as a function
of gate oxide thickness using NEMO; data provided by Hewlett-Packard.
Serious Limits to Scaling tox
160
symbols: measured
lines: modeling
140
tox=1.8nm
Cg (pF)
120
100
80
tox=1.5nm
60
40
20
0
-3
tox=1.3nm
-2
-1
0
1
2
Vg (V)
Measured and equivalent circuit simulations of imaginary component of input
admittance, large area MOS capacitor structure with oxide thickness as parameter.
Drain Current with Isub
• Distorted drain current (Id) from the real drain current (Id0)
due to gate current (Ig): Id0=Id+0.5Ig (Zeitzoff, EDL’03)
• But, note that Id0=Id+0.5(Ig-Isub) in the presence of Isub
Correction of Drain Current
• Over-estimation of corrected drain current (Id0) for
Id0=Id+0.5Ig expression
• New expression:Id0=Id+0.5(Ig-Isub) in the presence of Isub
Correction of Charge-Pumping Current
• Measurement of true inversion charge (Ninv) based on device symmetry
(Keber, VLSI tech.’03)
• Elimination of Ntun from Ninv for high-K or thin oxide
Inversion charge pumping
Ninv=2NICP_b-NICP_a
Modified Ninv
Ninv=2NICP_b-NICP_a-Ntun
Where DC values of Ntun are
used (Masson et. al 1999)
Small-Signal Modeling of RF
MOSFET
Jaejune Jang
PhD 2004
Center for Integrated Systems
Stanford University
Non-Quasi-Static Effect
Quasi-Static
Non-Quasi-Static
Source: Ronald van Langevelde, Philips Research Laboratories
• Quasi-Static is when each terminal responds instantaneously to
applied signal
• If switching time of vg is compatible with transit time of inversion
charge, QS approximation fails
NQS Effect on Cggeff and Gggeff
VG = 3V, VD = 0 V
Cggeff
1
10
Gggeff
0
fNQS
0.9
0.8
)
z
H
0
1
@
C
(g
xg
a
m
/ g
0.7
fNQS
10
-5
10
-10
10
-15
10
-20
~f2
0.6
0.5
| g
gg
|
L=0.3um
L=0.6um
L=1.2um
L=2.5um
L=10um
L=50um
0.4
g
C 0.3
0.2
0.1
0
5
10
10
6
10
7
8
10
Frequency (Hz)
10
9
10
10
L=0.3um
L=0.6um
L=1.2um
L=2.5um
L=10um
L=50um
10
2
10
4
6
10
Frequency (Hz)
10
8
10
10
• Long channel device falls off at lower frequencies
• Gggeff ~ f2: directly proportional to gate induced noise
• fNQS is defined as a frequency when NQS start
Bias Dependency of fNQS
VDS = 0  Leff_gs = Leff_gd
fNQS(Cgs) = fNQS(Cgd)
Leff _ gs ≈ L ⋅
Leff _ gd ≈ L ⋅
C gs
C gs + C gd
C gd
C gs + C gd
VDS > 0  Leff_gs > Leff_gd
fNQS(Cgs) << fNQS(Cgd)
f NQS
 µ (VGS − VT ) 
= n

2
 2πLeff

f NQS
 vsat 
= n

2
π
L
eff 


 Long Channel
 Short Channel
• Leff is determined by charge sharing b/w source and drain
• Bias dependency of fNQS is primarily function of Leff ,
mobility (µ) and, saturation velocity (vsat)
ygs and ygd
G
Cgs
Cgd
ymvgs
rgd
S
-ysd
ymbvbs
D
-ybs
ymxvgb
-ygb
rgd
rgs
• ygs and ygd can be represented as
series RC
• Cgsrgs/Cgdrgd determines fNQS
-ybd
VGS
B
VDS
L = 1.2 um (measured)
Capacitance vs. Channel Length
@ 1MHz
L = 10 um
0.45
L = 0.3 um
20
0.4
10
0.35
0
0.3
y
x
C
) -10
V
(
Cg -20
/ g
C
ss
C
sd
C
sg
C
0.15
C
ss
C
sd
C
sg
C
Cxx/Cgg
Cxx/Cgg
)
V 0.25
(
Cg 0.2
/ g
sb
y
x
sb
C -30
0.1
-40
0.05
-50
0
-0.05
0
0.5
1
1.5
V (V)
GS
V
GS (V)
2
2.5
3
-60
0
0.5
1
V
1.5
(V)
2
2.5
3
GS
VGS (V)
• All 16 capacitances agree well with charge-based capacitances
for long channel device
• Short channel capacitances show quite different behavior
• This is due to existence of substrate resistance (Rsub)
Impact of Rsub on Terminal Admittance
G
Cgs
(gm-jwCm)vgs
Cgd
Csdeff
Rsub g mb
= Csd +
Cbd
2 2
2
1 + ω RsubCbb
g sdeff
2
ω 2 Rsub
g mb
= g sd +
CbbCbd
2 2
2
1 + ω RsubCbb
gsd
S
D
Csd
gmbvbs
Cgb
Cbs
B
Rsub
ib
B’
Cbd
As L decreases, Rsub and gmb
increase
• Rsub is amplified through gmb
• Impacts following y-parameters (ydd, yds, ydb, ydg,
yss, ysg, ysd, and ysb )
Bias Dependency of Substrate Network
Saturation Region
vd
vs
rs_d
Cs_s
Cs_d
rs_s
• It’s been reported that substrate network is bias independent  not true
• Cs_s > Cs_d & rs_s < rs_d in saturation region
- Surface area of effective electrode is bias dependent due to charge sharing
ybs & ybd
G
rgs
ymvgs
rgd
• Csub and Rsub is a strong
function of bias
• Cbs and Cbd are also strongly
bias dependent
S
-ysd
ymbvbs
D
Cbs
Cgs
Cgd
Cbd
Cbs
rs_s
Cs_s
-ygb
B
rs_d
Cbd
Cs_d
VGS
VDS
Noise Analysis of deepsubmicron MOSFETs
Tae-young Oh
PhD 2004
Center for Integrated Systems
Stanford University
MOS Channel Length and Excess Noise
 Higher speed devices offer great promise for RF
Noise Parameters (no unit)
However, the changes in intrinsic noise of scaled
MOS devices is not clearly understood
7
Uncertain!
• The amount and source for this excess
noise were still uncertain
6
5
4
• High electric field in short channel MOS
device should have relation with this
Drain Noise excess noise
- Simulation has to handle this carefully
(Drift-Diffusion vs. Hydro-Dynamic models)
Gate Noise
3
2
1
0.1
1
Channel Length
µm)
(
10
Channel Length vs. Drain Noise Parameters
 PMOS Transistor
Drain Noise Parameter
Drain Noise Parameter
 NMOS Transistor
3.2
3.2
Hydrodynamic 2.5GHz
Hydrodynamic 1MHz
Drift-Diffusion 2.5GHz
Drift-Diffusion 1MHz
2.8
2.4
2.0
2.4
•Noise
increases with reduced L
2.0
•Modeling
of Carrier Transport
1.6
very1.2important
1.6
1.2
0.8
0.8
Classical Limit
0.4
(Van der Ziel)
0.4
0.0
Hydrodynamic 2.5GHz
Hydrodynamic 1MHz
Drift-Diffusion 2.5GHz
Drift-Diffusion 1MHz
2.8
0.0
0.1
1
10
ChannelLength
Lengthµm)
(
Channel
(µm)
Bias Condition : Vg =1.08 V, Vd=1.2 V
0.1
1
10
Channel Lengthµm)
(
Bias Condition : Vg =-1.07 V, Vd=-1.2 V
Measurement vs. Modeling--0.18µm
/Hz)
Drain Current Noise (A
0.18 µm Channel Length MOS--Measurement and
Simulation at 5 GHz (Data from Philips (Scholten, IEDM 02))
1.0x10-23
2
2
Gate Current Noise (A
/Hz)
10-20
10-21
10-22
10-23
0.2
Measured
Hydrodynamic
0.4
0.6
0.8
1.0
1.2
Vgs(V)
1.4
1.6
Measured
Hydrodynamic
1.0x10-24
1.8
0.4
0.6
0.8
1.0
1.2
Vgs(V)
1.4
1.6
1.8
Two-Lump Impedance Field Model
L’
xL’
Linear
Saturation
Current Injection
iin
RS
1/gm
2
iout
-
Sid = ∇Ak Sin
gmVgs
RL
Vgs
+
€
First-Order View of Impedance Field
L
xL’
L’(1-x)
L’
A(x) =
RS
RS +
€
1
gm
=
x
1− x
x
1− x
Space
Charge
x
≈
≈x
+ 1− x x + (1− x)
Comparison of A(x)--1µm vs 0.18µm
L=1µm
A (no unit)
1.0
A (no unit)
1.0
0.8
0.8
0.6
L=
0.18µm
0.6
0.4
0.4
0.2
0.0
-0.6
Hydronynamic
Drift-Diffusion
-0.4
-0.2
0.0
0.2
Positionµm)
(
0.4
0.6
0.2
Hydronynamic
Drift-Diffusion
0.0
-0.15 -0.10 -0.05
0.00
0.05
Positionµm)
(
•Effects on noise in short-channel devices more
pronounced
•Field-effects impact source-end noise, the most
critical area base on impedance field analysis
•Clear differences between Drain- and Gatecurrent noise contributions
0.10
0.15
Gate Current Noise--Short Channel MOS
µ mHz)
Contribution to Gate Noise /(A
• 0.18 µm channel length. Vds = 1.8 V f=5GHz
2.0x10-25
Gate Noise
2
Hydrodynamic
Drift-Diffusion
gate
1.5x10-25
1.0x10-25
Hot Carriers
5.0x10-26
0.0
-0.15
drain
source
-0.10
-0.05
0.00
0.05
Positionµm)
(
0.10
0.15
• Noise from high energy carriers has
direct impact on gate noise in short
channel MOS devices.
Self-Heating and Scaling of
Silicon Nano-Transistors
Eric Pop
PhD Orals 2004
Center for Integrated Systems
Stanford University
2-D: Thin Body SOI (Lg = 18 nm)
Mesh
Engineer to ITRS Specs:
LG=18 nm, tSI=4.5 nm, tOX=1 nm
NSD=1e20 cm-3, NCH=1e15 cm-3
ION=1000 µA/µm, IOFF=1 µA/µm
ΦGATE=4.53 eV (Mo), VDD=0.8 V
E-field
if W/L = 4 then Nelec ~ 2500 total!
Current
MONET*
J·E
(no Poisson)
*nanoheat.stanford.edu
Ultra-Thin Body SOI Scaling
intrinsic
baseline scaling:
Intel DST/SOI Transistor (IEDM 2001)
Rox = (Ri + tox/kox)/A
Ri = 2x10-8 m2K/W
Rco = 6.75x10-9 m2K/W
other  R = L/(kA)
Lex ~ Lg/2
Lsd ~ Lg
tsi ~ Lg/4
tsd ~ 2tsi
W ~ 3Lg
Aco ~ 2LgxLg
extrinsic:
link-up (Lex)
elevated S/D (Rsd)
other parameters:
(Ion, Vdd, tox) from ITRS
Eric Pop, Stanford PhD 2004
Thermal Modeling for SOI
Drain T Rise (K)
Stanford--E. Pop et al
(IEDM 2003)
double Lex = Lg  T ↑
low power
increase tsd = 3tsi  T ↓
halve Rco  T ↓
Gate Length Lg (nm)
• “Baseline” (ITRS power scaling): tsd=2tsi, Lex=Lg/2
• “Low power” case uses proposed quadratic power
scaling guidelines--reduce power, consistent with
volume
Proposed Power (I·V) Scaling
Proposed quadratic power scaling
Q = I ⋅ V = −0.17 L2g + 27.5 Lg
(Lg in nm)
•
•
•
•
ITRS power scaling non-uniform
Quadratic scales power closer with device dimension (and volume) scaling
Device temperatures near-isothermal
250 W/m power budget  Vdd = 0.25 V @ Ion = 1000 A/m
Stanford--E. Pop et al
(IEDM 2004)
Bottom-Line:
GOI can achieve lower delays;
improved drive current results
in lower heat generation
Intrinsic Delay (ps)
SOI-GOI Gate-Delay Comparisons
tsd = ntsi
n = 1... 5
Gate Length Lg (nm)
• Ge-O-I  assume tGe = 3/4tSi where tSi = Lg/4
• Si more kthin reduction due to larger phonon mean free path
• Ge has 2x mobility advantage, 40% lower Vdd
• Delay not lowered for S/D raised beyond ~ 3 x tfilm
Proposed Methodology*
(RF Power MOS Devices)
• Minimize fabricationcharacterization time by using
device simulation
• Generate table-based model from
device simulation for use in
circuit simulation
• Resulting model:
– “Black box” model
– Easy enough to generate for
quick evaluation of design
changes
*C. Ito et al, Title, SISPAD 2004
This work
Device
Fabrication
Process
Simulation
Measurements
Device
Simulation
DC, AC
parameters
Model
Extraction
Model
Extraction
Circuit
Simulation
RF Operation Metrics: Power Gain, Efficiency,
Gain Compression, Intermodulation, etc.
Thermal Characteristics
(Simulation Results)
• RF power amplifiers require temperature-dependent models
• Implemented using several tables extracted at different temperatures
• Characteristics for arbitrary temperatures may be linearly interpolated
between tables
DC Characteristics
(Model vs. Measurements*)
• Isothermal (pulsed) currentvoltage (IV) measurements
and simulations
• IV characteristics match well
between model and
measurement
• Small discrepancy possibly
due to differences between
simulation doping profile
and actual device profile
*Infineon Device
Methodology for Modeling
• Compact models are becoming more
abundant and complex
• Implementation is becoming bottleneck
and potential weak link
• Cross-platform model portability is
important to technology deployment
• HLD Languages (Verilog/VHDL…)
offer powerful solution
Models Implemented in Verilog-A
•
•
•
•
•
•
BSIM3, BSIM4.3, BSIMSOI
HiSIM, Shur-RPI TFT, EKV
HICUM
SPICE Gummel-Poon, Diode, JFET
Philips MEXTRAM, MOS 9, MOS 11
Triquent, Curtice, Parker-Skellern, Raytheon-Statz,
Angelov
• UCSD (Aspeck) GaAs HBT
Multiple Simulators, Single Model
• Compiled Verilog-A devices can be
shared among diverse simulators
• Same compiled object file linked to
each simulator
• Develop in one simulator, same
results in all simulators
BSIM3.cml
Tiburon Design Automation
Example: Adding Self-heating to BSIM3
• Adding a thermal circuit to a compact model can
be a complicated project, as all of the derivatives
with respect to the temperature must be provided
to the simulator.
• Since Verilog-A does that for the developer, the
additional lines of code are minimal, typically just
a few dozen, including the parameter definition.
Electrical Model for Self-heating
• An R-C circuit is added to
the intrinsic model
• The current source
represents the power
dissipated in the device
• The voltage across the
thermal resistance and
thermal capacitance
represents the associated
temperature rise
• This temperature rise is fed
back to the device model
Pdiss
Trise
Rth
Tiburon Design Automation
Cth
Verilog-A Implementation
• The code change is minimal
Tiburon Design Automation
DC I-V Results
• The (standard) BSIM3
compared to the
BSIM3 with selfheating
Tiburon Design Automation
Summary and Conclusions
• Development of scaled-MOS compact models
face many challenges: intrinsic and parasitic
device effects and “other” challenges:
– Intrinsic Limits--mobility, gate current, “leakage”
– RF Issues--NQS, substrate effects, noise
– Thermal Issues--new models, scaling laws
• Methodology for compact model deployment
shifting to HLL approach and compilers; “handcoded” models (for “efficiency”) inherently limit
portability
• “We live in interesting times (still!)”
Back-up Slides
• Power RF Table-based model (Root)
• Silicon RTD--physics and Verilog-A model
Resonant Tunneling
• Higher gate tunneling in DG than SG (bulk) MOS
• Simulated resonant gate tunneling current for thin layer
DG SOI by using NEMO: possibly Si-based resonant
tunneling diodes (RTD)
€
0.0 0.5 1.0 1.5 2.0
Vg (V)
€
Ig (uA/um)
DG (Tsi=5nm,tox=1.5nm)
SG
Ig (µA/µm)2
Ig (µA/µm)2
Ig (uA/um)
70
70
60
60
50
50
40
40
30
30
20
20
10
10
00
70 I=c1V[tan-1(c2V+c3)-tan-1(c2V+c4)]
70
+c5Vm+c6Vn
60
60
50
50
40
40
NEMO
compact model
30
30
20
20
10
10
00
0.0
0.5
1.0 1.5
Vg (V)
2.0
Advanced Device Development
• Verilog-A provides a
simple way to
implement new devices
• Resonant tunneling
diode
Tiburon Design Automation
Table-Based Models
• Table lookup + interpolation
• Separate models can easily be generated for different designs
– Possible due to efficient model generation
• Root Model
– Consists of 5 variables over the Vg-Vd space
– Igs, Ids, Qg, Qd, Idh
Im{ y11}
Im{ y12 }
∇QG =
v gs +
vds
ω
ω
Im{ y21}
Im{ y22 }
∇QD =
v gs +
vds
ω
ω
∇I Dh = Re{ y21}v gs + Re{ y22 }vds