A Generalized Approach for Harmonics and
Unbalanced Current Compensation through Inverter
Interfaced Distributed Generator
Jing Wang, Dalia D. Konikkara, A. Monti
Institute for Automation of Complex Power Systems
E. ON Energy Research Centre
Aachen, Germany
jwang, dkonikkara, amonti@eonerc.rwth-aachen.de
Abstract—Harmonics and unbalanced current compensation
in the distribution grid has become a major concern due to
connections of nonlinear and unbalanced loads and high
penetration of renewable energy sources. To tackle this problem,
the increasing integration of inverter interfaced distributed
generation (DG) may actually be considered able to provide
ancillary service for power quality support, if controlled and
regulated properly. The challenging part consists of precisely
extracting the current to be compensated in a fast dynamics and
accurately tracking the compensation reference as close and as
fast as possible. Most of the existing control methods are
developed for selected harmonics compensation, thus not
appropriate for the scenarios with wide range of harmonics due
to the increasing implementation complexity. Therefore, this
work proposes an approach to compensate harmonics and
unbalance in a generalized way aiming to correctly compensate
wide range of harmonics with less complexity and computation
effort. Simulation and hardware-in-the-loop (HIL) experiment
results are provided to validate the proposed approach.
extracted and then parallel P+Resonant (PR) controllers are
adopted to track the harmonic components. Although desirable
results are achieved with this compensation approach, it only
suits for selected harmonics and unbalance component thus not
suited for compensation of wide band of harmonic frequencies
[11]. Therefore, complete compensation techniques are
developed in [9][10], which extract the compensation reference
current in a generalized way and thus track the reference
current in a universal manner. However, some of them, e.g
methods based on Current´s Physical Component (CPC) [9],
Conservative Power Theory (CPT) [10] have drawbacks, such
as long time delay, complex implementation, and large
computation effort. Thus, as an alternative reference generation
solution of the second group, this work utilizes an advanced
PLL which can rapidly and accurately extract the fundamental
current component and therefore the compensation reference
current. A deadbeat type controller is customized to track the
compensation reference current.
Keywords—Harmonics
and
Unbalanced
Current
Compensation; Distributed Generation (DG); power quality support
The main contributions of the paper can be summarized as
follows:
I.
INTRODUCTION
Harmonics and unbalanced current compensation in the
distribution grid has become a major concern due to
connections of nonlinear and unbalanced loads and high
penetration of renewable energy sources. To tackle this
problem, the increasing integration of inverter interfaced
distributed generation (DG) may actually be considered able to
provide ancillary service for power quality support, if
controlled and regulated properly [1]. The idea of using the
inverter interfaced DG to improve the grid current quality is to
control the DG unit as a shunt Active Power Filter (APF),
where the DG absorbs the harmonic and unbalance current of
the nonlinear loads, improving the current quality in the grid
with lower total harmonic distortion (THD) [1]. To achieve this
goal, the harmonic and unbalance current in the load side must
be accurately extracted as current reference and then precisely
tracked by a current controller of inverter interfaced DG unit.
The challenging part consists of precisely extracting the
current to be compensated in a fast dynamics and accurately
tracking the compensation reference as close and as fast as
possible. Control techniques for grid harmonics and unbalance
current compensation may be classified into two groups
selective and complete compensation techniques [1][2].
Compensation methods using selective scheme are reported in
[1][4], in which the harmonic components are selectively
•
Proposal of a new control strategy for harmonics and
unbalance current compensation, which is more
flexible and effective than the selective approach.
•
Use of an advanced PLL to accurately extract the
current reference of harmonic and unbalance
components in a general way and with fast dynamics.
•
Design of a novel current control algorithm for a VSI
interfaced DG. First, a digital deadbeat current
controller with delay compensation has been designed
to achieve high bandwidth current control
characteristics. Secondly, the evaluations of the
closed-loop performance indicate good tracking
performance and robustness against parameter
variations with the proposed deadbeat controller.
•
Implementation, testing of the proposed harmonic
and unbalanced current compensation algorithm in
hardware-in-the-loop with the OPAL-RT platform,
thus proving the practical feasibility.
'978-1-4799-5115-4/14/$31.00 ©2014 IEEE'
II.
CONTROL SCHEME FOR HARMONICS AND UNBALANCED
CURRENT COMPENSATION
A. Compensation Schemes
The basic structure for harmonics and unbalanced current
compensation includes two parts: generation of the
compensation reference current and current controller for
tracking the compensation reference current. In the literature, if
a compensation reference current is generated in a selective
way, the multiple parallel P+Resonant controller is adopted to
selectively track the compensation reference current
[1][3][4][5].While a deadbeat type of controller is developed in
[9][10] to track the reference in a general way when the
complete approach is adopted to generate the compensation
reference current. The first scheme (selective reference
extraction + selective reference tracking) is developed for
selected harmonics and unbalanced compensation, thus not
appropriate for the scenarios with wide range of harmonics due
to the increasing implementation complexity [1]. Therefore,
this work proposes an approach (second scheme) to
compensate harmonics and unbalance current in a generalized
way aiming to correctly compensate wide range of harmonics
with less complexity and computation effort compared to the
existing complete compensation techniques.
B. Proposed Current Compensation Method
The inverter interfaced DG compensates the power quality
besides the primary function of fundamental current injection,
assuming that the available power rating of the DG is
sufficient. DG are distributed generators such as wind turbine,
PV, Fuel Cell and battery which forms the DC power supply
for the inverter system. When the DG is not operating in full
power conditions, the inverter may also operate as an APF to
be controlled for power quality support and fundamental
current injection.
The basic structure of the power quality compensation
scheme using Current Control is shown in Fig. 1. The figure
includes an inverter interfaced DG unit symbolized using a
DG source, a voltage source inverter and an LCL filter. The
Grid is represented using grid voltage, grid impedance and
signifies the load
harmonic and unbalanced loads where
current and the PCC voltage. As depicted, the fundamental
three phase reference current
is obtained from the power
control loop in the dq frame and the compensation reference
current for complete compensation is generated from the
advanced PLL.
vs
Zg
iL
io vo
io
vo
i
*
c
i
vg
vs
θ
i u* + h
i*af
i*a
*
b
iL
i
*
bf
i
*
cf
i*df
i*qf
vsf
P*
Q*
Fig. 1. Basic structure of the proposed control scheme.
A model-based deadbeat current controller, with predictive
compensation is designed to allow the output current of the
with accuracy and
filter to track the reference current
high bandwidth. The filtered fundamental voltage angle
information of PCC voltage θ is provided to guarantee the
injected fundamental current to synchronize with the grid
fundamental voltage. Fig. 4 depicts the information of the LCL
filter variables used for control purpose such as and .
The following two sections discuss the advanced PLL used
and the proposed deadbeat control algorithm.
III.
ALGORITHM OF THE ADVANCED PLL
A. An Overview of Detection Techniques for Extracting the
Compensation Harmonic and Unbalance Current
Detection techniques for extracting the needed
compensation harmonic and unbalance in the existing literature
may be classified into two groups: selective detection and
complete detection [2].
The first group is only valid for selected harmonics
compensation, thus not appropriate for the scenarios with wide
range of harmonics due to implementation complexity caused
by parallelization of multiple Phase-Lock-Loops (PLL) such as
multiple complex-coefficient-filter PLL (MCCF-PLL), secondorder generalized integrator PLL (SOGI-PLL) and decoupled
synchronous reference frame PLL (DSRF-PLL) [3][4][5].
Moreover, both MCCF and SOGI-PLL essentially perform
resonant filtering which implies possible problems of
sensitivity in the magnitude and the phase responses around the
resonance points [1]. As explained in [1], the DSRF-PLL uses
multiple feedback loops to separate the positive- and negativesequence components thus not appropriate for input harmonics.
Resonant filters are used as well to selectively extract the
harmonics; however, they introduce a large change of phase
angle around the resonance frequencies which results in
substantial phase errors in the extracted signals [1]. Adaptive
notch filter (ANF) is reported to isolate the selected harmonics
[7]; however, the drawbacks such as phase error around the
notch frequencies, and the large computational effort for
continuously tuning the coefficients of the notch filters limit its
application for the purpose of this work.
The second group performs complete harmonic extraction
and uses various methods based on either time domain or
frequency domain or a combination, to generate the
compensation reference current from a power theory
perspective [6]. Comparison of applicability of these methods
depending on goals of compensation as well as on expected
system conditions are summarized in [6] which shows to offer
very effective and a high degree of flexibility in compensation
applications [2]. However, some of them, e.g based on
Current´s Physical Component (CPC) [9], Conservative Power
Theory (CPT) [10] have drawbacks, such as complex
implementation, large computation effort and longtime delay.
Thus, as an alternative reference generation solution, the
second group utilizes an advanced PLL which can rapidly and
accurately extract the fundamental current component and
therefore the compensation reference current. The advanced
PLL is called Cascaded Delayed Signal Cancellation (CDSC)
PLL [8], and is used for fast selective harmonic detection.
However, the fundamental component is harmonic in a broad
sense, thus the fundamental component can be extracted with
CDSC PLL by choosing proper parameters.
B. Applied Advanced PLL
The CDSC-PLL discussed in [8] is adopted in this paper
due to its advantages over the previously mentioned methods.
The parameters of CDSC-PLL are properly designed here to
extract the fundamental current component and thereafter
obtain the reference current containing harmonics and
unbalance currents. The method uses a cascaded connection of
Delayed Signal Cancellation (DSC) subsystems as shown in
Fig. 2. The key idea behind it is the fact that different
frequencies in the same portion of time can be separated
through delay operation. Let us assume
/
is the
vector
delayed by / and lagging
by :
2
1
where
represents the fundamental period at the
fundamental frequency , and represents 2
, and
signifies harmonic order and targeted harmonic order which in
this case is +1 for fundamental component of current. When we
multiply the delayed vector by a chosen rotation angle , it
results in a rotated vector which along with the original vector
is used to construct the DSC operator as follows.
1
2
e
θ
2
1
3
2
2
4
represents the harmonic gain. Using trigonometric
identities and equating real and imaginary parts of (3) the
following equations can be obtained.
|cos
/2|
Fig. 2. Basic structure of CDSC-PLL.
Using this method, unwanted harmonics can be eliminated,
thus obtaining the fundamental component. Though it sounds
as a selective harmonic elimination method, studies show that
the PLL leads to automatic elimination of harmonics other
than the selected ones when appropriate parameters
(h=+3,+5,+9 and h*=1) are chosen. The rules to choose the
parameters are summarized as follows: 1) fix the targeted
order harmonic, and then to choose the first unwanted
harmonic and obtain the magnitude representation diagram of
the first DSC operator as the top one shown in Fig. 3; 2)
choose the second unwanted harmonic (gain equals to 1 in the
first DSC operator) and get the magnitude representation
diagram, and then pick the third unwanted harmonic (gain
equals to 1 in the first and the second DSC operators); 3) make
the cascaded CDS operators and get the complete magnitude
representation diagram and check if the unwanted harmonics
are cancelled; 4) if not, repeat the step 3. It is worth pointing
out that the advantage of this method is that the number of
CDSC subsystems equals to the number of harmonics to be
detected. Whereas in SOGI-PLL or DSRF-PLL, the number of
SOGI/DSRF subsystems equals the number of harmonics
present. Therefore to extract only the fundamental
components, SOGI/DSRF needs multiple subsystems, while
only one CDSC subsystem is required. A single CDSC-PLL
module is enough to extract the fundamental component and
thus significantly reduces the implementation complexity and
computation effort.
5
(6)
In order to eliminate unwanted harmonics , the gain
must be zero for all cases other than
for which the gain is
unity. Substituting
0 in (5),
2
can be obtained.
3, 5, 9 and
1, then
4, 8 and 16
Consider
respectively. Fig. 3 shows the magnitude representation of the
DSC operators and the CDSC-PLL. The first three plots show
the DSC operators for
4,
8 and
16 respectively.
The last part in the plot shows the cascaded operation of the
three DSC operators for fundamental current component
extraction. For the first DSC operator, harmonics such as +1, 3, +5 (gain equal to 1) are retained and harmonics such as +3,
+7 (gain equal to 0) are eliminated. The same principle holds
for the second and third DSC operators. The highlight in this
approach is, by trying to get rid of +3, +5 and +9 harmonics,
we can get rid of ±3, ±5, ±7, ±9, ±11and other higher order
harmonics (-1, -12, 13…). Even the magnitudes at the even
order and interharmonics (e.g 2.5th harmonic) may not be zero;
they are attenuated to a negligible amount [8]. Thus by
properly choosing h and h*, wide band of harmonics can be
eliminated. Fig. 2 shows the basic structure of a CDSC-PLL
with three DSC operators corresponding to n=4, 8 and 16. The
extracted fundamental component is then used to obtain the
as shown in the
unbalance and harmonic component
Figure 2.
Fig. 3. Diagrammatical magnitude representation of DSC and CDSC.
As seen in Fig. 2, the extracted fundamental component
is located by locking the zero-crossing point of the
fundamental component of the current , which indicates that
there is no phase shift (error) in the extracted fundamental
component. Therefore, using CDSC-PLL will not cause phase
error to the extracted harmonics and unbalance component like
resonance filter or notch filter does.
IV.
AN OVERVIEW OF THE CONTROL ALGORITHM FOR
POWER QUALITY IMPROVEMENT
A. Types of Current Controller
The main aim of a current controller of an inverterinterfaced DG is to provide accurate current tracking for the
reference current as fast and as close as possible. There are
different types of current controllers which have one advantage
over the other. The comparisons among them are summarized
in Table I.
TABLE I.
TYPES OF CONTROLLERS
Type of control
Stationary PR
control
Advantages
Zero phase error
Synchronous
PR/PI control
No phase lag
Hysteresis control
Fast transient
response
Fast transient
response
Deadbeat control
Disadvantages
Slow transient response; poor
compensation of high order
harmonics; complex tuning process
Slow transient response; nondefined robustness; poor
compensation of high order
harmonics
Unpredictable low order harmonics
Delay limits the bandwidth of
controller; sensitivities to plant
uncertainty
As the compensating reference current contains harmonics
at frequencies much higher than the fundamental one,
conventional current approaches (PR or PI controller) fail to
reach control goals such as minimization of the phase and
amplitude errors of reference tracking and fast dynamic
response [11]. Harmonics control by using parallel PR
controller is limited to the selected harmonics reference in the
chosen number and order, which is not appropriate for tracking
a reference with wide band of frequencies and without knowing
the number and order of the harmonics. In addition, higherorder harmonic tracking should be avoided with the multiresonance controller due to the limited bandwidth (higher than
13th) [1]. Hysteresis current controller has non-constant
switching frequency as main drawback. Due to this fact, the
spectrum of controlled current may contain various harmonics
that are hardly predictable. To overcome all these limitations, a
deadbeat type of controller featuring accurate refined tracking,
high bandwidth and less complexity is proposed for harmonic
compensation control.
B. Proposed Deadbeat Control
The basic idea of the proposed deadbeat controller is to use
the desired output to generate the desired control input
based on the controlled plant (inverter and LCL filter) shown in
Fig. 4.
implementation complexity without losing the accuracy of the
controlled plant. Meanwhile, it involves less plant parameters
which results in less sensitivity to plant parameter variations.
The well-known two-step delay caused by the computation of
the control algorithm and the PWM modulation are included,
thus the plant equations can be given as follows:
1
represents the two-step delay. Using Euler
where
Backward integration method, the discretized system can be
described as:
8
where
1
9
is the discretization time. Based on the above equation,
the control law can be formulated as follows:
2
1
2
10
If only one-step-ahead prediction is carried out to test the
proposed control scheme and the compensation effect, the one1 and voltage
1 are
step-ahead reference current
obtained using linear prediction as described in [11].
1
3
3
1
1
2
2
11
1
12
Two-step-ahead prediction of the reference current
and
the voltage , and one-step-ahead prediction of the output
current
are needed to compute the desired control input
. A prediction algorithm which estimates future
variables such as reference current and the measured current
and voltage has to be developed. Taking into account the
different characteristics of the estimated variables, specific
prediction method should be applied to predict or estimate each
of the future variables [11][13].
The output voltage is a slow and periodic varying signal
therefore the prediction of the voltage at the next time step
1 can be done by using first-order linear extrapolation
method. The prediction is based on available measured voltage
value at the time step k and the history sampling values, and it
can be formulated as in (12). The voltage at the time step
2 can be derived directly based on (12):
2
3
2
1
13
1 affects not only the
The prediction algorithm of
accuracy of prediction but also the stability of the entire
system. The estimation of the measured current is calculated
based on the system model due to the fact that the output
current has faster dynamic features compared to the voltage
and it is determined mainly by the system model. Therefore,
1 is
the prediction law for the current at the time step
proposed based on the real plant shown in (7). The prediction
law can be characterized as follows.
Fig. 4. Structure of one phase of the LCL filter.
In this work, the desired control input
is generated
is the
based on LC filter rather than LCL. In this case,
control input and
is the disturbance input, and
is the
output. As we have
, substituting this
equation into (7), we can observe that generating the control
input
using LC filter model is equivalent as using LCL filter
model. To put it another way, the LC model still contains the
information of the LCL filter model. Essentially, this way of
modeling reduces the system to second order thus reducing the
7
1
where
1
,
,
2
,
1
14
.
The reference current is stochastic and unknown, and depends
on the characteristics of the nonlinear load in the utility grid.
This feature makes the prediction of the reference current
difficult and more sophisticated algorithm should be developed
to accurately estimate the current especially when there is a
sudden change in the reference current. However, more
sophisticated prediction/estimation algorithm may need large
computation effort which gives problem of undesirable delay
[11]. The polynomial extrapolation method is reported in
[11][13] and has been proven to be an effective solution
considering accuracy and computation burden. Therefore, this
method is adopted in this work and a fourth-order two-stepahead extrapolation method is applied to guarantee the
estimation accuracy and not much computation effort, therefore
resulting in the following prediction formula:
2
1
2
Z −2
i* (k + 2)
∑
The optimization of the coefficients is part of the training
of the ANN, and the forecasted two-step-ahead reference
current will be the output. The whole training process must be
much faster than the control step (sampling step). This can be
satisfied due to the memory function of ANN during training,
then the optimized coefficients will be the same as long as no
sudden change in the reference current. If the output error
is over a tolerance then it is detected as a sudden reference
is used for
change, therefore, the reference current value
2 . The results of the estimated
the predicted value
reference current and the estimation error are presented in Fig.
6, which shows the forecasted current is exactly two steps
ahead the present value and the estimation error is small.
Current (A)
2
⁄
17
where
estimated io*(k+2)
present io*(k)
10
2 sampling steps
1.005
1.01
1.015
1.02
1
1.005
1.01
Time (s)
1.015
1.02
20
1
21
⁄
22
For good steady-state performance, that is, response in
finite settling time, the poles must be moved to the origin and
the final value theorem should be fulfilled for step response
[12]. Thus, |G(z)|z=1=1 has to be fulfilled. Further deriving the
shows that the poles are in the origin
transfer function
zero steady-state error. This condition is verified by the fact
that the magnitude of the transfer function is zero by
1.
substituting
10
0
-10
-20
-30
-40
-50
-60
-70
-80 1
10
2
10
Frequency (Hz)
3
10
Fig. 7. Bode diagram of the gain of the disturbance input (io(k)/vo(k))
The disturbance term results in an instantaneous tracking
error which is caused by the prediction errors of the voltage
1 ,
2 and
1 . For a sampling frequency of
5 kHz and for an operating frequency of 50 Hz, the error of
1 is 0.394% and
linear prediction for one-step-ahead
2 is 1.18%. The gain of the lumped
for two-step-ahead
0
1
19
1 the magnitude of the transfer function is 1.
and at
is a disturbance for the closed-loop system, the
As
transfer function
should be zero for accurate tracking and
e(k )
Fig. 5. The proposed current reference predictor using ANN.
Estimation error (A)
⁄
Magnitude (dB)
Z0
Z −1
Z −1
Z −1
Z −1
0.2
0
tracking error is indicated by the transfer function
-0.2
ANALYSIS OF THE PROPOSED DEADBEAT CONTROL
A. Control Performance Analysis
Based on the prediction methods, the following control law
is obtained:
2
1
(16)
2
,
2
3
. The
bode diagram is shown in Fig. 7 which denotes that the
tracking error is small considering the possible harmonic
components in the capacitance voltage.
Fig. 6. Results of the estimated two-step-ahead reference current.
where
The transfer function of the discretized closed-loop current
control is derived based on the plant (7) and the updated
control law (16), which can be written as
18
i* (k )
V.
.
15
where a, b, c, d and e are the coefficients to be optimized by
artificial neural network (ANN) which provides advantages
including very fast computation speed, adaptability to
changing parameters or even plant structure and high noise
immunity [13]. The proposed current reference predictor using
ANN is presented in Fig. 5 which is a three-layered back
propagation network consisting of 5 inputs, 3 nodes in hidden
layer and one output.
-0.4
2
3
4
-10
1
,
B. Robustness Analysis
Robustness to the variations of the plant parameters is an
important issue of the proposed deadbeat control since the
control law is obtained based on the plant model. As the main
variations of the plant parameters come from the inductance
and capacitance , robustness of the proposed controller is
investigated regarding to the variations of these two
parameters. If and are defined as parameters of the real
24
where
1
25
2
2
3
26
2
3
27
2
2
28
The magnitude Bode plot of the gain is used to evaluate the
tracking performance of the controller with variation of the
and . Fig. 8 shows that the curve of variations of
(80%
and 120%) overlaps with the case with perfect matched
parameters, which denotes that the variation of
has minor
influences on tracking performance of the deadbeat controller
compared to the perfect matched parameters. Variations of
have larger impact as shown in Fig. 8, while it is still within
the acceptable limits. It is worth to note that ±20% variation is
large considering inductance and capacitance can be produced
to have variation less than ±10% in practice [12]. Thus, the
tracking performance is degraded slightly with the mismatched
parameters.
A. Extraction of the Compensation Reference Current
(Simulation)
The load harmonics and unbalance currents are extracted
using the CDSC-PLL. The significantly distorted load side
current, the extracted fundamental current and the
compensation reference current are shown in Fig. 9. Fig. 9
shows that the advanced PLL can extract the fundamental
current within a short period (less than 0.01s) and good
transients as well. The FFT analysis presented in Fig. 9 shows
that the THD of the extracted fundamental current is 0.03%
while the original distorted current has THD value of 36.7%,
which implies the accurate extraction of the unbalance and
harmonic components from the distorted current thanks to the
CDSC theory.
40
20
0
-20
-40
0
20
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
0.01
0.02
0.03
0.04
0.05
Time (s)
0.06
0.07
0.08
0.09
0.1
0
-20
0
20
0
-20
0
Fig. 9. Extraction of compensation reference current.
16
THD=36.70%
THD=0.03%
14
Mag (% of Fundamental)
23
Load Current (A)
0
From the above equation, we can notice that only the
variation of has impact on the stability of the closed-loop
system. There are two roots, one is at origin, and the other is
equal to
/
. The absolute value of the
second root is always smaller than 1 within the variation range
of 10%~200% of
which means the stability is ensured. In
and
have no impact to the
conclusion, variations of
stability of the controlled system.
The effect of parameters variations on the transient
performance which is determined by the gain of the
disturbance input is investigated, and the transfer function is
formulated as following.
and further validation is carried out on a HIL OPAL-RT
platform. The system parameters used in simulation and
experiment are listed in the Appendix.
Harmonic &
Fundamental
Unbalance Current (A) Current (A)
plant,
and
are the estimated parameters for the control
algorithm. The characteristic equation of the closed-loop
system is rewritten and given as follows.
12
10
8
6
4
2
0
0
2
4
6
8
10
Harmonic Order
12
14
16
Fig. 10. FFT analysis of load and extracted fundamental current.
B. Harmonic and Unbalanced Current Compensation
(Simulation)
10
Iabc
Grid Current (A)
0
-20
-30
10
0
-10
-20
0
80% Cf,Lf
Cf, Lf
Cf, 80% Lf
Cf,120% Lf
120% Cf,Lf
-40
-50
-60
-70
-80 1
10
2
10
Frequency (Hz)
10
3
Fig. 8. Bode diagram of the gain of the disturbance input (io(k)/vo(k) under
parameters variations.
VI.
RESULTS AND DISCUSSION
The validation of the proposed control scheme includes two
parts: extraction of the compensation reference current and
harmonic and unbalanced current compensation with the
designed deadbeat current control. The simulation is
implemented and tested in real-time on an OPAL-RT platform,
0.02
0.04
0.06
0.08
0.1
0.12
0.08
0.1
0.12
Ioabc
10
Inverter injected
Current (A)
Magnitude (dB)
-10
20
5
0
-5
-10
0
0.02
0.04
0.06
Time (s)
Fig. 11. Grid and inverter injected current for unbalance compensation
In this simulation scenario, the grid current is unbalanced
due to the connection of an unbalanced load, and the DG is
connected to the main grid at 0.045s. The results are shown in
Fig. 11, which depicts that the unbalance in the grid caused by
the load is well compensated by the grid connected inverterinterfaced DG, which is connected at 0.045s.
In this simulation scenario, the grid current is severely
distorted by harmonic and unbalance currents and the DG is
connected to the main grid at 0.045s. The simulation results of
the proposed deadbeat control with two-step-ahead prediction
are provided for comparison.
Grid Current(A)
As shown in Fig. 12, using two-step-ahead prediction, the
grid current distortion is well compensated thanks to the good
tracking performance of the proposed deadbeat control. And
the THD value of the grid current as shown in Fig. 13 is
significantly reduced from 36.7% to 2.00% and within the
acceptable limit as per IEEE standard 519. The reference
tracking performance of the deadbeat controller in phase A is
presented in Fig. 12: it shows that the proposed deadbeat
controller tracks the reference current with slight tracking error
and delay but good and acceptable accuracy as demonstrated by
the THD of the compensated grid current.
50
0
-50
0
Reference &
Injection Current(A)
Fig. 14. Experimental results of extraction of compensation reference current
(blue: grid current, red:fundamental current, pink: harmonics and unbalance).
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
30
0.09
0.1
Reference Current
20
Injection Current
10
0
-10
-20
0.1
0.11
0.12
0.13
Time(s)
0.14
0.15
0.16
Fig. 12. Grid current (top), injected current and refernce current of phase
A(bottom).
16
THD=36.70%
THD=2.00%
Mag (% of Fundamental)
14
12
10
8
6
4
2
0
0
2
4
6
8
10
Harmonic Order
12
14
16
Fig. 13. FFT analysis of grid current before and after compensation.
C. Hardware-in-the-loop Experimental Verification
In order to validate the practical application of the proposed
compensation approach, a signal level HIL experimental
verification is carried out in OPAL-RT platform. In this HIL
platform, the power system and inverter models run in CPU,
the measurements (voltage and current) are sent to the
controller under test. A Field-Programmable Gate Array
(FPGA) is applied to implement the CDSC-PLL algorithm to
generate the compensation reference current, to calculate the
fundamental reference current and the deadbeat control
algorithm.The voltage reference for the inverter is sent back to
the CPU to generate the PWM for the inverter. The optimized
coefficients of ANN are directly applied in the reference
current prediction, thus no ANN algorithm is programmed in
FPGA. The experimental parameters are listed in the Appendix,
and the results are shown in Figure 14-16.
Fig. 15. Grid current before and after compensation (blue), reference current
(red), inverter injected curent (pink) and switching signal of DG (green).
The extraction of the compensation reference current shown
in Fig. 14 further validates that the CDSC-PLL can extract the
compensation reference current accurately. The THD value
(0.12%) is slightly larger than the simulation results due to the
problems in the practical implementation such as delay and
data conversion error in data transmission between CPU and
FPGA, data resolution and timing-delay of digital
implementation in FPGA. Fig. 16 shows the experimental
result of the grid current before (unbalanced) and after
compensation. It proves that the proposed control method can
compensate the grid unbalance current very well.
The experimental results of the grid current before
(unbalanced and harmonics) and after compensation are shown
in Fig. 15 which indicates that the grid current is well
compensated in a fast dynamics. The comparison between the
injected inverter current and the reference current shows that
there is a tracking error in the more distorted area in the
compensation reference current, while in the non-distorted area
the injected current tracks the reference current perfectly. The
THD of the grid current after compensation is 2.54%, which is
acceptable as per IEEE standard 519.
Fig. 16. Grid current before (unbalanced) and after compensation.
The experimental results clearly show that the proposed
approach can compensate the harmonic and unbalance current
with excellent performance.
D. Discussion
The CDSC-PLL can be used to extract the fundamental
current component accurately if the parameters of CDSC-PLL
are properly designed. However, sub-harmonics (e.g 2.5 order)
cannot completely be cancelled but only attenuated to some
extent, which results in tracking error for the compensation
reference current. This can be considered the limitation of this
method. The other limiting factors for the inverter-interfaced
DG to compensate the harmonics and unbalance in the grid
current are the power rating of the DG and the tracking
accuracy of the deadbeat controller. The simulation result
shows that the errors in the two-step-ahead prediction
1 and output
2 , output current
(reference current
2 and
1 ) cause tracking error (it is
voltage
acceptable from the results) with the proposed deadbeat
controller. In addition, the non-ideality in the practical
implementation such as delay in data transmission, error in data
conversion, and data resolution in digital computation cause
tracking error as well. However, the compensation effects are
satisfactory as seen from the simulation and experimental
results, and the simplicity of implementation and effectiveness
shows the proposed method is a good solution for grid
harmonics and unbalance current compensation.
VII. CONCLUSION
This work presents a generalized approach for harmonics and
unbalance current compensation through inverter interfaced
DG. The proposed control scheme is composed of an
advanced PLL and a deadbeat current controller. Compared to
the commonly used SOGI and DSRF PLL, the adopted
advanced PLL can extract the compensation reference current
more accurately and rapidly, and the implantation and
computation effort of the PLL is much reduced. The proposed
predictive deadbeat controller has accurate reference tracking
performance for a wide band of frequencies with fast
dynamics and less implementation complexity. The simulation
and experimental results show that the proposed compensation
scheme of DG can improve the power quality (current) with
fast dynamics, satisfactory accuracy and good transient
behavior. Therefore the proposed control scheme is validated
to be an effective solution for unbalanced harmonics current
compensation.
0.4mH, power reference
200μs, DC link voltage
0 var,
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APPENDIX
Supply: Nominal grid line-line voltage at the PCC=400V at 50
Hz; Inverter:
0.15Ω,
1.8mH,
30μF,
0.1Ω,
2 kW,
750 V.
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