ELEC 2200-002
Digital Logic Circuits
Fall 2015
Delay and Power
Vishwani D. Agrawal
James J. Danaher Professor
Department of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
http://www.eng.auburn.edu/~vagrawal
vagrawal@eng.auburn.edu
Fall 2015, Nov 30
ELEC2200-002 Lecture 8
1
Power and Delay of a Transition
Ron
VDD
ic(t)
vi (t)
vo(t)
CL
R = large
Ground
CL =
Total load capacitance for gate; includes transistor capacitances
of driving gate + routing capacitance + transistor capacitances
of driven gates; obtained by layout analysis.
Fall 2015, Nov 30
ELEC2200-002 Lecture 8
2
Charging of a Capacitor
R = Ron
t=0
v(t)
i(t)
C = CL
VDD
Charge on capacitor, q(t)
=
C v(t)
Current, i(t)
=
C dv(t)/dt
Fall 2015, Nov 30
=
dq(t)/dt
ELEC2200-002 Lecture 8
3
i(t)
=
C dv(t)/dt =
dv(t)
∫ ───── =
VDD – v(t)
ln [VDD – v(t)] =
[VDD – v(t)] /R
dt
∫ ────
RC
–t
── +
RC
A
Initial condition, t = 0, v(t) = 0 → A = ln VDD
–t
v(t) = VDD [1 – exp(───)] = 0.5VDD
RC
t = 0.69 RC
Fall 2015, Nov 30
ELEC2200-002 Lecture 8
4
Delay: Definitions
Rise time is the time a signal takes to rise from 10% to 90% of its
peak value.
Fall time is the time a signal takes to drop from 90% to 10% of its
peak value.
Delay of a gate or circuit is the time interval between the input
crossing 50% of peak value and the output crossing 50% of peak
value.
VDD
90% VDD
A
Fall time
10% VDD
GND
1→0
A
NOT
gate
Time
Gate delay
B
0→1
VDD
90% VDD
B
GND
Fall 2015, Nov 30
Rise time
10% VDD
ELEC2200-002 Lecture 8
Time
5
Inverter: Idealized Input
INPUT
VDD
GND
Gate delay
OUTPUT
VDD
0.5VDD
GND
Fall 2015, Nov 30
time
t =0
0.69CR
ELEC2200-002 Lecture 8
6
Timing of a Digital Circuit
Most digital circuits are clocked
synchronous finite state machines (FSM).
Primary
Inputs
FF
FF
FF
Combinational circuit
(Gates interconnected
without feedback)
Primary
Outputs
FF
Clock
FF
FF
Fall 2015, Nov 30
ELEC2200-002 Lecture 8
7
Large Circuit Timing Analysis
Determine gate delays:
From layout analysis, or use approximate delays:
– Gate delay increases in proportion to number of fanouts
(increased capacitance)
– Delay decreases in proportion to increase in gate size
(reduced transistor channel resistance)
Purpose of analysis is to verify timing behavior –
determine maximum speed of operation.
Methods of analysis:
Circuit simulation – most accurate, expensive (Spice program)
Static timing analysis (STA) – most efficient, approximate
Fall 2015, Nov 30
ELEC2200-002 Lecture 8
8
Static Timing Analysis (STA)
Combinational logic for critical path delays.
Circuit represented as an acyclic directed
graph (DAG).
Gates characterized by delays; gate
function ignored.
No inputs are used – worst-case analysis
– static analysis (simulation would be
dynamic).
Fall 2015, Nov 30
ELEC2200-002 Lecture 8
9
Combinational Circuit of an FSM
A
1
H
1
Gate delay
B
1
E
4
G
1
Fanout
=4
C
2
F
2
J
1
D
1
Input to Output delay must not exceed clock period
Fall 2015, Nov 30
ELEC2200-002 Lecture 8
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Static Timing Analysis (STA) Step 1
Levelize circuit. Initialize arrival times at primary inputs to 0.
0
0
0
0
0
0
0
0
Level 0
Fall 2015, Nov 30
A
1
B
1
H
1
E
4
G
1
C
2
J
1
F
2
D
1
1
Level of a gate is one greater than
the maximum of fanin gate levels
2
3
ELEC2200-002 Lecture 8
4
5
11
Static Timing Analysis (STA) Step 2
Determine output arrival times of gates in level order.
0
0
0
0
0
0
0
0
Level 0
Fall 2015, Nov 30
1
A
1
B
1
1
E
4
C
2
6
1
G
1
9
J
1
9
2
F
2
D
1
10
H
1
1
8
Arrival time at a gate output
= maximum of input arrivals + gate delay
2
3
ELEC2200-002 Lecture 8
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5
12
Static Timing Analysis (STA) Step 3
Trace critical paths from the output with longest arrival time.
0
0
0
0
0
0
0
0
Level 0
Fall 2015, Nov 30
1
A
1
B
1
1
E
4
C
2
6
1
9
G
1
2
F
2
D
1
10
H
1
1
9
J
1
8
Critical path: C, E, F, G, H; delay = 10
2
3
ELEC2200-002 Lecture 8
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5
13
Power in CMOS Logic (Inverter)
VDD
No current flows
from power supply!
Where is power
consumed?
GND
F. M. Wanlass and C. T. Sah, “Nanowatt Logic using Field-Effect
Metal-Oxide-Semiconductor Triodes,” IEEE International SolidState Circuits Conference Digest, vol. IV, February 1963, pp.
32-33.
Fall 2015, Nov 30
ELEC2200-002 Lecture 8
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Three Components of Power
Dynamic, when output changes
– Signal transitions (major component)
Logic activity
Glitches
– Short-circuit (small, often neglected)
Static, when signal is in steady state
– Leakage (small)
Ptotal =
=
Fall 2015, Nov 30
Pdyn + Pstat
Ptran + Psc + Pstat
ELEC2200-002 Lecture 8
15
Charging of Output Capacitor
From Slide 4:
v(t) =
i(t)
Fall 2015, Nov 30
=
–t
V [1 – exp( ── )]
RC
dv(t)
C ───
dt
=
V
–t
── exp( ── )
R
RC
ELEC2200-002 Lecture 8
16
Total Energy Per Charging
Transition from Power Supply
Etrans =
=
Fall 2015, Nov 30
∞
∫ V i(t) dt =
0
CV
∞ V
2
–t
∫ ── exp( ── ) dt
0 R
RC
2
ELEC2200-002 Lecture 8
17
Energy Dissipated Per Transition in
Transistor Channel Resistance
∞2
R ∫ i (t) dt
0
Fall 2015, Nov 30
=
V ∞
-2t
R ──
∫ exp( ── ) dt
2
R 0
RC
=
1
2
─ CV
2
2
ELEC2200-002 Lecture 8
18
Energy Stored in Charged Capacitor
∞
∞
-t V
-t
∫ v(t) i(t) dt = ∫ V [1-exp( ── )] ─ exp( ── ) dt
0
0
RC R
RC
1
2
= ─ CV
2
Fall 2015, Nov 30
ELEC2200-002 Lecture 8
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Transition Power
Gate output rising transition
– Energy dissipated in pMOS transistor = ½CV
2
– Energy stored in capacitor = ½CV
2
Gate output falling transition
– Energy dissipated in nMOS transistor = ½ CV
Energy dissipated per transition = ½ CV
Power dissipation:
2
2
Ptrans =
Etrans α fck =
½ α fck CV
α = activity factor = prob.(gate has transition)
fck = clock frequency
2
Fall 2015, Nov 30
ELEC2200-002 Lecture 8
20
Power Density of a Chip
Assume dynamic power is major component.
2
Power density = ½ α fck CV × gate density
C = average gate capacitance
Gate density = number of gates per unit area
Example: α = 0.5, fck = 1GHz, C = 1pF,
V = 1 volt, gate density = 1 million gates/cm2
Power density = 250 watts/cm2
Fall 2015, Nov 30
ELEC2200-002 Lecture 8
21
CMOS Gate Power
R = Ron
V
i(t)
vi (t)
Large
resistance
v(t)
Output signal
transition
v(t)
i(t)
Dynamic
current
isc(t)
Short-circuit
current
C
isc(t)
Ground
Leakage
current
Leakage
current
time
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ELEC2200-002 Lecture 8
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References
Delay modeling, simulation and testing:
– M. L. Bushnell and V. D. Agrawal, Essentials of Electronic
Testing for Digital, Memory and Mixed-Signal VLSI Circuits,
Springer, 2000.
Timing analysis and design:
– G. De Micheli, Synthesis and Optimization of Digital Circuits,
McGraw-Hill, 1994.
– N. Maheshwari and S. S. Sapatnekar, Timing Analysis and
Optimization of Sequential Circuits, Springer, 1999.
PrimeTime (A static timing analysis tool):
– H. Bhatnagar, Advanced ASIC Chip Synthesis, Second
Edition, Springer, 2002
CMOS digital circuit power:
– A. Chandrakasan and R. Brodersen, Low-Power Digital CMOS
Design, Boston: Springer, 1995.
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ELEC2200-002 Lecture 8
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